CN103716517A - Nios II-based high-speed image acquisition system - Google Patents
Nios II-based high-speed image acquisition system Download PDFInfo
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- CN103716517A CN103716517A CN201310692642.8A CN201310692642A CN103716517A CN 103716517 A CN103716517 A CN 103716517A CN 201310692642 A CN201310692642 A CN 201310692642A CN 103716517 A CN103716517 A CN 103716517A
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Abstract
The invention relates to a Nios II-based high-speed image acquisition system comprising a pick-up head, an input video decoding chip, an FPGA chip, an output video decoding chip and a video displayer. The pick-up head is connected with the FPGA chip via the input video decoding chip. The FPGA chip is connected with the video displayer via the output video decoding chip. According to the Nios II-based high-speed image acquisition system, a NiosII soft-core processor and relevant interface modules are configured on the FPGA chip so that main hardware circuits of the system are realized. Besides, the high-speed multi-functional video decoding chips and encoding chips are controlled in combination with software design of the system so that functions like high-speed A/D and D/A conversion and storage of images are realized.
Description
Technical field
The present invention relates to the field of video image, especially a kind of high-speed image acquisition system based on Nios II.
Background technology
Digital image processing techniques are very extensive in the application of telecommunications and field of information processing, and the high speed acquisition that how to realize digital picture is one of key technology of Digital Image Processing.Along with numeral and development and the progress of multimedia technology, in the fields such as that digital image processing techniques are widely used in is military, civilian, commercialization and industrial production.People can obtain image from observed scene by various observation systems, comprising: camera and the camera system of taking various scenes; Observe the micro-image system of small cell; The satellite multispectral scanner imaging system of earth surface; X ray computer tomography ray system etc.No matter these images are in imaging, storage, transmitting procedure, or in analyzing, all must adopt a lot of digital image processing methods.
The defects such as the image capturing system using at present exists image processing speed slow, and autgmentability is poor.
Summary of the invention
The technical problem to be solved in the present invention is: in order to overcome the problem of above-mentioned middle existence, provide a kind of high-speed image acquisition system based on Nios II, its project organization rationally, realized the functions such as high-speed transitions box storage of image
The technical solution adopted for the present invention to solve the technical problems is: a kind of high-speed image acquisition system based on Nios II, comprise camera, input video decoding chip, fpga chip and output video decoding chip and video display, described camera is connected with fpga chip by input video decoding chip, and fpga chip is connected with video display by output video decoding chip.
Described fpga chip comprises Nios II CPU, is articulated in Avalon bus, I on Nios II CPU
2c configuration interface module, input FIFO control interface, output FIFO control interface, TV encoder, input dma controller, output DMA controls and memory control interface and for receiving the general parallel interface of key information, described I
2c configuration interface module is connected with input video decoding chip, and the input of input FIFO control interface is connected with input video decoding chip, described Avalon bus respectively with I
2c configuration interface module, input FIFO control interface, output FIFO control interface, input dma controller, output DMA control, memory control interface, for receiving the general parallel interface of key information, be connected, output FIFO control interface output is connected with TV encoder, TV encoder output is connected with output video decoding chip, and general parallel interface input is connected with control button.
Described fpga chip is circumscribed with view data memory module, and view data memory module is connected with the memory control interface in fpga chip.
The model of described input video decoding chip is ADV7181.
The model of described output video decoding chip is ADV7123.
The invention has the beneficial effects as follows, a kind of high-speed image acquisition system based on Nios II of the present invention, on fpga chip, configure the main hardware circuit that NiosII soft-core processor and relevant interface module realize system, and the Software for Design of coupling system is controlled high-speed multifunctional video decoding chip, coding chip and has been realized high-speed a/d, the D/A conversion of image and the function such as storage.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the present invention is further described.
Fig. 1 is structural representation of the present invention;
Fig. 2 is the flow chart of systems soft ware of the present invention.
1. cameras in figure, 2. input video decoding chip, 3.FPGA chip, 31.Nios II CPU, 32.Avalon bus, 33.I
2c configuration interface module, 34. input FIFO control interfaces, 35. output FIFO control interfaces, 36.TV encoder, 37. input dma controllers, 38. output dma controllers, 39. memory control interfaces, 310. general parallel interfaces, 4. output video decoding chip, 5. video display, 6. view data memory module, 7. controls button.
Embodiment
In conjunction with the accompanying drawings, the present invention is further detailed explanation.These accompanying drawings are the schematic diagram of simplification, basic structure of the present invention is only described in a schematic way, so it only show the formation relevant with the present invention.
A kind of high-speed image acquisition system based on Nios II as shown in Figure 1, comprise camera 1, input video decoding chip 2, fpga chip 3 and output video decoding chip 4 and video display 5, camera 1 is connected with fpga chip 3 by input video decoding chip 2, and fpga chip 3 comprises Nios II CPU31, is articulated in Avalon bus 32, I on Nios II CPU31
2c configuration interface module 33, input FIFO control interface 34, output FIFO control interface 35, TV encoder 36, input dma controller 37, output dma controller 38 and memory control interface 39 and for receiving the general parallel interface 310 of key information, I
2c configuration interface module 33 is connected with input video decoding chip 2, and the input of input FIFO control interface 34 is connected with input video decoding chip 2, Avalon bus 32 respectively with I
2c configuration interface module 33, input FIFO control interface 34, output FIFO control interface 35, input dma controller 37, output dma controller 38, memory control interface 39, for receiving the general parallel interface 310 of key information, be connected, output FIFO control interface 35 outputs are connected with TV encoder 36, TV encoder 36 outputs are connected with output video decoding chip 4, fpga chip 3 is connected with video display 2 by output video decoding chip 4, fpga chip 3 is circumscribed with view data memory module 6, view data memory module 6 is connected with the memory control interface 39 in fpga chip 3, general parallel interface 310 inputs are connected with controls button 7.
The model of input video decoding chip 2 is ADV7181, ADV7181 is a multi-functional high-speed video decoding chip of low-power, this chip can detect automatically and the PAL NTSC of transfer standard and the composite video signal of Sequential Color and Memory system formula are the composite video digital signal of TTU656 YUV4:2:2 form, ADV7181 inside has 240 control registers, can set and realize by configuring these control registers the various functions of ADV7181, its ADV7181 to deposit parameter configuration as follows:
| Register address | 00h | 04h | 08h | 0Ah | 0Eh | 0Ah | 10h | 11h | 15h | 17h |
| The parameter arranging | 50h | 02h | 60h | 18h | 05h | 00h | 00h | 00h | 00h | 04h |
| Register address | 2Bh | 2Ch | 2Dh | 2Eh | 2Fh | 30h | 31h | 32h | 33h | 37h |
| The parameter arranging | 00h | 8Ch | F2h | EEh | F4h | D2h | 12h | 81h | 84h | A0h |
| Register address | 3Ah | 50h | 51h | 52h | 53h | 54h | 58h | 77h | 7Ch | 7Dh |
| The parameter arranging | 16h | 04h | 20h | 18h | 00h | 00h | EDh | C5h | 93h | 00h |
| Register address | C3h | C4h | D0h | D5h | D7h | E4h | E5h | E6h | E7h | EAh |
| The parameter arranging | 05h | 80h | 48h | A0h | EAh | 3Eh | 80h | 03h | 85h | 0Fh |
The control register of ADV7181 is to pass through I
2c bus mode realizes configuration, and the base address of configuration is 40h, owing to not comprising I in the IP storehouse carrying at SOPC Builder
2c configuration interface module, carries out special design so this module need to design specially according to the register feature of configuring chip and functional requirement.
A kind of high-speed image acquisition system based on Nios II of the present invention, gathers after key when pressing, through I
2the video decoding chip ADV7181 of C configuration decodes the analog video signal of camera output, and from output, give input FIFO control interface 34 and carry out first-in first-out formula buffer memory, when the data of input FIFO storage reach the capacity thresholding of setting, to inputting after dma controller reception is asked, just complete and once input FIFO to the DMA transmission between view data memory module 6, wherein view data memory module 6 controllers are interfaces of Avalon bus and view data memory module 6 memories, repeatedly repeating to input FIFO transmits to the DNA between view data memory module 5, until press, gather stop key position, just realized the acquisition function of image, after playback key is pressed, first system starts a view data memory module 6 by output dma controller 38 and transmits to the DMA that exports FIFO control interface 35, TV encoder colleague exports ADV7123 after output FIFO output yuv format digital signal is converted to rgb format, by it, carry out VGA decoding and output to VGA display.
A kind of high-speed image acquisition system based on Nios II as shown in Figure 2, after this system starts, carry out initial work, initialize routine mainly completes the register configuration of ADV7181, the fifo buffer of initialization DMA passage and clear FIFO control interface, subsequently, system enters major cycle state, and detect button, when collection button being detected, start FIFO control interface and start save data, when data-avaiblc being detected when effective, start and once input DMA transmission, so circulation, until stop key detected, press, just realized video data easy to operate, by simple transformation, can also complete single slit diffraction, the experiments such as two-slit interference, suitable Scientific Research in University Laboratory application.
The above-mentioned foundation desirable embodiment of the present invention of take is enlightenment, and by above-mentioned description, relevant staff can, within not departing from the scope of this invention technological thought, carry out various change and modification completely.The technical scope of this invention is not limited to the content on specification, must determine its technical scope according to claim scope.
Claims (5)
1. the high-speed image acquisition system based on Nios II, it is characterized in that: comprise camera (1), input video decoding chip (2), fpga chip (3) and output video decoding chip (4) and video display (5), described camera (1) is connected with fpga chip (3) by input video decoding chip (2), and fpga chip (3) is connected with video display (2) by output video decoding chip (4).
2. a kind of high-speed image acquisition system based on Nios II according to claim 1, is characterized in that: described fpga chip (3) comprises Nios II CPU(31), be articulated in Nios II CPU(31) on Avalon bus (32), I
2c configuration interface module (33), input FIFO control interface (34), output FIFO control interface (35), TV encoder (36), input dma controller (37), output dma controller (38) and memory control interface (39) and for receiving the general parallel interface (310) of key information, described I
2c configuration interface module (33) is connected with input video decoding chip (2), input FIFO control interface (34) input be connected with input video decoding chip (2), described Avalon bus (32) respectively with I
2c configuration interface module (33), input FIFO control interface (34), output FIFO control interface (35), input dma controller (37), output dma controller (38), memory control interface (39), for receiving the general parallel interface (310) of key information, be connected, output FIFO control interface (35) output is connected with TV encoder (36), TV encoder (36) output is connected with output video decoding chip (4), and general parallel interface (310) input is connected with controls button (7).
3. a kind of high-speed image acquisition system based on Nios II according to claim 2, it is characterized in that: described fpga chip (3) is circumscribed with view data memory module (6), view data memory module (6) is connected with the memory control interface (39) in fpga chip (3).
4. a kind of high-speed image acquisition system based on Nios II according to claim 1, is characterized in that: the model of described input video decoding chip (2) is ADV7181.
5. a kind of high-speed image acquisition system based on Nios II according to claim 1, is characterized in that: the model of described output video decoding chip (4) is ADV7123.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106454215A (en) * | 2016-04-26 | 2017-02-22 | 安徽师范大学 | High speed video data acquisition display system and display method |
| CN110365945A (en) * | 2019-07-24 | 2019-10-22 | 成都甄识科技有限公司 | A kind of cellular camera front end data acceleration system |
| CN110933333A (en) * | 2019-12-06 | 2020-03-27 | 河海大学常州校区 | Image acquisition, storage and display system based on FPGA |
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| US20120124588A1 (en) * | 2006-12-01 | 2012-05-17 | Synopsys, Inc. | Generating Hardware Accelerators and Processor Offloads |
| CN202696739U (en) * | 2012-05-11 | 2013-01-23 | 中国矿业大学 | HD (high definition) low-power dissipation embedded video server |
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| US20120124588A1 (en) * | 2006-12-01 | 2012-05-17 | Synopsys, Inc. | Generating Hardware Accelerators and Processor Offloads |
| CN202696739U (en) * | 2012-05-11 | 2013-01-23 | 中国矿业大学 | HD (high definition) low-power dissipation embedded video server |
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| 袁海林: ""基于Nios Ⅱ的高速图像采集系统的设计"", 《电子器件》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106454215A (en) * | 2016-04-26 | 2017-02-22 | 安徽师范大学 | High speed video data acquisition display system and display method |
| CN110365945A (en) * | 2019-07-24 | 2019-10-22 | 成都甄识科技有限公司 | A kind of cellular camera front end data acceleration system |
| CN110933333A (en) * | 2019-12-06 | 2020-03-27 | 河海大学常州校区 | Image acquisition, storage and display system based on FPGA |
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Application publication date: 20140409 |