CN103685103A - Integral verification platform based on FPGA communication base bands - Google Patents
Integral verification platform based on FPGA communication base bands Download PDFInfo
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Abstract
The invention discloses an integral verification platform based on FPGA communication base bands. The integral verification platform comprises a software base band part and a hardware base band part which are connected through the UDP protocol of the Ethernet. The software base band part is a base band algorithm software simulation module implemented through corresponding software. The hardware base band part is a base band hardware module built on the basis of an FPGA board and comprises a radio frequency module and a base band processing module, wherein the radio frequency module is used for transceiving wireless signals, and the base band processing module is used for processing base band signal data. By the platform, software and hardware advantages are combined, software simulation can be performed in actual communication environments, the hardware verification results can be displayed visually and in real time in a software interface, independent algorithm verification and hardware verification of corresponding base band modules can be performed without the completion of the whole base band system, the problems in independent modules can be discovered by designers conveniently, and the design efficiency of base bands can be increased.
Description
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Technical field
The present invention relates to communicate by letter baseband functions emulation and performance verification technical field, more specifically, relate to a kind of integrated verification platform of the communication base band based on FPGA.
Background technology
In recent years, along with the extensive use of wireless communication technology, wireless communication chips designs is rapid, and in communication chip design, a most important ring is exactly the design of base band of communicating by letter.In design process, can base band normally work, and whether reaches the function of expection, needs corresponding checking and test platform to detect.Current existing base band verification platform method mainly contains two kinds, and the first is utilized software emulation exactly, by software modeling analog communication system, carries out corresponding base band proof of algorithm.The second downloads on FPGA plate after exactly base band algorithm being finished writing with hardware program language, under practical communication environment, directly carries out hardware verification.These two kinds of methods are conventional modes in current base band checking, general communication baseband design all can be used this two kinds of methods, first in early stage, use high-level language (C, C++, Matlab) carry out the software emulation checking of algorithm, after being verified, then convert high-level language to hardware program language (Verilog, VHDL) under, be loaded on FPGA plate, carry out the detection of practical communication environment.
Chip checking is the committed step of whole chip design, is related to the success or failure of whole chip design task, and these two kinds of chip verification methods are verification methods conventional in current chip verification technique.
Two kinds of current conventional verification methods above-mentioned, the first utilizes the software emulation checking can be effectively and verify efficiently the correctness of base band algorithm.First verification step is to use high-level language (as C++, Matlab) algorithm of the modules of base band (as mapping and demapping module) is write out, then the module of writing out is utilized simulation software (as Simulink) to carry out the simulating, verifying under analog communication environment.When emulation, need to carry out Channel Modeling to wireless communications environment, simulate interchannel noise, channel fading with situations such as channel disturbance.Due to communication environment be approximate simulation out, simultaneously for some factor as transceiver two ends carrier frequency frequency deviation be to be difficult to simulation, so software emulation completely actual response go out the signal intelligence of channel, cause the real result deficiency of checking.
The second hardware verification mode, etc. that all modules of base band are all by after above-mentioned software emulation checking, use again corresponding EDA design software (as Quartus) by its for modules hardware program language (as VHDL, Verilog) describe, and then be loaded into FPGA development board and carried out corresponding hardware verification.This base band verification mode can verify the whole baseband module designing under actual communication environment, not directly perceived but this verification mode exists verification msg to show, and the shortcoming of very flexible.Data show not directly perceived, being embodied in us need to use corresponding tester (as spectrum measurement instrument, oscilloscope etc.) to carry out Real-Time Monitoring to the data in communication, after the hardware designs that very flexible is embodied in all baseband modules such as needs all completes, could unify whole baseband system to carry out hardware verification, and can not verify the single module in baseband system, will cause like this when mistake appears in baseband communication module, can not accurately navigate to is fast which module occurs abnormal.
Above-mentioned the first software verification mode completely actual response goes out the result under practical communication environment, and the second hardware verification mode technology can not allow design engineer find in time and intuitively the problem that in design process, each baseband module occurs, thereby cause design efficiency low.Simultaneously due to these two kinds of verification modes, one is the checking when baseband chip algorithm Front-end Design, one is the checking of having carried out after baseband chip design hardware language has designed, and these two kinds of verification methods can not combine simultaneously the software verification result of baseband module and hardware verification result are carried out to real-time comparative analysis.
Summary of the invention
In order to address the above problem, the present invention proposes a kind of integrated verification platform of the base band of communicating by letter, and realize and baseband module is carried out to software verification and hardware verification simultaneously, and viewing hardware verification msg directly perceived, be beneficial to the accurate alignment error of designer position.
To achieve these goals, technical scheme of the present invention is:
A kind of integrated verification platform of the communication base band based on FPGA, comprise software baseband processing module, hardware baseband processing module and radio-frequency module, described software baseband processing module is by adopting the Ethernet of UDP host-host protocol to be connected with hardware baseband processing module, and hardware baseband processing module is connected with radio-frequency module by ad/da converter;
Described hardware baseband processing module comprises transmission hardware baseband processing unit and reception hardware baseband processing unit, and radio-frequency module comprises radio frequency transmitting element and rf receiver unit; Described transmission hardware baseband processing unit is connected with radio frequency transmitting element by DA transducer, receives hardware baseband processing unit and is connected with rf receiver unit by AD converter;
Described transmission hardware baseband processing unit comprises microcontroller, ethernet physical layer PHY, ethernet controller MAC, data storage controller DSC, send FIFO subelement and send base band subelement, the output of ethernet physical layer PHY is connected with the input of ethernet controller MAC, the output of ethernet controller MAC is connected with the input of data storage controller DSC, the output of data storage controller DSC is connected with the input that sends FIFO subelement, the output that sends FIFO subelement is connected with the input that sends base band subelement, the output that sends base band subelement is connected with radio frequency transmitting element by DA transducer, microcontroller respectively with net controller MAC too, data storage controller DSC connects, and in described ethernet controller MAC, is also provided with broadcast packet filter,
Described reception hardware baseband processing unit comprises microcontroller, ethernet physical layer PHY, ethernet controller MAC, data storage controller DSC, receive FIFO subelement and receive base band subelement, the input of ethernet physical layer PHY is connected with the output of ethernet controller MAC, the input of ethernet controller MAC is connected with the output of data storage controller DSC, the input of data storage controller DSC is connected with the output that receives FIFO subelement, the input that receives FIFO subelement is connected with the output that receives base band subelement, the input that receives base band subelement is connected with radio frequency transmitting element by DA transducer, microcontroller respectively with net controller MAC too, data storage controller DSC connects.
The present invention, by software baseband processing module, hardware baseband processing module and radio-frequency module integrated design, can relate to the data-handling efficiency of MCU and the port of each module and connect and data transmission problems in the process of integrated design.
In order to improve the treatment effeciency of MCU, use MAC broadcast packet filter and DSC, problem for port transmission coupling, use FIFO buffer, in order to overcome the data transmission problems between soft and hardware baseband processing module, employing Ethernet connects, and Ethernet is to adopt the UDP host-host protocol with feedback mechanism.
The inner setting principle of hardware baseband processing module of the present invention is:
(1) because software baseband processing module is generally the PC end with 100 m ethernet, so can send a large amount of broadcast datas, and the disposal ability of MCU is limited, a large amount of broadcast datas can take too much MCU resource, in order to improve the efficiency of MCU, alleviate the load of MCU, so use broadcast packet filter to filter out the useless broadcast message in PC end transmission information at MAC layer, make MCU receive only useful IP Information On Demand.
(2) in baseband hardware processing module, use the storage of DSC(Data storage controller data to control) module completes the transfer of data between FIFO and mac controller.DSC is a kind of DMA(of being similar to direct memory access) technology.DMA is a kind of internal storage access technology in computer science, when not using DMA, will complete external equipment IO mouth must be through CPU to the visit data stream of memory, and DMA technology allows externally direct read/write data between equipment and memory, neither by CPU, do not need CPU to intervene yet.What the DSC in same the present invention realized is that between FIFO and MAC, direct data are directly transmitted, and MCU only need be responsible for the header portion of deal with data report, and a large amount of data realize directly transmission by DSC.Specific works mode is as follows: when hardware baseband processing module transmits data toward software baseband processing module, first MCU is ready for the datagram header portion of network layer transmission, then MCU allows DSC to obtain the access rights of MAC, DSC is directly transferred to the data that receive in FIFO subelement in MAC, and transmission data add after header file is packaged into packet, by ethernet PHY layer and netting twine, network packet are transferred to software baseband processing module; When software baseband processing module sends data to hardware baseband processing module, first by the header portion of MCU handle packet, then MCU allows DSC to obtain the authority that directly receives MAC data, data division in packet is directly transferred in DSC by MAC, is finally transferred to again and sends in FIFO subelement.Use DSC technology can effectively alleviate the workload of MCU, allow DSC directly be responsible for the transmission of big data quantity, make MCU can have clearance spaces to go to process other tasks, therefore in the most of the time, MCU and data input and output are all in parallel work-flow, and the application of this technology improves the efficiency of whole system greatly.
(3) used two FIFO subelements as the data buffer between DSC and base band subelement.One of them FIFO is for the transmission of data, and a FIFO is used for the reception of data.FIFO(First Input First Output) First Input First Output, is a kind of data buffer of first in first out, with the difference of normal memory be there is no exterior read-write address wire, use so very simple.FIFO has two important characteristics: first can, for the transfer of data between different clock-domains, adopt FIFO to be used as data buffer storage between two different clock zones; Second can, for the transfer of data between the data-interface of different in width, realize the object of data bit width coupling with FIFO.The present invention is exactly that two characteristics that make full use of above-mentioned FIFO realize transfer of data between baseband module and DSC module, first in DSC module end, the clock frequency of MCU is fixing 16MHz, and the clock frequency of baseband module end needs not be equal to 16MHz, so need to make of FIFO the data buffering of different clock-domains; The data bit width that its deuterzooid verification platform connects DSC end is 8, the data bit width of connection digital baseband block interface is the difference along with the difference of the base band submodule of testing, for example the bit wide after BPSK demodulation is 1, and high order modulation 64QAM demodulation bit wide is afterwards 6, so be configurable with regard to needing the bit wide of FIFO.The present invention has utilized these two characteristics of FIFO to make the data between DSC and baseband module be able to effective transmission.
(4) use the network data transmission of carrying out of udp protocol.UDP(User Datagram Protocol) agreement is User Datagram Protoco (UDP), is a kind of connectionless transport layer protocol in OSI Reference Model, compares without connecting with the other side with Transmission Control Protocol, just can directly Packet Generation be gone over.It is mainly used in not requiring that, in the transmission of order of packets arrival, the inspection of transmitted in packets order is completed by application layer with sequence, and the simple unreliable information transfer service towards affairs is provided.UDP agreement is the interface of IP agreement and upper-layer protocol substantially, possesses the simple and fireballing advantage of the transmission mechanism of biography.This verification platform requires transfer of data to accomplish to transmit real-time, so the present invention has adopted udp protocol, because UDP is a kind of insecure transmission mechanism without connecting with the other side, can not guarantee that each packet sending can both normally be received, so increased a feedback mechanism in this verification platform also to UDP transmission mechanism in program, if do not receive data or order that transmitting terminal sends in setting-up time, one of receiving terminal feedback is retransmitted order to transmitting terminal, transmitting terminal resends packet again, thereby guaranteeing under the prerequisite of transmission speed, also guaranteed not loss of packet, increased the reliability of UDP transmission mechanism.
In a kind of preferred scheme, described radio frequency transmitting element comprises radio-frequency modulator, local oscillator LO and phase-locked loop pll and power amplifier PA; The input of the output termination radio-frequency modulator of described local oscillator LO and phase-locked loop pll, the input of the output termination power amplifier PA of radio-frequency modulator; DA transducer connects the input of radio-frequency modulator.
In a kind of preferred scheme, described rf receiver unit comprises variable gain amplifier VGA, radio-frequency (RF) demodulator, low noise amplifier LNA and local oscillator LO and phase-locked loop pll; The input of the output termination radio-frequency (RF) demodulator of described low noise amplifier LNA, the input of the output termination radio-frequency (RF) demodulator of local oscillator LO and phase-locked loop pll, the input of the output termination variable gain amplifier VGA of radio-frequency (RF) demodulator, the output termination AD converter of variable gain amplifier VGA.
In a kind of preferred scheme, described software baseband processing module is the processor with display unit, can be specifically PC end.
In a kind of preferred scheme, described software baseband processing module and hardware baseband processing module adopt asks--and answer-mode is mutual, when transmission starts, software baseband processing module and hardware baseband processing module all start to send a socket order, software baseband processing module sends a bind order, for distributing a native protocol address to socket; At software baseband processing module/hardware baseband processing module, " Recv " operation is used for receiving datagram, and " Send " operation is to be responsible for sending datagram; In transmission request process, the retransmitted timeout mechanism of packet of loss detects, if software baseband processing module is received this mechanism of data, does not allow software baseband processing module to retransmit transmission request to hardware baseband processing module.
Compared with prior art, beneficial effect of the present invention is:
1) this platform can make base-band software algorithm early stage high-level language algorithm for design Qualify Phase accept the check of actual channel, the communication environment without utilizing software emulation simulation, makes the result more true and reliable.
2) this verification platform can be described and partly independently carry out hardware verification the hardware language of the modules of base band, without waiting until that all modular algorithms all complete after hardware language is realized, enter again hardware verification, thereby can find in time the mistake of modules in design process.
3) when carrying out hardware verification, can utilize Ethernet that the data of checking are shown intuitively with image after the corresponding software processing by PC, facilitate designer accurately location and data analysis.
4) proof of algorithm of each base band submodule and hardware verification data can be carried out to comparative analysis directly perceived simultaneously.
5) at MAC, partly use broadcast packet filter, at MAC layer, broadcast message has been filtered out, made MCU receive only the data that software baseband processing module sends for baseband processing module, thereby alleviate the load of MCU, improved the operating efficiency of MCU.
6) use DSC, alleviated the workload of the deal with data of MCU, made MCU have more time and space to go to process other tasks, improved MCU treatment effeciency.
7) used FIFO to guarantee that the data between different clock frequencies and different bit wide interface can transmit normally and exchange.
8) use the UDP transmission technology that increases feedback mechanism, made the transfer of data of hardware baseband processing module and host computer PC end possess real time high-speed and reliable performance.
Accompanying drawing explanation
Fig. 1 is the Organization Chart of the integrated base band verification platform of the present invention.
Fig. 2 is the structure chart of radio-frequency module.
Fig. 3 is the transfer process figure of UDP transport layer protocol.
Fig. 4 is OFDM baseband system schematic diagram.
Fig. 5 is base band sync equalizing module verification block diagram.
Embodiment
Below in conjunction with accompanying drawing, the present invention will be further described, but embodiments of the present invention are not limited to this.
Whole base band verification platform mainly comprises that software baseband processing module, hardware baseband processing module and three parts of radio-frequency module form, wherein one end of software baseband processing module and hardware baseband processing module is connected use UDP transmission mechanism, and the other end of hardware baseband processing module connects RF front-end module by AD/DA.Inner at FPGA, mainly realized microcontroller, ethernet controller MAC, DSC, sending and receiving FIFO function are controlled in data storage.Above-mentioned three parts join together just to form an integrated complete base band verification platform, as shown in Figure 1.
1. each module of verification platform is introduced
1.1 software baseband processing modules, i.e. upper computer software baseband processing module
Software baseband processing module is to be comprised of two parts: first is the algorithm part of the modules in the communication baseband system of realizing by high-level language, and second is for showing the mathematical software part of verification msg at hardware verification or software verification.For first: the algorithm design of module belongs to the front end procedure of IC design, after having front-end algorithm emulation only and determining, just further do the design work of Hardware I P core, the high-level language that is about to each module of base band is described and is converted hardware program language to and describe; When base-band software proof of algorithm, use two blocks of FPGA plates as hardware baseband processing module, a reception for signal, a transmission for signal, whole system is under real communication environment, so carry out the factors such as analog channel decline, carrier shift, sampling frequency deviation without communication channel is carried out to modeling, can obtain real verification msg.For second portion: use powerful signal processing software, can intuitively the result be showed with various ways when hardware verification or software verification.
Software baseband processing module makes the various interference that baseband chip runs in actual environment when software algorithm is verified, just obtain true reflection, make algorithm reliability higher, while is shown after also allowing the result of software verification and hardware verification process by signal processing software intuitively, is convenient to designer and observes and contrast.
1.2 hardware baseband processing modules
Hardware baseband processing module is the core of whole verification platform, as shown in Figure 1.This module is comprised of two blocks of FPGA plates, and one for sending, and one for receiving.This module one end connects the full-duplex communication realizing with host computer by Ethernet, the other end connects RF front-end module by AD/DA, and these two connectivity port parts just relate to the technology of corresponding exchanges data and transmission.Inner at FPGA, in order to realize the network service with host computer, used the UDP network transmission protocol, for sending and receiving fifo register has been used in the communication realizing between hardware base band subelement and DSC module.Whole hardware baseband portion comprises: microcontroller, ethernet physical layer PHY, ethernet controller MAC, data storage controller DSC, sending and receiving FIFO, and the sending and receiving baseband module unit of realizing with hardware language in baseband system.
Fig. 1 (a) adopts this verification platform transmitting terminal schematic diagram, and Fig. 1 (b) adopts this verification platform receiving terminal schematic diagram.
Microcontroller is the 8-bit microprocessor of compatible 51 instruction set, and operating frequency is 16MHz, and its major function is the operation for control system, for example, configure DSC and realize data at MAC and send the direct transmission receiving between FIFO; By SPI/I2C bus configuration radio-frequency module; Realize the transfer of data based on udp protocol between host computer and baseband hardware processing module.
Ethernet controller MAC data link layer possesses provides the structure of addressing mechanism, Frame, data error inspection, transfer control, the functions such as data-interface of standard are provided to network layer, and assist MCU to complete the transmitting-receiving work of Ethernet data, the present invention has opened broadcast packet filter in MAC module, by this filter, at MAC, just filter out a large amount of useless broadcast singal that the host computer network port sends, only useful signal is transferred to MCU, thereby alleviate the Processing tasks of MCU, improve MCU operating efficiency.
Ethernet PHY end, is the physical layer of Internet Transmission.Physical layer has defined data and has transmitted and receive the needed signal of telecommunication, line status, clock reference, data encoding and circuit etc., and provides standard interface to data link layer device.
DSC data storage control module has been used for the transfer of data between transmitting-receiving FIFO and MAC.Use this technology can allow data transmission procedure between FIFO and MAC additionally take hardly MCU resource.When PC end sends data to FPGA hardware module, MCU receives only and processes the header portion of corresponding data bag, packet other parts complete MAC to directly transmission FIFO by DSC, when FPGA sends data to PC end, MCU only need generate corresponding header file and can utilize DSC to realize FIFO to the direct transfer of data of MAC.Use DSC can improve significantly system treatment effeciency, allow MCU have the more time to go to process other tasks.
Two FIFO subelements are as the data buffering between Ethernet interface and hardware baseband module.First between two different clock zones, adopt FIFO to be used as data buffering; Secondly for the data-interface of different in width, also can realize with FIFO the object of Data Matching.This test platform makes full use of these two characteristics of FIFO, because MCU is not necessarily consistent with the clock frequency of DA/AD end data, simultaneously between DSC and baseband module, data bit width is also not necessarily identical, so use FIFO to do data buffer storage, can solve the problems referred to above.
1.3 radio-frequency module
Radio-frequency module is mainly the mutual conversion realizing between baseband signal and radiofrequency signal, for the sending and receiving of radiofrequency signal.As shown in Figure 2 (a) shows, radio frequency transmitting element comprises radio-frequency modulator, local oscillator LO and phase-locked loop pll and power amplifier PA; The input of the output termination radio-frequency modulator of local oscillator LO and phase-locked loop pll, the input of the output termination power amplifier PA of radio-frequency modulator; DA transducer connects the input of radio-frequency modulator.As shown in Fig. 2 (b), rf receiver unit comprises variable gain amplifier VGA, radio-frequency (RF) demodulator, low noise amplifier LNA and local oscillator LO and phase-locked loop pll; The input of the output termination radio-frequency (RF) demodulator of low noise amplifier LNA, the input of the output termination radio-frequency (RF) demodulator of local oscillator LO and phase-locked loop pll, the input of the output termination variable gain amplifier VGA of radio-frequency (RF) demodulator, the output termination AD converter of variable gain amplifier VGA.
Wherein: radio-frequency modulator and radio-frequency (RF) demodulator: for to carrying out corresponding modulation and demodulation between baseband signal and radiofrequency signal; Local oscillator LO and phase-locked loop pll: for generation of carrier signal; Power amplifier PA: for by radiofrequency signal power amplification and send through antenna; Low noise amplifier LNA: for by antenna reception to radiofrequency signal carry out low noise amplification; Variable gain amplifier VGA: for the baseband signal after demodulation being enlarged into the signal that amplitude is suitable and sending AD converter to.Because rf board is high speed circuit board, be easy to occur the problems such as crosstalking of signal, the reliability of impact communication, so will pay special attention to integrality and the EMC problem of radio-frequency module signal.
1.4 UDP message transmission mechanisms
The present invention uses UDP transmission process mechanism to carry out transfer of data between host computer and hardware baseband processing module, and a kind of connectionless transmission means is provided.User datagram UDP transmission process mechanism is simple, and data transmission bauds is fast, is therefore suitable as the transmission means of base band data between software-based tape cell and hardware Base Band Unit.Host computer sends request to test platform, after meeting with a response, base band data is packaged into UDP message, is sent in test platform, and MCU processes and extract base band data to the data message receiving.Host computer sends sampling request to test platform, and test platform gathers base band data and is packaged into UDP message, passes on host computer and processes.
This test platform can be designed to a client as shown in Figure 3--the reciprocity framework of server, and wherein client is on PC, and server is at FPGA hardware module end.Fig. 3 has shown the program flow diagram of the base band data of server end after the processed rear transmission sampling of sampling request to pc client.Although UDP does not have flow control, for transmission is more reliably provided, used request-answer-mode here.When transmission starts, client and server all starts to send a socket order, and server sends a bind order, for distributing a native protocol address to socket.At client end/server end, " Recv " operation is used for receiving datagram, and " Send " operation is to be responsible for sending datagram.In transmission request process, the packet of losing can detect by retransmitted timeout mechanism, if client does not receive that this mechanism of data allows client to retransmit transmission request and arrives server end, same this data re-transmitting mechanism is also applicable to base band data transmission process.
Use has increased the udp protocol of feedback mechanism, can guarantee, under the fast prerequisite of transmission speed, to improve the reliability of transfer of data.
2. based on OFDM base band verification platform of the present invention
Adopt OFDM baseband module conventional in current wireless communication system to come example explanation how with this verification platform, to verify.
2.1 OFDM base band brief introductions
OFDM (OFDM Orthogonal Frequency Division Multiplexing) technology is a kind of improvement to multi-carrier modulation (MCM), its feature is that each subcarrier is mutually orthogonal, frequency spectrum after band spectrum modulation is overlapped, not only reduce the phase mutual interference between subcarrier, also greatly improved the availability of frequency spectrum.The core of OFDM base band is that inverse discrete Fourier transform (IFFT) module of transmitting terminal and receiving terminal are by discrete Fourier transform (FFT) module, also have as shown in Figure 4 some other common base band submodules simultaneously, also have in addition some submodules not show in the drawings as scrambling descrambling module.
2.2 baseband equalization module verification examples
With the verification platform of building, verify OFDM baseband functions, base band verification platform is divided into two parts, and a transmitting terminal and a receiving terminal, built by two FPGA plates.Choose in the present embodiment the balanced submodule of base band and verify explanation, from Fig. 4 (b), baseband equalization module is positioned at receiver baseband module, for the signal to after IFF conversion, carry out equilibrium treatment, so the hardware baseband module of transmitting terminal is complete baseband system, and the hardware baseband module of receiver only has the part base band submodule before balance module, Design for Verification Platform as shown in Figure 5.
The checking of baseband equalization module is divided into two steps, software algorithm checking and the checking of hardware base band.
The first step is the software algorithm checking of balance module, as shown in Fig. 5 (a), because balance module is positioned at receiving terminal, so when checking balance module, transmitting terminal is a complete transmitting system, first by PC software, export corresponding signal transmission (as digital audio and video signals) and by network cable transmission to FPGA transmission board, signal arrives MAC layer through the ethernet PHY layer of baseband hardware module, first MAC filters out useless broadcast datas a large amount of in Ethernet, the header file of useful data message is transferred in MCU and is processed, then MCU allows DSC directly to receive the mass data information of MAC transmission again, DSC arrives the transfer of data receiving to send FIFO again, through sending the data buffer storage of FIFO, transmitted signal is transferred to hardware baseband system, be that OFDM sends baseband system, baseband system is now the transmission baseband system of a complete Hardware, after the processing of baseband system, by the DA transducer of signal transmission and rf board and complete the transmission of radiofrequency signal.In receiving terminal, first be rf board received RF signal, through signal being transferred to after the processing of rf board to the AD converter of baseband hardware system, then signal is being transferred to receiving terminal hardware baseband module, hardware baseband module is now not a complete baseband system, only comprised the base band submodule before balance module, through directly data being sent to after IFF module, receive FIFO, receive FIFO and make corresponding data buffer storage and bit wide coupling for the different data frequency in two ends and data bit width interface, directly data-signal is imported into DSC module again, by MCU, complete datagram header file generated again, header file is being transferred to ethernet mac and PHY layer with receiving after data are packaged into packet, utilizing udp protocol that the data after packing are sent to PC by netting twine holds, in software, utilize equalization algorithm to realize the equilibrium of signal, and demonstrate balanced effect and numerical value with corresponding software.
Second step is the baseband hardware checking of balance module, after passing through the proof of algorithm of the first step, balance module is realized with hardware program language, hardware is applied this verification platform after realizing the Hardware I P core of balance module is verified, Fig. 5 (b) is the hardware verification schematic diagram of balance module, the verification system transmitting terminal course of work is identical with the software base band checking in the first step with setting, and receiving terminal than the receiving system in the first step different be, hardware baseband module has added a balanced submodule after FFT module, utilize hard-wired balance module to carry out equilibrium treatment to the signal after FFT resume module, again the signal after equilibrium is sent to host computer, utilize equally mathematical software to demonstrate portfolio effect and the numerical value of output signal after hardware equilibrium treatment, and itself and first step proof of algorithm result can be analyzed.
In like manner, for other baseband modules of receiving terminal and transmitting terminal, as mapping, conciliate mapping block, also can apply this platform and carry out integrated software and hardware combined proof of algorithm and hardware verification.
Above embodiments of the present invention, do not form limiting the scope of the present invention.Any modification of having done within spiritual principles of the present invention, be equal to and replace and improvement etc., within all should being included in claim protection range of the present invention.
Claims (5)
1. the integrated verification platform of the communication base band based on FPGA, it is characterized in that, comprise software baseband processing module, hardware baseband processing module and radio-frequency module, described software baseband processing module is by adopting the Ethernet of UDP host-host protocol to be connected with hardware baseband processing module, and hardware baseband processing module is connected with radio-frequency module by ad/da converter;
Described hardware baseband processing module comprises transmission hardware baseband processing unit and reception hardware baseband processing unit, and radio-frequency module comprises radio frequency transmitting element and rf receiver unit; Described transmission hardware baseband processing unit is connected with radio frequency transmitting element by DA transducer, receives hardware baseband processing unit and is connected with rf receiver unit by AD converter;
Described transmission hardware baseband processing unit comprises microcontroller, ethernet physical layer PHY, ethernet controller MAC, data storage controller DSC, send FIFO subelement and send base band subelement, the output of ethernet physical layer PHY is connected with the input of ethernet controller MAC, the output of ethernet controller MAC is connected with the input of data storage controller DSC, the output of data storage controller DSC is connected with the input that sends FIFO subelement, the output that sends FIFO subelement is connected with the input that sends base band subelement, the output that sends base band subelement is connected with radio frequency transmitting element by DA transducer, microcontroller respectively with net controller MAC too, data storage controller DSC connects, and in described ethernet controller MAC, is also provided with broadcast packet filter,
Described reception hardware baseband processing unit comprises microcontroller, ethernet physical layer PHY, ethernet controller MAC, data storage controller DSC, receive FIFO subelement and receive base band subelement, the input of ethernet physical layer PHY is connected with the output of ethernet controller MAC, the input of ethernet controller MAC is connected with the output of data storage controller DSC, the input of data storage controller DSC is connected with the output that receives FIFO subelement, the input that receives FIFO subelement is connected with the output that receives base band subelement, the input that receives base band subelement is connected with radio frequency transmitting element by DA transducer, microcontroller respectively with net controller MAC too, data storage controller DSC connects.
2. the integrated verification platform of the communication base band based on FPGA according to claim 1, is characterized in that, described radio frequency transmitting element comprises radio-frequency modulator, local oscillator LO and phase-locked loop pll and power amplifier PA; The input of the output termination radio-frequency modulator of described local oscillator LO and phase-locked loop pll, the input of the output termination power amplifier PA of radio-frequency modulator; DA transducer connects the input of radio-frequency modulator.
3. the integrated verification platform of the communication base band based on FPGA according to claim 2, is characterized in that, described rf receiver unit comprises variable gain amplifier VGA, radio-frequency (RF) demodulator, low noise amplifier LNA and local oscillator LO and phase-locked loop pll; The input of the output termination radio-frequency (RF) demodulator of described low noise amplifier LNA, the input of the output termination radio-frequency (RF) demodulator of local oscillator LO and phase-locked loop pll, the input of the output termination variable gain amplifier VGA of radio-frequency (RF) demodulator, the output termination AD converter of variable gain amplifier VGA.
4. the integrated verification platform of the communication base band based on FPGA according to claim 1, is characterized in that, described software baseband processing module is the processor with display unit.
5. the integrated verification platform of the communication base band based on FPGA according to claim 1, it is characterized in that, described software baseband processing module and hardware baseband processing module adopt asks--and answer-mode is mutual, when transmission starts, software baseband processing module and hardware baseband processing module all start to send a socket order, software baseband processing module sends a bind order, for distributing a native protocol address to socket; At software baseband processing module/hardware baseband processing module, " Recv " operation is used for receiving datagram, and " Send " operation is to be responsible for sending datagram; In transmission request process, the retransmitted timeout mechanism of packet of loss detects, if software baseband processing module is received this mechanism of data, does not allow software baseband processing module to retransmit transmission request to hardware baseband processing module.
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