CN103681234B - The formation method of self-alignment duplex pattern - Google Patents
The formation method of self-alignment duplex pattern Download PDFInfo
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- CN103681234B CN103681234B CN201210333005.7A CN201210333005A CN103681234B CN 103681234 B CN103681234 B CN 103681234B CN 201210333005 A CN201210333005 A CN 201210333005A CN 103681234 B CN103681234 B CN 103681234B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Abstract
A formation method for self-alignment duplex pattern, comprising: provide material layer to be etched; Described material layer to be etched is formed and sacrifices photoresist layer; Described sacrifice photoresist layer is cured; The first mask pattern is formed in the sidewall surfaces of described sacrifice photoresist layer; Remove described sacrifice photoresist layer.After described sacrifice photoresist layer is cured, the hardness of sacrificing photoresist layer improves, the stress forming the first mask layer generation in the first mask pattern process can not make to sacrifice photoresist layer generation deformation, make the sidewall of sacrificing photoresist layer still perpendicular to material surface to be etched, make the follow-up sidewalls orthogonal being formed at the first mask pattern of described sacrifice photoresist layer sidewall surfaces in material surface to be etched, finally treating etachable material layer, to carry out etching the sidewall profile of the etched features formed better.
Description
Technical field
The present invention relates to semiconductor technology, particularly a kind of formation method of self-alignment duplex pattern.
Background technology
In field of semiconductor manufacture, Other substrate materials is used for mask image to be transferred in one or more layers material layer, such as, mask image be transferred in metal level, dielectric layer or Semiconductor substrate.But along with constantly the reducing of characteristic size of semiconductor technology, the mask pattern utilizing photoetching process to form small-feature-size in material layer becomes more and more difficult.
In order to improve the integrated level of semiconductor device, industry has proposed multiple double-pattern technique, and wherein, self-alignment duplex pattern (Self-AlignedDoublePatterning, SADP) technique is one wherein.Fig. 1 to Fig. 6 is a kind of method utilizing self-alignment duplex pattern to etch semiconductor structure for mask of prior art, specifically comprises:
Please refer to Fig. 1, Semiconductor substrate 10 is provided, form material layer 20 to be etched on Semiconductor substrate 10 surface, form bottom anti-reflection layer 40 on described material layer 20 surface to be etched, form photoresist layer 50 on described bottom anti-reflection layer 40 surface;
Please refer to Fig. 2, exposure imaging is carried out to described photoresist layer, formed and sacrifice photoresist layer 55, with described sacrifice photoresist layer 55 for mask, bottom anti-reflection layer is etched, formed and sacrifice bottom anti-reflection layer 45;
Please refer to Fig. 3, on described material layer 20 surface to be etched, sacrifice photoresist layer 55 and sacrifice the sidewall surfaces of bottom anti-reflection layer 45, the top surface formation hard mask layer 60 of sacrifice photoresist layer 55;
Please refer to Fig. 4, etching is carried out back to described hard mask layer, until expose the top surface of described material layer to be etched 20 surface and sacrifice photoresist layer 55, form side wall 65 in described sacrifice photoresist layer 55, sacrifice bottom anti-reflection layer 45 sidewall surfaces;
Please refer to Fig. 5, remove described sacrifice photoresist layer and sacrifice bottom anti-reflection layer;
Please refer to Fig. 6, using described side wall 65 as mask, described material layer 20 to be etched is etched.
Manyly please refer to about self-alignment duplex pattern technique the american documentation literature that publication number is US2009/0146322A1.
But inventor finds, the sidewall profile of etched features that material layer to be etched formed is poor to utilize said method to etch.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of self-alignment duplex pattern, and the sidewall profile of the etched features utilizing described method finally to be formed is better.
For solving the problem, technical solution of the present invention provides a kind of formation method of self-alignment duplex pattern, comprising: provide material layer to be etched; Described material layer to be etched is formed and sacrifices photoresist layer; Described sacrifice photoresist layer is cured; The first mask pattern is formed in the sidewall surfaces of described sacrifice photoresist layer; Remove described sacrifice photoresist layer.
Optionally, described curing process is ion implantation curing process, utilizes described ion implantation curing process the photoresist of sacrificing top and sidewall in photoresist layer to be become solidification photoresist shell.
Optionally, the ion injected in described ion implantation curing process is H, B, BF
2, BF
3, BF
4, P, As, In, C, Ge wherein one or more combination.
Optionally, the dosage range injected in described ion implantation curing process is 10E13atom/cm
2~ 10E16atom/cm
2, the energy range of injection is 1KeV ~ 500KeV, and the angular range of injection is-70 ~ 70 degree.
Optionally, the technique forming described sacrifice photoresist layer comprises: form photoresist layer in described material surface to be etched, carry out exposure imaging to described photoresist layer, formed and sacrifice photoresist layer.
Optionally, the technique forming described first mask pattern comprises: at described material layer to be etched, sacrifice photoresist layer surface formation the first mask layer, etching is carried out back to described first mask layer, forms the first mask pattern at described sacrifice photoresist layer sidewall.
Optionally, the technique forming described sacrifice photoresist layer comprises: form bottom anti-reflection layer in described material surface to be etched, forms photoresist layer, carry out exposure imaging, formed and sacrifice photoresist layer described photoresist layer on described bottom anti-reflection layer surface.
Optionally, the technique forming described first mask pattern comprises: in described bottom anti-reflection layer, sacrifice photoresist layer surface formation the first mask layer, etching is carried out back to described first mask layer, forms the first mask pattern at described sacrifice photoresist layer sidewall.
Optionally, the technique forming described sacrifice photoresist layer comprises: on described material layer to be etched, form bottom anti-reflection layer, photoresist layer is formed on described bottom anti-reflection layer surface, exposure imaging is carried out to described photoresist layer, formed and sacrifice photoresist layer, with described sacrifice photoresist layer for mask, described bottom anti-reflection layer is etched, formed and sacrifice bottom anti-reflection layer.
Optionally, the technique forming described sacrifice photoresist layer comprises: on described material layer to be etched, form the bottom anti-reflection layer dissolving in developer solution, photoresist layer is formed on described bottom anti-reflection layer surface, exposure imaging is carried out to described bottom anti-reflection layer and photoresist layer, forms the sacrifice photoresist layer of sacrificing bottom anti-reflection layer and being positioned at described sacrifice bottom anti-reflection layer surface.
Optionally, the technique forming described first mask pattern comprises: form the first mask layer at the top surface of described material surface to be etched, the sidewall surfaces of sacrificing bottom anti-reflection layer and sacrifice photoresist layer, sacrifice photoresist layer, etching is carried out back to described first mask layer, forms the first mask pattern in the sidewall surfaces of described sacrifice bottom anti-reflection layer and sacrifice photoresist layer.
Optionally, the material of described first mask pattern is silica, silicon nitride, silicon oxynitride, titanium nitride, tantalum nitride wherein one or more.
Optionally, also comprise, form the second mask layer in described material surface to be etched, described second mask layer is formed and sacrifices photoresist layer.
Optionally, after forming described first mask pattern, with described first mask pattern for mask, described second mask layer is etched, forms the second mask pattern.
Optionally, remove described first mask pattern, with described second mask pattern for mask, described material layer to be etched is etched.
Optionally, the material of described second mask layer is silica, silicon nitride, carborundum, silicon oxynitride, amorphous carbon, polysilicon, hafnium oxide, titanium oxide, zirconia, titanium nitride, tantalum nitride, titanium wherein one or more.
Optionally, also comprise, with described first mask pattern for mask, described material layer to be etched is etched.
Compared with prior art, the present invention has the following advantages:
The embodiment of the present invention is formed on described material layer to be etched sacrifices photoresist layer, described sacrifice photoresist layer is carried out ion implantation solidification, then the first mask pattern is formed in the sidewall surfaces of described sacrifice photoresist layer, after removing described sacrifice photoresist layer, utilize described first mask pattern to treat etachable material layer and etch.After described sacrifice photoresist layer is cured, the hardness of sacrificing photoresist layer improves, the stress forming the first mask layer generation in the first mask pattern process can not make to sacrifice photoresist layer generation deformation, make the sidewall of sacrificing photoresist layer still perpendicular to material surface to be etched, make the follow-up sidewalls orthogonal being formed at the first mask pattern of described sacrifice photoresist layer sidewall surfaces in material surface to be etched, finally treating etachable material layer, to carry out etching the sidewall profile of the etched features formed better.
Accompanying drawing explanation
Fig. 1 to Fig. 6 is the cross-sectional view of the self-alignment duplex pattern technique of prior art;
Fig. 7 is the schematic flow sheet of the formation method of the self-alignment duplex pattern of the embodiment of the present invention;
Fig. 8 to Figure 17 is the cross-sectional view of the forming process of the self-alignment duplex pattern of the embodiment of the present invention.
Embodiment
The sidewall profile of etched features that material layer to be etched formed is etched poor owing to utilizing above-mentioned technology, inventor finds through research, when forming hard mask layer in described sacrificial material layer and sacrifice photoresist layer surface, described hard mask layer can produce effect of stress to sacrifice photoresist layer, because the hardness of photoresist layer is little, even if photoresist layer is also comparatively soft after front baking, the stress that described hard mask layer produces can make to sacrifice photoresist layer distortion, forming section is the trapezoidal sacrifice photoresist layer of class, the sidewall of sacrificing photoresist layer is made to be not orthogonal to material surface to be etched, the follow-up side wall being formed at described sacrifice photoresist layer sidewall surfaces is made to be not orthogonal to material surface to be etched, the sidewall profile that etachable material layer carries out etching the etched features formed finally is treated in impact.
For this reason, the present invention proposes a kind of formation method of self-alignment duplex pattern, described material layer to be etched is formed and sacrifices photoresist layer, described sacrifice photoresist layer is cured, then the first mask pattern is formed in the sidewall surfaces of described sacrifice photoresist layer, after removing described sacrifice photoresist layer, utilize described first mask pattern to treat etachable material layer and etch.After described sacrifice photoresist layer is cured, the hardness of sacrificing photoresist layer improves, the stress forming the first mask layer generation in the first mask pattern process can not make to sacrifice photoresist layer generation deformation, make the sidewall of sacrificing photoresist layer still perpendicular to material surface to be etched, make the follow-up sidewalls orthogonal being formed at the first mask pattern of described sacrifice photoresist layer sidewall surfaces in material surface to be etched, finally treating etachable material layer, to carry out etching the sidewall profile of the etched features formed better.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here to implement with multiple, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention.Therefore the present invention is not by the restriction of following public concrete enforcement.
Please refer to Fig. 7, be the schematic flow sheet of the formation method of the self-alignment duplex pattern of the embodiment of the present invention, specifically comprise:
Step S101, provides Semiconductor substrate, forms material layer to be etched at described semiconductor substrate surface;
Step S102, forms the second mask layer in described material surface to be etched;
Step S103, forms bottom anti-reflection layer on described second mask layer surface, forms photoresist layer on described bottom anti-reflection layer surface;
Step S104, carries out exposure imaging to described photoresist layer, is formed and sacrifices photoresist layer;
Step S105, carries out ion implantation to described sacrifice photoresist layer, the photoresist of top and sidewall in described sacrifice photoresist layer is formed solidification photoresist shell;
Step S106, in described bottom anti-reflection layer, sacrifices photoresist layer surface formation the first mask layer, carries out back etching, form the first mask pattern at described sacrifice photoresist layer sidewall to described first mask layer;
Step S107, removes described sacrifice photoresist layer, with described first mask pattern for mask, etches, form the second mask pattern to described bottom anti-reflection layer, the second mask layer;
Step S108, removes described first mask pattern, with described second mask pattern for mask, etches described material layer to be etched, forms etched features.
Concrete, please refer to Fig. 8 to Figure 17, is the structural representation of the forming process of the self-alignment duplex pattern of the embodiment of the present invention.
Please refer to Fig. 8, Semiconductor substrate 100 is provided, form material layer 110 to be etched on described Semiconductor substrate 100 surface.
Described Semiconductor substrate 100 is silicon substrate, germanium substrate, silicon-Germanium substrate, silicon-on-insulator substrate (SOI), one wherein such as germanium on insulator (GOI) substrate, glass substrate etc.Described material layer to be etched 110 is wherein one or more such as silicon oxide layer, silicon nitride layer, polysilicon layer, low-K dielectric material, amorphous carbon, metal level.In the present embodiment, described material layer 110 to be etched is metal level, and the material of described metal level is aluminium, utilizes self-alignment duplex pattern to form metal interconnecting wires for mask carries out etching to described metal level.In other embodiments, described material layer to be etched can also be Semiconductor substrate, utilizes self-alignment duplex pattern to etch described Semiconductor substrate as mask.
Please refer to Fig. 9, form the second mask layer 120 on described material layer 110 surface to be etched.
Described second mask layer 120 is single layer structure or multilayer lamination structure, the material of described second mask layer 120 is silica, silicon nitride, carborundum, silicon oxynitride, amorphous carbon, polysilicon, hafnium oxide, titanium oxide, zirconia, titanium nitride, tantalum nitride, titanium wherein one or more, and the technique of described formation second mask layer 120 is chemical vapor deposition method or physical gas-phase deposition.The material of described second mask layer 120 is different from the material of material layer 110 to be etched, both have high etching selection ratio, make the second mask pattern of the second mask layer 120 formation described in later use treat the loss of the second mask pattern when etachable material layer 110 etches less, be conducive to the pattern and the size that control the final etched features formed.And the upper end of the first mask pattern formed due to follow-up time etching is not often the rectangle of rule, there is certain radian, directly utilize described first mask pattern to treat etachable material layer for mask and carry out the sidewall profile that etching can affect the final etched features formed, therefore, in the present embodiment, the second mask layer 120 is formed on described material layer 110 surface to be etched, after later use second mask layer 120 forms the second mask pattern, remove the first mask pattern being positioned at its surface, the second mask pattern being regular oblong with described upper end shape is for mask, etch described material layer to be etched, be conducive to the pattern controlling the final etched features formed.And in the present embodiment, described second mask layer 120 comprises amorphous carbon layer and is positioned at the silicon oxide layer on described amorphous carbon layer surface, because when dry etch process etches amorphous carbon layer, amorphous carbon layer sidewall profile is better, and described silicon oxide layer is larger with the etching selection of metal level, be conducive to the metal level that etch thicknesses is larger.
Please refer to Figure 10, form bottom anti-reflection layer 130 on described second mask layer 120 surface, form photoresist layer 140 on described bottom anti-reflection layer 130 surface.
Reflected by the interface after photoresist layer between photoresist layer and substrate to prevent the light exposed, make photoresist can not uniform exposure, in the present embodiment, first form bottom anti-reflection layer (BARC) 130 on described second mask layer 120 surface, then form photoresist layer 140 on described bottom anti-reflection layer 130 surface.In other embodiments, also directly photoresist layer can be formed on described second mask layer surface.
In the present embodiment, described bottom anti-reflection layer 130 is Inorganic bottom antireflective layer, such as silicon nitride, silicon oxynitride etc.In other embodiments, described bottom anti-reflection layer can also be organic bottom antireflective layer, such as polyimides etc.
Above-mentioned Inorganic bottom antireflective layer and organic bottom antireflective layer are insoluble to developer solution after exposure technology, in other embodiments, the bottom anti-reflection layer adopted can also be dissolved in developer solution after overexposure, make a step exposure imaging technique form patterned sacrifice bottom anti-reflection layer simultaneously and be positioned at the sacrifice photoresist layer of sacrificing bottom anti-reflection layer surface, saving a step etching and remove the technique of sacrificing bottom anti-reflection layer.
In the present embodiment, the technique forming described Inorganic bottom antireflective layer is chemical vapor deposition method or physical gas-phase deposition, and the technique forming photoresist layer is spin coating technique.
In other embodiments, the technique forming described bottom anti-reflection layer can also be spin coating technique.
In other embodiments, also the second mask layer can not be formed in described material surface to be etched, directly form bottom anti-reflection layer in described material surface to be etched, photoresist layer is formed on described bottom anti-reflection layer surface, and utilize follow-up the first mask pattern being formed at material surface to be etched to be mask, described material layer to be etched is etched.
Please refer to Figure 11, to described photoresist layer 140(with reference to Figure 10) carry out exposure imaging, form patterned sacrifice photoresist layer 145 on described bottom anti-reflection layer 130 surface.
After exposing described photoresist layer 140, utilize the photoresist layer of developer solution to described exposure area to develop, in the present embodiment, described developer solution is tetramethyl ammonium hydroxide solution.In the present embodiment, after forming described patterned sacrifice photoresist layer 145, form the first mask pattern at described patterned sacrifice photoresist layer 145 sidewall.
In other embodiments, after forming described patterned sacrifice photoresist layer, with described patterned sacrifice photoresist layer for mask, described bottom anti-reflection layer is etched, form patterned sacrifice bottom anti-reflection layer, the follow-up sidewall surfaces at described sacrifice bottom anti-reflection layer, sacrifice photoresist layer forms the first mask pattern.
In other embodiments, when described bottom anti-reflection layer is dissolved in developer solution after exposure, exposure imaging is carried out to described photoresist layer, bottom anti-reflection layer, obtain patterned sacrifice bottom anti-reflection layer simultaneously and be positioned at the sacrifice photoresist layer of sacrificing bottom anti-reflection layer surface, the follow-up sidewall surfaces at described sacrifice bottom anti-reflection layer, sacrifice photoresist layer forms the first mask pattern.
Please refer to Figure 12, ion implantation is carried out to described sacrifice photoresist layer 145, the photoresist of top and sidewall in described sacrifice photoresist layer 145 is formed solidification photoresist shell 146.
The design parameter of described ion implantation curing process comprises: the ion of injection is H, B, BF
2, BF
3, BF
4, P, As, In, C, Ge wherein one or more combination, the dosage range of ion implantation is 10E13atom/cm
2~ 10E16atom/cm
2, the energy range of ion implantation is 1KeV ~ 500KeV, and the angular range of injection is-70 ~ 70 degree, makes not only at the top of sacrificing photoresist layer 145, also forms solidification photoresist shell 146 at the sidewall of sacrificing photoresist layer 145.Again cross-linking reaction can be there is in the ion of described injection with photoresist molecule, photoresist is solidified, and heavy dose of ion injected can make the temperature on sacrifice photoresist surface raise, and makes the sacrifice photoresist layer of described ion implantation dewater, even carburizing reagent occurs.Hardness due to the photoresist of carbonization is far longer than the hardness of the photoresist without ion implantation, solidification photoresist shell 146 is formed at the top of described sacrifice photoresist layer and sidewall, the stress that first mask layer of follow-up formation produces can not produce deformation to described solidification photoresist shell, also wall deformation run-off the straight or the fold of described sacrifice photoresist layer would not be made, the sidewall of described sacrifice photoresist layer still flat smooth and perpendicular to material surface to be etched, the sidewall making follow-up the first mask pattern formed in described sacrifice photoresist layer sidewall surfaces also flat smooth and perpendicular to material surface to be etched.
Please refer to Figure 13, form the first mask layer 150 at described bottom anti-reflection layer 130 surface, the sidewall of sacrificing photoresist layer 145 and top surface.
The material of described first mask layer 150 is silica, silicon nitride, silicon oxynitride, titanium nitride, tantalum nitride wherein one or more.The material of described first mask layer 150 is different from the material of the second mask layer 120, both have high etching selection ratio, when first mask pattern of the first mask layer 150 formation described in later use is etched the second mask layer 120, the loss of the first mask pattern is less, is conducive to the pattern and the size that control the final etched features formed.
In other embodiments, when described bottom anti-reflection layer is formed directly into described material surface to be etched, the material of described first mask layer is different from the material of material layer to be etched, both have high etching selection ratio, make the first mask pattern of the first mask layer formation described in later use treat the loss of the first mask pattern when etachable material layer etches less, be conducive to the pattern and the size that control the final etched features formed.
Because described first mask layer 150 is for the formation of the first mask pattern of self-alignment duplex pattern, the width of described first mask pattern depends on the thickness of the first mask layer 150 of the sidewall surfaces of sacrificing photoresist layer 145, therefore, by controlling the thickness of described first mask layer 150, the width of the final etched features formed just can be controlled.The technique of described first mask layer that the embodiment of the present invention is formed is atom layer deposition process, low-pressure chemical vapor deposition process or sub-aumospheric pressure cvd technique, because the deposition rate of above-mentioned several depositing operation is slower, the the first mask layer uniformity formed is better, the sidewall being positioned at the first mask layer 150 of the sidewall surfaces of described sacrifice photoresist layer 145 is vertically smooth, pattern is better, make the sidewall profile of the first mask pattern of follow-up formation better, with described first mask pattern for mask the second mask layer or material layer to be etched are etched time, the pattern of the figure that etching is formed is better.
Please refer to Figure 14, to described first mask layer 150(with reference to Figure 13) carry out back etching, until expose described bottom anti-reflection layer 130 surface, the first mask layer 150 being positioned at the sidewall surfaces of described sacrifice photoresist layer 145 forms the first mask pattern 155.
The width of described first mask pattern 155 is corresponding with the thickness of the first mask layer 150.When the shape of overlooking visual angle of described sacrifice photoresist layer 145 is strip, the shape of described first mask pattern 155 is the annular mask pattern around sacrificing photoresist layer 145, in the present embodiment, because the etched features finally formed is metal interconnecting wires, when the described sacrifice bottom anti-reflection layer of follow-up removal with after sacrificing photoresist layer, recycling photoresist covers the first mask pattern corresponding to strip zone line, expose the first mask pattern that strip two ends are corresponding, with described photoresist for mask removes the first mask pattern corresponding to described strip two ends, described first mask pattern is made to become straight line or the broken line of bar shaped.
Please refer to Figure 15, utilize cineration technics to remove described sacrifice photoresist layer 145(with reference to Figure 13).
The organic substance be made up of elements such as C, O, H, N due to the material of described sacrifice photoresist layer forms, and the reacting gas of described cineration technics is O
2by described oxygen gas plasma, and utilize the sacrifice photoresist layer 145 of described oxygen gas plasma and carbonization or non-carbonization to react, form the main product such as volatile carbon monoxide, carbon dioxide, water, thus remove described sacrifice photoresist layer 145.In other embodiments, the reacting gas of described cineration technics can also comprise N
2or H
2deng, described N
2or H
2be conducive to improving the ability removed and sacrifice photoresist layer and residual polymer.
In other embodiments, wet-etching technology or dry etch process also can be adopted to remove described sacrifice photoresist layer.
Material due to the bottom anti-reflection layer in the embodiment of the present invention is Inorganic bottom antireflective layer, can not be ashed technique and removed, and makes described cineration technics only eliminate described sacrifice photoresist layer 145.
In other embodiments, when described first mask pattern is formed at described sacrifice bottom anti-reflection layer and sacrifices photoresist layer sidewall, cineration technics, wet-etching technology or dry etch process is utilized to remove described sacrifice bottom anti-reflection layer and sacrifice photoresist layer.
Please refer to Figure 16, with described first mask pattern 155 for mask, to described bottom anti-reflection layer 130(with reference to Figure 15), the second mask layer 120(is with reference to Figure 15) carry out dry etching, form the second mask pattern 125.Due to the rectangle that the upper end returning the first mask pattern 155 that etching is formed is not often rule, there is certain radian, directly utilize described first mask pattern to treat etachable material layer for mask and carry out the sidewall profile that etching can affect the final etched features formed, therefore, in the present embodiment, after forming the second mask pattern 125, remove and be positioned at first mask pattern 155 on its surface and remaining bottom anti-reflection layer, the second mask pattern 125 being regular oblong with described upper end shape is for mask, etch described material layer to be etched 110, be conducive to the pattern controlling the final etched features formed.
Please refer to Figure 17, remove described first mask pattern 155(with reference to Figure 16) and remaining bottom anti-reflection layer, with described second mask pattern 125 for mask, described material layer 110 to be etched is etched, form the etched features 115 of self-alignment duplex pattern.In the present embodiment, the technique removing described first mask pattern 155 and remaining bottom anti-reflection layer is wet etching.Because the width of described etched features 115 determines according to the thickness of the first mask layer, the thickness of described first mask layer can be less than the photoetching of existing technique, the minimum dimension of etching technics, make the width of described etched features 115 be less than the width of the figure utilizing photoetching process to be formed, be conducive to the integrated level improving integrated circuit.
To sum up, the embodiment of the present invention is formed on described material layer to be etched sacrifices photoresist layer, described sacrifice photoresist layer is carried out ion implantation solidification, then the first mask pattern is formed in the sidewall surfaces of described sacrifice photoresist layer, after removing described sacrifice photoresist layer, utilize described first mask pattern to treat etachable material layer and etch.After described sacrifice photoresist layer is cured, the hardness of sacrificing photoresist layer improves, the stress forming the first mask layer generation in the first mask pattern process can not make to sacrifice photoresist layer generation deformation, make the sidewall of sacrificing photoresist layer still perpendicular to material surface to be etched, make the follow-up sidewalls orthogonal being formed at the first mask pattern of described sacrifice photoresist layer sidewall surfaces in material surface to be etched, finally treating etachable material layer, to carry out etching the sidewall profile of the etched features formed better.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (16)
1. a formation method for self-alignment duplex pattern, is characterized in that, comprising:
Material layer to be etched is provided;
Described material layer to be etched forms patterned sacrifice photoresist layer;
Described sacrifice photoresist layer is cured;
The first mask pattern is formed in the sidewall surfaces of described sacrifice photoresist layer, the technique forming described first mask pattern comprises: at described material layer to be etched, sacrifice photoresist layer surface formation the first mask layer, etching is carried out back to described first mask layer, forms the first mask pattern at described sacrifice photoresist layer sidewall;
Remove described sacrifice photoresist layer.
2. the formation method of self-alignment duplex pattern as claimed in claim 1, it is characterized in that, described curing process is ion implantation curing process, utilizes described ion implantation curing process the photoresist of sacrificing top and sidewall in photoresist layer to be become solidification photoresist shell.
3. the formation method of self-alignment duplex pattern as claimed in claim 2, it is characterized in that, the ion injected in described ion implantation curing process is H, B, BF
2, BF
3, BF
4, P, As, In, C, Ge wherein one or more combination.
4. the formation method of self-alignment duplex pattern as claimed in claim 3, it is characterized in that, the dosage range injected in described ion implantation curing process is 10E13atom/cm
2~ 10E16atom/cm
2, the energy range of injection is 1KeV ~ 500KeV, and the angular range of injection is-70 degree ~ 70 degree.
5. the formation method of self-alignment duplex pattern as claimed in claim 1, it is characterized in that, the technique forming described sacrifice photoresist layer comprises: form photoresist layer in described material surface to be etched, carry out exposure imaging to described photoresist layer, formed and sacrifice photoresist layer.
6. the formation method of self-alignment duplex pattern as claimed in claim 1, it is characterized in that, the technique forming described sacrifice photoresist layer comprises: form bottom anti-reflection layer in described material surface to be etched, photoresist layer is formed on described bottom anti-reflection layer surface, exposure imaging is carried out to described photoresist layer, is formed and sacrifice photoresist layer.
7. the formation method of self-alignment duplex pattern as claimed in claim 6, it is characterized in that, the technique forming described first mask pattern comprises: in described bottom anti-reflection layer, sacrifice photoresist layer surface formation the first mask layer, etching is carried out back to described first mask layer, forms the first mask pattern at described sacrifice photoresist layer sidewall.
8. the formation method of self-alignment duplex pattern as claimed in claim 1, it is characterized in that, the technique forming described sacrifice photoresist layer comprises: on described material layer to be etched, form bottom anti-reflection layer, photoresist layer is formed on described bottom anti-reflection layer surface, exposure imaging is carried out to described photoresist layer, is formed and sacrifice photoresist layer, with described sacrifice photoresist layer for mask, described bottom anti-reflection layer is etched, is formed and sacrifice bottom anti-reflection layer.
9. the formation method of self-alignment duplex pattern as claimed in claim 1, it is characterized in that, the technique forming described sacrifice photoresist layer comprises: on described material layer to be etched, form the bottom anti-reflection layer dissolving in developer solution, photoresist layer is formed on described bottom anti-reflection layer surface, exposure imaging is carried out to described bottom anti-reflection layer and photoresist layer, forms the sacrifice photoresist layer of sacrificing bottom anti-reflection layer and being positioned at described sacrifice bottom anti-reflection layer surface.
10. the formation method of self-alignment duplex pattern as claimed in claim 8 or 9, it is characterized in that, the technique forming described first mask pattern comprises: form the first mask layer at the top surface of described material surface to be etched, the sidewall surfaces of sacrificing bottom anti-reflection layer and sacrifice photoresist layer, sacrifice photoresist layer, etching is carried out back to described first mask layer, forms the first mask pattern in the sidewall surfaces of described sacrifice bottom anti-reflection layer and sacrifice photoresist layer.
The formation method of 11. self-alignment duplex pattern as claimed in claim 1, is characterized in that, the material of described first mask pattern is silica, silicon nitride, silicon oxynitride, titanium nitride, tantalum nitride wherein one or more.
The formation method of 12. self-alignment duplex pattern as claimed in claim 1, is characterized in that, also comprise, form the second mask layer in described material surface to be etched, described second mask layer is formed and sacrifices photoresist layer.
The formation method of 13. self-alignment duplex pattern as claimed in claim 12, is characterized in that, after forming described first mask pattern, with described first mask pattern for mask, etches, form the second mask pattern to described second mask layer.
The formation method of 14. self-alignment duplex pattern as claimed in claim 13, is characterized in that, remove described first mask pattern, with described second mask pattern for mask, etches described material layer to be etched.
The formation method of 15. self-alignment duplex pattern as claimed in claim 12, it is characterized in that, the material of described second mask layer is silica, silicon nitride, carborundum, silicon oxynitride, amorphous carbon, polysilicon, hafnium oxide, titanium oxide, zirconia, titanium nitride, tantalum nitride, titanium wherein one or more.
The formation method of 16. self-alignment duplex pattern as claimed in claim 1, is characterized in that, also comprise, and with described first mask pattern for mask, etches described material layer to be etched.
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| CN103972078A (en) * | 2014-05-20 | 2014-08-06 | 上海华力微电子有限公司 | Method for forming self-aligned double-layer graph |
| CN103972076A (en) * | 2014-05-20 | 2014-08-06 | 上海华力微电子有限公司 | Method for forming self-aligned double-layer graph |
| CN104064471A (en) * | 2014-05-21 | 2014-09-24 | 上海华力微电子有限公司 | Side wall forming method for dual imaging process flow |
| CN107785242B (en) * | 2016-08-31 | 2020-02-07 | 中芯国际集成电路制造(上海)有限公司 | Triple patterning method |
| CN107978517B (en) * | 2016-10-21 | 2020-07-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
| CN109767976A (en) * | 2017-11-10 | 2019-05-17 | 中芯国际集成电路制造(上海)有限公司 | Pattern photoresist, the multiple pattern of autoregistration, semiconductor devices and manufacturing method |
| CN111640656B (en) * | 2019-03-01 | 2023-06-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN111696862B (en) * | 2019-03-12 | 2023-07-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111834214B (en) * | 2019-04-16 | 2024-04-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110501871A (en) | 2019-08-13 | 2019-11-26 | 上海华虹宏力半导体制造有限公司 | For defining the photoetching technological method of litho pattern sidewall profile |
| CN110459465B (en) * | 2019-08-30 | 2022-03-04 | 上海华力微电子有限公司 | Method for forming self-aligned double-layer pattern |
| CN111123641A (en) * | 2019-12-20 | 2020-05-08 | 上海华虹宏力半导体制造有限公司 | Gray scale mask pattern for changing photoetching sidewall morphology |
| CN114093755B (en) * | 2021-11-15 | 2024-05-03 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
| CN114640934B (en) * | 2022-04-20 | 2024-04-02 | 瑶芯微电子科技(上海)有限公司 | MEMS microphone and preparation method thereof |
| CN117650043A (en) * | 2023-12-07 | 2024-03-05 | 芯联越州集成电路制造（绍兴）有限公司 | Method for manufacturing semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS648676A (en) * | 1987-06-30 | 1989-01-12 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| EP0753764A1 (en) * | 1995-07-14 | 1997-01-15 | Texas Instruments Incorporated | Improvements in or relating to semiconductor devices |
| US5876903A (en) * | 1996-12-31 | 1999-03-02 | Advanced Micro Devices | Virtual hard mask for etching |
| CN102439523A (en) * | 2009-07-23 | 2012-05-02 | 道康宁公司 | Method and materials for double patterning |
-
2012
- 2012-09-10 CN CN201210333005.7A patent/CN103681234B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS648676A (en) * | 1987-06-30 | 1989-01-12 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| EP0753764A1 (en) * | 1995-07-14 | 1997-01-15 | Texas Instruments Incorporated | Improvements in or relating to semiconductor devices |
| US5876903A (en) * | 1996-12-31 | 1999-03-02 | Advanced Micro Devices | Virtual hard mask for etching |
| CN102439523A (en) * | 2009-07-23 | 2012-05-02 | 道康宁公司 | Method and materials for double patterning |
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