CN103677917A - Customizable embedded processing system based on FPGA reconfiguration technology - Google Patents
Customizable embedded processing system based on FPGA reconfiguration technology Download PDFInfo
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- CN103677917A CN103677917A CN201310670431.4A CN201310670431A CN103677917A CN 103677917 A CN103677917 A CN 103677917A CN 201310670431 A CN201310670431 A CN 201310670431A CN 103677917 A CN103677917 A CN 103677917A
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Abstract
The invention discloses a customizable embedded processing system based on the FPGA reconfiguration technology. The customizable embedded processing system achieves parallel processing on tasks by reusing hardware resources in the time domain, and can be defined as a computing system composed of a master control module and a plurality of customizable function modules. The master control module is in charge of control and dispatching management for the whole system. The customizable function modules adopt the FPGA reconfiguration technology, and can response configuration instructions of a maser control node, upload different configuration information and execute different function tasks according to different application requirements. The customizable embedded processing system is formed based on the unified architecture through recombination or reconfiguration of components according to the requirements for the function, performance, reliability, safety and the like of an application, the development cost is effectively reduced, the development period is shortened, and the resource use ratio, system reliability and reusability are improved.
Description
Technical field
The invention belongs to high-performance embedded digital signal parallel processing technique field, particularly relate to a kind of customizable embedded processing systems based on FPGA reconfiguration technology.
Background technology
FPGA reconfiguration technology is a kind of method for designing of Runtime reconfiguration of the local or whole logical resources of FPGA being carried out at system run duration.This technology has been utilized the repeatedly characteristic of repeated configuration logic function of FPGA, can realize more complicated logical circuit function with less hardware resource, when improving system applies dirigibility, shortening the construction cycle, significantly reduce again system cost, and can effectively improve fpga chip utilization factor, the applicability of raising FPGA hardware platform to systemic-function.
Embedded processing systems is application-centered, take computing machine treatment technology as basis, is that a kind of software and hardware can cutting, and being applicable to application system has the computer system of strict demand to aspects such as function, reliability, cost, volume, power consumptions.According to the feature of embedded processing systems, traditional embedded processing systems exists that product category is many, the construction cycle is long, reusability is poor and the problem such as logistics support is difficult in design.The conventional method addressing the above problem is for to carry out universalization, seriation, modularized processing by computing system, yet this processing is only only applicable to the application of standard product, when slightly doing to change, interface, resource distribution still need again to develop, in addition in general module, there is redundant resource configuration, in actual applications, in the time of can not guaranteeing to move different application, can bring into play optimum usefulness.
Electronic system and the sensor fusion techniques of high integrity are had higher requirement to embedded processing systems, the embedded processing technical requirement system of Next Generation electronic system application possesses high speed processing ability, data transmission capabilities at a high speed and flexibly internet topology, and can be according to different and each function in task and stage in the required different disposal ability of different phase, can carry out dynamic recognition to the resource of meter embedded processing systems, thereby reach the optimization of resource distribution and utilization, improve reliability, reusability, reduce the objects such as cost of development.
Summary of the invention
For solving existing embedded processing systems, there is redundant resource configuration, in actual applications, in the time of can not guaranteeing to move different application, system can be brought into play the technical matters of optimum usefulness, the invention provides a kind of customizable embedded processing systems based on FPGA reconfiguration technology.
Technology settling mode of the present invention:
Customizable embedded processing systems based on FPGA reconfiguration technology, its special character is: comprise main control module, Switching Module and at least one customizable functionality module,
Described main control module comprises at least one main controlled node, between described main controlled node and main controlled node, interconnects,
Described Switching Module comprises at least one exchange chip, between described exchange chip and exchange chip, interconnects,
Described customizable functionality module comprises that at least one reshuffles node, described in reshuffle node for reshuffling FPGA, described in reshuffle node and reshuffle between node and interconnect,
Described main control module interconnects by Switching Module and customizable functionality module, between described customizable functionality module and customizable functionality module, by Switching Module, is connected.
Above-mentioned main controlled node is one or more of FPGA, CPU, DSP.
The above-mentioned FPGA of reshuffling comprises static part and reshuffles region,
Described static part comprises processor, bus control logic, store control logic, communication interface logic, reshuffles steering logic,
Described store control logic, communication interface logic, reshuffle steering logic and be connected with bus control logic respectively,
Described reshuffle steering logic by bus control logic with reshuffle joint area,
Described processor passes through each logic of bus control logic access static part,
Described processor is configured by reshuffling steering logic counterweight configuring area,
Described processor is by communication interface logical and master control FPGA and/or reshuffle FPGA and communicate by letter.
Above-mentioned exchange chip is RapidIO exchange chip.
Between above-mentioned main controlled node and main controlled node, by RapidIO exchange chip, be connected, described in reshuffle node and by RapidIO exchange chip, be connected with reshuffling between node.
Compared with prior art, advantage is in the present invention:
1, the present invention on unified shader basis according to demands such as the functions, performance, reliability, security of application, restructuring by member or reshuffle, realize a kind of embedded processing systems of customization, can effectively reduce cost of development, shorten the construction cycle, improve resource utilization, system reliability and reusability.
2, main control module of the present invention adopts the embedded high-performance processor core of FPGA as processing node, is responsible for the control and scheduling management to whole system, guarantees the performance of system.
3, in customizable functionality module of the present invention, reshuffling region can be according to different system requirements, by main controlled node, configured different hardware logic electric circuits, realize the time division multiplex of hardware resource, can allow the system of a comparison " greatly " realize on the hardware resource of a comparison " little ".
4, the present invention forms the interconnection topology network of a high speed serialization by Switching Module, realizes system-wide high-speed interconnect, guarantees the dirigibility of system.
Accompanying drawing explanation
Fig. 1 is theory diagram of the present invention;
Fig. 2 is specific embodiment of the invention high speed interconnection network theory diagrams;
Fig. 3 is functional module theory diagram in the specific embodiment of the invention;
Fig. 4 is main controlled node theory diagram in the specific embodiment of the invention;
Fig. 5 reshuffles node theory diagram in the specific embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing, 1-5 elaborates to the present invention.
As shown in Figure 1, customizable embedded processing systems based on FPGA reconfiguration technology, comprise a main control module, a Switching Module and several customizable functionality modules, main control module interconnects by Switching Module and customizable functionality module, between customizable functionality module and customizable functionality module, by Switching Module, is connected.
Figure 2 shows that specific embodiment of the invention high speed interconnection network theory diagram, customizable embedded processing systems comprises a main control module, two customizable modules, a Switching Module, main control module comprises 2 master control FPGA, Switching Module comprises 3 exchange chips, and customizable module module comprises that 2 are reshuffled FPGA.
Main control module and each customizable functionality module are respectively exported 4 tunnel high speed Serial RapidIO interfaces, and (wherein in module, exchange chip is exported 2 tunnels, two nodes are respectively exported 1 tunnel) be connected to Switching Module, system forms the interconnection topology network of a high speed serialization by Switching Module.
Structure is applicable to main control module and is also applicable to customizable module as shown in Figure 3, in module, main processing node is comprised of two Xilinx Virtex-5 FX200T FPGA, monolithic FPGA has been embedded in two PowerPC processor stones, and processor core completes and the communicating by letter of peripherals by inner PLB bus.Every FPGA outside has independently storage resources: DDR2 SDRAM, FLASH, QDR2 SDRAM and the guiding PROM that powers on; Every FPGA outside has independently communication interface: Ethernet interface, Serial RapidIO interface, LVDS communication bus, RocketIO communication bus; Every FPGA outside has independently debugging interface: RS232 interface.Every FPGA outside also has independently DVI display interface, the demonstration of reshuffling for local dynamic station and checking.Meanwhile, every FPGA realizes 8 road GPIO interfaces, realizes the I/O of module and interrupts controlling.
Inside modules realizes the totally interconnected exchange network of Serial RapidIO, and each FPGA node Chu Yi road 4x RapidIO is to inside modules exchange chip, and Chu Yi road 4x RapidIO is interfaced to back plane connector.Meanwhile, exchange chip is externally exported 2 road 4x RapidIO and is interfaced to back plane connector, forms a complete interconnected multichannel Serial RapidIO high-speed serial network.
Figure 4 shows that main controlled node theory diagram, main controlled node is responsible for control, the management and running of whole system, by RapidIO bus, customizable functionality module is reshuffled, make customizable module realize various configurations function, utilize the local dynamic station reconfiguration technology of FPGA, main control module can also carry out reshuffling of partial function to it in customizable functionality module operational process, and this Local Gravity And configuration can not affect the normal operation of other parts.Master control FPGA is configured to one and has the programmable system on chip that enriches peripheral interface in power up, comprises in high-performance PowerPC processor core, DDR2 steering logic, large capacity storage FLASH steering logic, Ethernet steering logic, UART steering logic, discrete magnitude steering logic and responsible and module and RapidIO logic, RocketIO logic and LVDS communication logic that in system, other nodes communicate.Processor core, by each steering logic of PLB bus access in sheet, is completed and is reshuffled reshuffling the local dynamic station of FPGA by RapidIO communication interface.
Figure 5 shows that and reshuffle node theory diagram, reshuffle node and adopt FPGA reconfiguration technology, can be according to different application demands, the configuration order of response main controlled node, loads different configuration informations, carries out different functional tasks.Reshuffling intra-node divides static part and reshuffles region, static part is that system can normally be moved needed least part, comprise high-performance PowerPC processor core, DDR2 steering logic, large capacity storage FLASH steering logic, Ethernet steering logic, UART steering logic, discrete magnitude steering logic, QDR2 steering logic, DVI display control logic, to specify reshuffle region carry out the ICAP interface logic of local dynamic station configuration and be responsible for module in system in the RapidIO logic that communicates of other nodes, RocketIO logic and LVDS communication logic.Processor core is by each steering logic of PLB bus access in sheet, in operation Processing tasks, can also respond the reconfigure command of being sent by master control FPGA, according to the different demands of system, the ICAP interface local bit stream file that transmission comes according to master control FPGA reshuffles by appointment the logical circuit that area configurations becomes to have difference in functionality.System, in power up, is reshuffled node and is only configured to a functional circuit with static part, reshuffles region and can in system operational process, according to the different demands of system, by main controlled node, be completed the local dynamic station of this part is configured.
System is in service, master control FPGA internal logic circuit remains constant, this part function also needs own peripheral resource to carry out periodic self check when carrying out Processing tasks, also need for No. ID, the RapidIO link configuration of whole system, in addition, main controlled node also needs periodically to collect the whether true(-)running of each node.The running status of the periodic collector node of reprovision FPGA inside in system operational process, and periodically to master control FPGA, report the running status of oneself.
System is in service, master control FPGA carries out local dynamic station and reshuffles reshuffling FPGA according to the concrete operation demand of system, the local bit stream file that is applicable to reshuffling FPGA has designed and has been stored in the mass-memory unit of master control FPGA periphery in advance, the embedded processor of master control FPGA completes the management of these files and transmission work, and completes the monitoring function to reconfiguration course.Whole reconfiguration course is as follows: the FPGA that master control FPGA reshuffles to needs sends reconfigure command, reshuffles FPGA and stops and reshuffling the relevant all tasks in region after receiving this order, and reshuffle ready information to master control FPGA feedback; Master control FPGA takes out and reshuffles accordingly bit stream after receiving ready information from outside mass-memory unit, and transfers to the corresponding node of reshuffling by RapidIO host-host protocol; Reshuffle node and send an interrupt request at the processor core to intra-node after bit stream of reshuffling of receiving this part, now this processor core is collected corresponding bit stream file, and write in the ICAP interface of FPGA inside, by ICAP interface logic, complete the local dynamic station reshuffle region to specifying and configure, thus the customization function of whole system.
Claims (5)
1. the customizable embedded processing systems based on FPGA reconfiguration technology, is characterized in that: comprise main control module, Switching Module and at least one customizable functionality module,
Described main control module comprises at least one main controlled node, between described main controlled node and main controlled node, interconnects,
Described Switching Module comprises at least one exchange chip, between described exchange chip and exchange chip, interconnects,
Described customizable functionality module comprises that at least one reshuffles node, described in reshuffle node for reshuffling FPGA, described in reshuffle node and reshuffle between node and interconnect,
Described main control module interconnects by Switching Module and customizable functionality module, between described customizable functionality module and customizable functionality module, by Switching Module, is connected.
2. the customizable embedded processing systems based on FPGA reconfiguration technology according to claim 1, described main controlled node is one or more of FPGA, CPU, DSP.
3. the customizable embedded processing systems based on FPGA reconfiguration technology according to claim 2, is characterized in that: described in reshuffle FPGA and comprise static part and reshuffle region,
Described static part comprises processor, bus control logic, store control logic, communication interface logic, reshuffles steering logic,
Described store control logic, communication interface logic, reshuffle steering logic and be connected with bus control logic respectively,
Described reshuffle steering logic by bus control logic with reshuffle joint area,
Described processor passes through each logic of bus control logic access static part,
Described processor is configured by reshuffling steering logic counterweight configuring area,
Described processor is by communication interface logical and master control FPGA and/or reshuffle FPGA and communicate by letter.
4. the customizable embedded processing systems based on FPGA reconfiguration technology according to claim 3, is characterized in that: described exchange chip is RapidIO exchange chip.
5. the customizable embedded processing systems based on FPGA reconfiguration technology according to claim 4, it is characterized in that: between described main controlled node and main controlled node, by RapidIO exchange chip, be connected, described in reshuffle node and by RapidIO exchange chip, be connected with reshuffling between node.
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| CN104394150A (en) * | 2014-11-26 | 2015-03-04 | 大连梯耐德网络技术有限公司 | System and method for implementing mimic security network architecture based on hardware reconfiguration |
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| WO2018114957A1 (en) | 2016-12-19 | 2018-06-28 | Centre National De La Recherche Scientifique | Parallel processing on demand using partially dynamically reconfigurable fpga |
| CN108696390A (en) * | 2018-05-09 | 2018-10-23 | 济南浪潮高新科技投资发展有限公司 | A kind of software-defined network safety equipment and method |
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| CN108924377A (en) * | 2018-06-08 | 2018-11-30 | 宁波华高信息科技有限公司 | A kind of quick method for reconfiguration of the hardware-compressed core based on DSP |
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Application publication date: 20140326 |