CN103677081B

CN103677081B - The processing method and processing meanss of data signal

Info

Publication number: CN103677081B
Application number: CN201310745643.4A
Authority: CN
Inventors: 黄帅; 王焕东; 陈新科
Original assignee: Loongson Technology Corp Ltd
Current assignee: Loongson Technology Corp Ltd
Priority date: 2013-12-30
Filing date: 2013-12-30
Publication date: 2017-03-15
Anticipated expiration: 2033-12-30
Also published as: CN103677081A

Abstract

The invention discloses a kind of processing method of data signal and processing meanss.Wherein, the method includes：5th data signal and the 6th data signal are obtained according to the first data signal, the second data signal, the 3rd data signal and the 4th data signal；Obtain the 3rd clock signal, and when second clock signal is located at the first pre-set interval relative to the phase contrast of the 3rd clock signal, the 5th data signal and the 6th data signal are gathered using the rising edge of the 3rd clock signal, when phase contrast is located at the second pre-set interval, the 5th data signal and the 6th data signal is gathered using the trailing edge of the 3rd clock signal；9th data signal is obtained according to the 8th data signal obtained by the 6th data signal of the 7th data signal obtained by the 5th data signal of collection and collection.The present invention solves the technical problem of timing margins of the uncontrollable data signal in the transmission path that cross clock domain is transmitted in prior art.

Description

The processing method and processing meanss of data signal

Technical field

The present invention relates to electronic circuit field, in particular to a kind of processing method of data signal and processing meanss.

Background technology

In the scheme of the cross clock domain transmission of existing data signal, it will usually gone using the hopping edge of a clock signal Collection data signal corresponding with another clock signal, to obtain data signal corresponding with preceding clock signal.But In this scheme, timing margins of the data signal in the transmission path that cross clock domain is transmitted be uncontrollable and uncertain, Its timing margins can be larger in one case, it is also possible to less in another scenario, and when timing margins are less, by The persistent period of the value after the data signal as acquisition target updates is shorter, and its data mode is relative and unstable, therefore The data for collecting also are inaccurate, the reliability that the cross clock domain so as to have impact on data signal is transmitted.In other words, existing There is scheme ensure to meet the requirement to timing margins, and its reason can then be attributed to uncontrollable data in prior art The problem of timing margins of the signal in the transmission path that cross clock domain is transmitted.

For above-mentioned problem, effective solution is not yet proposed at present.

Content of the invention

A kind of processing method of data signal and processing meanss are embodiments provided, at least to solve prior art In timing margins of the uncontrollable data signal in the transmission path that cross clock domain is transmitted technical problem.

A kind of one side according to embodiments of the present invention, there is provided processing method of data signal, including：According to first Data signal, the second data signal, the 3rd data signal and the 4th data signal obtain the 5th data signal and the 6th data letter Number, wherein, above-mentioned first data signal, above-mentioned second data signal, above-mentioned 3rd data signal and above-mentioned 4th data signal Corresponding with the first clock signal, above-mentioned 5th data signal and above-mentioned 6th data signal corresponding with second clock signal, above-mentioned Second clock signal is double frequency multiplied clock signals of above-mentioned first clock signal, and the rising edge of above-mentioned first clock signal with upper The rising edge alignment of second clock signal is stated, wherein, when above-mentioned first clock signal is 1, above-mentioned 5th data signal is corresponding Above-mentioned first data signal, corresponding above-mentioned 3rd data signal of above-mentioned 6th data signal is 0 in above-mentioned first clock signal When, corresponding above-mentioned second data signal of above-mentioned 5th data signal, corresponding above-mentioned 4th data signal of above-mentioned 6th data signal； The 3rd clock signal is obtained, and pre- positioned at first relative to the phase contrast of above-mentioned 3rd clock signal in above-mentioned second clock signal If when interval, gathering above-mentioned 5th data signal and above-mentioned 6th data signal using the rising edge of above-mentioned 3rd clock signal, When above-mentioned phase contrast is located at the second pre-set interval, above-mentioned 5th data letter is gathered using the trailing edge of above-mentioned 3rd clock signal Number and above-mentioned 6th data signal, wherein, the clock cycle of above-mentioned 3rd clock signal and the clock of above-mentioned second clock signal Cycle phase is same；According to the 7th data signal obtained by above-mentioned 5th data signal of collection and above-mentioned 6th data signal of collection The 8th obtained data signal obtains the 9th data signal, wherein, when above-mentioned 3rd clock signal is 1, above-mentioned 9th number It is believed that number corresponding above-mentioned 7th data signal, when above-mentioned 3rd clock signal is 0, above-mentioned 9th data signal corresponding above-mentioned the Eight data signals.

Another aspect according to embodiments of the present invention, additionally provides a kind of processing meanss of data signal, including：Obtain single Unit, for obtaining the 5th data letter according to the first data signal, the second data signal, the 3rd data signal and the 4th data signal Number and the 6th data signal, wherein, above-mentioned first data signal, above-mentioned second data signal, above-mentioned 3rd data signal and on State the 4th data signal corresponding with the first clock signal, above-mentioned 5th data signal and above-mentioned 6th data signal and second clock Signal is corresponding, and above-mentioned second clock signal is double frequency multiplied clock signals of above-mentioned first clock signal, and above-mentioned first clock is believed Number rising edge and above-mentioned second clock signal rising edge alignment, wherein, when above-mentioned first clock signal is 1, above-mentioned the Corresponding above-mentioned first data signal of five data signals, corresponding above-mentioned 3rd data signal of above-mentioned 6th data signal, above-mentioned the When one clock signal is 0, corresponding above-mentioned second data signal of above-mentioned 5th data signal, above-mentioned 6th data signal are corresponding above-mentioned 4th data signal；Select unit, for obtaining the 3rd clock signal, and in above-mentioned second clock signal relative to the above-mentioned 3rd When the phase contrast of clock signal is located at the first pre-set interval, using above-mentioned 5th number of the rising edge collection of above-mentioned 3rd clock signal It is believed that number and above-mentioned 6th data signal, above-mentioned phase contrast be located at the second pre-set interval when, using above-mentioned 3rd clock signal Trailing edge gather above-mentioned 5th data signal and above-mentioned 6th data signal, wherein, the clock week of above-mentioned 3rd clock signal Phase is identical with the clock cycle of above-mentioned second clock signal；Processing unit, for according to the above-mentioned 5th data signal gained of collection The 8th data signal obtained by the 7th data signal for arriving and above-mentioned 6th data signal of collection obtains the 9th data signal, Wherein, when above-mentioned 3rd clock signal is 1, corresponding above-mentioned 7th data signal of above-mentioned 9th data signal, the above-mentioned 3rd When clock signal is 0, corresponding above-mentioned 8th data signal of above-mentioned 9th data signal.

In embodiments of the present invention, employing makes according to the phase contrast between second clock signal and the 3rd clock signal With the rising edge or trailing edge pair of the 3rd clock signal the 5th data signal corresponding with second clock signal and the 6th data Signal carries out the mode of selection between being acquired, with obtain corresponding with the 3rd clock signal, relative to the 3rd clock signal with 9th data signal of the requirement of the timing margins of Double Data Rate transmission and satisfaction to cross clock domain transmission on the transmit path, Wherein, to the control of the timing margins can by above-mentioned selection mechanism setting with reference to the first pre-set interval and the second pre-set interval Put to realize, and then solve sequential of the uncontrollable data signal in the transmission path that cross clock domain is transmitted in prior art The technical problem of nargin.Further, in embodiments of the present invention, can be by the first pre-set interval and the second pre-set interval Reasonable setting meet the design requirement that the cross clock domain to data signal is transmitted, and improve the cross clock domain transmission of data signal Reliability.

Description of the drawings

Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the application, this Bright schematic description and description does not constitute inappropriate limitation of the present invention for explaining the present invention.In the accompanying drawings：

Fig. 1 is a kind of schematic diagram of the processing method of data signal according to embodiments of the present invention；

Fig. 2 is a kind of schematic diagram of the cross clock domain transmission of the data signal according to prior art；

Fig. 3 is the schematic diagram of the cross clock domain transmission of another kind of data signal according to prior art；

Fig. 4 is a kind of schematic diagram of the cross clock domain transmission of data signal according to embodiments of the present invention；

Fig. 5 is the schematic diagram of the cross clock domain transmission of another kind of data signal according to embodiments of the present invention；

Fig. 6 is a kind of schematic diagram of the processing meanss of data signal according to embodiments of the present invention；

Fig. 7 is the schematic diagram of the processing meanss of another kind of data signal according to embodiments of the present invention.

Specific embodiment

Below with reference to accompanying drawing and in conjunction with the embodiments describing the present invention in detail.It should be noted that not conflicting In the case of, the feature in embodiment and embodiment in the application can be mutually combined.

Embodiment 1

According to embodiments of the present invention, there is provided a kind of processing method of data signal, as shown in figure 1, the processing method bag Include：

S102：The 5th is obtained according to the first data signal, the second data signal, the 3rd data signal and the 4th data signal Data signal and the 6th data signal, wherein, the first data signal, the second data signal, the 3rd data signal and the 4th data Signal is corresponding with the first clock signal, and the 5th data signal and the 6th data signal are corresponding with second clock signal, and when second Clock signal is double frequency multiplied clock signals of the first clock signal, wherein, when the first clock signal is 1, the 5th data signal pair The first data signal, the 6th data signal is answered to correspond to the 3rd data signal, when the first clock signal is 0, the 5th data signal Corresponding second data signal, corresponding 4th data signal of the 6th data signal；

S104：The 3rd clock signal is obtained, and is located at relative to the phase contrast of the 3rd clock signal in second clock signal During the first pre-set interval, the 5th data signal and the 6th data signal is gathered using the rising edge of the 3rd clock signal, in phase place When difference is located at the second pre-set interval, the 5th data signal and the 6th data signal is gathered using the trailing edge of the 3rd clock signal, Wherein, the clock cycle of the 3rd clock signal is identical with the clock cycle of second clock signal；

S106：According to the 6th data signal gained of the 7th data signal obtained by the 5th data signal of collection and collection The 8th data signal that arrives obtains the 9th data signal, wherein, when the 3rd clock signal is 1, the 9th data signal corresponding the Seven data signals, when the 3rd clock signal is 0, corresponding 8th data signal of the 9th data signal.

It will be clear that one of technical solution of the present invention technical problem to be solved be to provide a kind of to data signal The method for being processed, to realize that the frequency multiplication cross clock domain to the data entrained by 4 circuit-switched data signals is transmitted, of the invention real Apply in example, the 4 circuit-switched data signal can be expressed as the first data signal, the second data signal, the 3rd data signal and Four data signals, the output data as result can carry the data entrained by first to fourth data signal 9th data signal, wherein, first to fourth data signal is corresponding with the first clock signal, the 9th data signal and the 3rd clock Double frequency multiplied clock signals of signal are corresponding, and the clock cycle of the first clock signal is the two of the clock cycle of the 3rd clock signal Times.

In embodiments of the present invention, the corresponding relation between first to fourth data signal and the first clock signal generally may be used It is mutually aligned with showing the two, that is, the clock frequency of the renewal frequency of first to fourth data signal and the first clock signal Consistent, and the two phase place is identical, but the present invention is not construed as limiting to this, for example, in some embodiments of the invention, first Corresponding relation between data signal and the first clock signal can also show as the phase place of certain determination between homogenous frequency signal Relation, orthogonal or anti-phase etc., under this scene, although the first data signal with the first clock signal and is not lined up, but As phase relation therebetween determines and, it is known that therefore still can deduce the first number by the first inaccurate clock signal It is believed that number sequential, so as to the first data signal can still be considered as in the clock zone of the first clock signal.

Similarly, in embodiments of the present invention, the corresponding relation between the 9th data signal and the 3rd clock signal also may be used Similar to the corresponding relation between the first clock signal to above-mentioned first data signal to show as, it is important to note, however, that Not necessarily completely the same between the two corresponding relations, for example, in embodiments of the present invention, the first data signal can be with One clock signal alignment, and the 9th data signal can be anti-phase with the 3rd clock signal, the present invention is not construed as limiting to this.

The processing method of the data signal for providing according to embodiments of the present invention, in step s 102, can first to first Processed to the 4th data signal, to obtain the 5th data signal and the 6th data signal, wherein, the 5th data signal and Six data signals can be corresponding with the second clock signal of the double frequency-doubled signals as the first clock signal, and the 5th data signal The first data signal and the data entrained by the second data signal can be carried, and the 6th data signal can carry the 3rd Data entrained by data signal and the 4th data signal.Easy to understand, under above-mentioned scene, it is also possible to be considered as step S102 The 5th data signal that first data signal and the second data signal are merged into double frequency, and by the 3rd data signal and Four data signals merge into the 6th data signal of double frequency.

In embodiments of the present invention, the concrete implementation mode of step S102 can have multiple, for example, as one of which Optional mode, step S102 can include：

S1：First data signal and the 3rd data letter are gathered using the trailing edge of first clock signal Number, second data signal and the 4th data signal is gathered using the rising edge of first clock signal；Or, make First data signal and the 3rd data signal are gathered with the rising edge of first clock signal, using described first The trailing edge of clock signal gathers second data signal and the 4th data signal；

S2：When first clock signal is 1, will gather data signal obtained by first data signal as 5th data signal, using the data signal obtained by described for collection the 3rd data signal as the 6th data signal, When first clock signal is 0, using the data signal obtained by described for collection the second data signal as the described 5th number It is believed that number, using the data signal obtained by described for collection the 4th data signal as the 6th data signal.

Certainly, a kind of above simply example, in embodiments of the present invention, can also have multiple other frequency multiplication modes, example 0 and 1 can also exchange as Rule of judgment such as in step S2, the present invention are not construed as limiting to this.

On the basis of above description, the processing method of the data signal for providing according to embodiments of the present invention, in step In S104, can further realize the 5th data signal and the 6th data signal from the clock zone of second clock signal to the 3rd The cross clock domain transmission of the clock zone of clock signal, in order in step s 106 according to the 7th obtained after cross clock domain transmission Data signal and the 8th data signal obtain the process of the 9th data signal corresponding with double frequency-doubled signals of the 3rd clock signal Operation.

Above description is based on, present invention problem to be solved in step S104 can also be expressed as：Will with second when Corresponding 5th data signal of clock signal and the 6th data signal are respectively converted into the 7th clock corresponding with the 3rd clock signal Signal and the 8th clock signal, wherein, the 5th data signal is identical with the content of the 7th data signal, but sequential has different, class As, the 6th data signal is identical with the content of the 8th data signal, but sequential have different.As the 5th data signal is to the 7th The cross clock domain transmission of data signal is similar to the cross clock domain transmission of the 8th data signal with the 6th data signal, below will be main The scheme of the embodiment of the present invention is described to the cross clock domain transmission of the 7th data signal around the 5th data signal.

For realizing above-mentioned cross clock domain transmission, in existing scheme, it will usually using the hopping edge of the 3rd clock signal Go to gather the 5th data signal, to obtain the 7th data signal, for example, in fig. 2 it is possible to using the 3rd as shown in the 3rd row The rising edge of clock signal gathers the 5th data signal as shown in the 2nd row, it is possible to by collecting, as shown in the 4th row Data signal as the 7th data signal, wherein, figure it is seen that the 5th data signal is corresponding with second clock signal, 7th data signal is corresponding with the 3rd clock signal, so as to realize the transmission of the cross clock domain of data signal.

It can easily be seen that in fig. 2, the 5th data signal as shown in the 2nd row is to the 7th data signal as shown in the 4th row Transmission path on timing margins t1 be more than half clock cycle T/2, wherein T represents the clock cycle of second clock signal, That is, using the 3rd clock signal rising edge gather five data signals when, the 5th data signal be updated to numerical value a this The persistent period of one state has exceeded T/2, so as to the data mode comparatively more easily from by numerical value update produced by Recover and be transitioned into relatively stable state in the disturbance such as burr, and then the rising edge using the 3rd clock signal is gathered Also more accurately, this is favourable for the cross clock domain transmission of data signal to the data for obtaining.

However, in fact, for above-mentioned existing scheme, data signal is in the transmission path that cross clock domain is transmitted Timing margins are uncertain, and under a scene, such as situation shown in Fig. 2, its timing margins are larger, in another scene Under, such as situation shown in Fig. 3, t2 is then relatively small for its timing margins, at least below half clock cycle, then under the scene When gathering five data signals using the rising edge of the 3rd clock signal, as the 5th data signal is updated to continuing for numerical value a Time is shorter, and therefore its data mode is possible and unstable, and the data for thus collecting also are inaccurate, so as to have impact on number It is believed that number cross clock domain transmission reliability.In other words, the rising edge using the 3rd clock signal gathers the 5th data letter Number cannot ensure to meet requirement to above-mentioned timing margins in the way of generating the 7th data signal, correspondingly, using the The trailing edge of three clock signals gathers the 5th data signal and there is also similar problem in the way of generating the 7th data signal, and Its reason can then be attributed to sequential of the uncontrollable data signal in the transmission path that cross clock domain is transmitted in prior art The problem of nargin.

For solving this problem, in embodiments of the present invention, the 5th data can be gathered along holding using the 3rd clock signal Signal is in the way of generating the 7th data signal, and obtains the 5th data signal and the 3rd clock letter in step s 102 Number, but prior art is different from, the processing method for providing according to embodiments of the present invention, in step S104, can be according to the Phase relation between two clock signals and the 3rd clock signal using the 3rd clock signal rising edge or trailing edge it Between selected, wherein, if second clock signal relative to the 3rd clock signal phase contrast be located at the first pre-set interval, can 5th data signal is gathered with the rising edge using the 3rd clock signal, if phase contrast is located at the second pre-set interval, can be made The 5th data signal is gathered with the trailing edge of the 3rd clock signal.In other words, in embodiments of the present invention, not statically make Gather the 5th data signal with the rising edge of the 3rd clock signal or trailing edge, but can with relative dynamic for different Situation selects one of rising edge and trailing edge to be acquired, so as to realize to data signal in the transmission path of clock transfer Timing margins control, and then reach the requirement to the timing margins.

It should be noted that above-mentioned " dynamically " selects to be not limited to select in real time, in embodiments of the present invention, Carry out between " rising edge collection " and " trailing edge collection " selection cycle can be a shorter time cycle, or One longer time cycle, additionally, the mechanism of the selection can be to intercouple with other mechanism, such as judgment mechanism, its In, result that this selection can also be according to produced by judgment mechanism triggering, etc. the present invention is not construed as limiting to this.Additionally, making For optional embodiment, above-mentioned selection mechanism both can be by hardware logic, and such as logic circuit is realizing, it is possible to enter one It is encapsulated in physical interface with raising integrated level and processing speed to step, and reduces the processing pressure of processor, which can also leads to Software logic is crossed, for example, the programmable platforms such as MCU, FPGA or PLC is programmed to, the present invention is not construed as limiting to this.

The operation principle of the scheme of the embodiment of the present invention is explained in detail below in conjunction with Fig. 4 and Fig. 5.In the present invention In embodiment, above-mentioned first pre-set interval could be arranged to（T/2, T）, above-mentioned second pre-set interval could be arranged to（0, T/2）. It should be noted that in this application, relative to the phase contrast of the 3rd clock signal, second clock signal represents that second clock is believed Number relative to the 3rd clock signal lead, for example, if second clock signal relative to the 3rd clock signal in advance 1/4 The clock cycle, then second clock signal is 1/4 clock cycle relative to the phase contrast of the 3rd clock signal.

As shown in figure 4, under a scene of the embodiment of the present invention, when second clock signal can be as shown in the 1st row Clock signal, the 5th data signal can be the data signal as shown in the 2nd row, and the 3rd clock signal can be as shown in the 3rd row Clock signal.Under above-mentioned scene, second clock signal is all more than half clock relative to the phase contrast of the 3rd clock signal Phase, namely it is located at the first pre-set interval（T/2, T）Interior, so as to according to step S104, select using the 3rd clock signal Rising edge gathers the 5th data signal, and obtains the data signal as shown in the 4th row as the 7th data signal.It can easily be seen that Under above-mentioned scene, the 5th data signal is corresponding with second clock signal, and the 7th data signal is corresponding with the 3rd clock signal, and The data content of the 7th data signal is consistent with the 5th data signal, namely achieves the cross clock domain biography of the 5th data signal Defeated, on the other hand, the timing margins in the transmission path of the cross clock domain transmission are equal to above-mentioned phase contrast, and above-mentioned phase contrast It is located in the first pre-set interval, is more than half clock cycle, therefore the timing margins are more than half clock cycle, that is, at this In inventive embodiments, the control of timing margins partly can be realized by the first pre-set interval, such that it is able to by The reasonable setting of one pre-set interval is to meet the requirement to the timing margins, and then reaches gathered data exactly and improve The effect of the reliability of the cross clock domain transmission of data signal.

As a comparison, under above-mentioned scene, if selecting the trailing edge of the 3rd clock signal to gather the 5th data signal, To data signal can be if the 5th rows of Fig. 4 are by the data signal of expression of tiltedly ruling, it will therefore be readily appreciated that the data letter for collecting Number relative to the 5th data signal timing margins be less than half clock cycle, and do not meet corresponding with the first pre-set interval right The requirement of above-mentioned timing margins, and then the relatively low problem of reliability that the cross clock domain of data signal may be caused to transmit.

As shown in figure 5, under another scene of the embodiment of the present invention, second clock signal can be as shown in the 1st row Clock signal, the 5th data signal can be the data signal as shown in the 2nd row, and the 3rd clock signal can be such as the 3rd row institute The clock signal that shows.Under above-mentioned scene, second clock signal is less than half clock relative to the phase contrast of the 3rd clock signal Cycle, namely it is located at the second pre-set interval（0, T/2）Interior, so as to according to step S104, select using the 3rd clock signal Trailing edge gather the 5th data signal, and obtain the data signal as shown in the 5th row as the 7th data signal.Easily see Go out, under above-mentioned scene, on the basis of the cross clock domain for realizing the 5th data signal is transmitted, the transmission of the cross clock domain transmission Timing margins on path are equal to above-mentioned phase contrast and add half clock cycle, and above-mentioned phase contrast is located at the second pre-set interval Interior, be less than half clock cycle, therefore the timing margins are more than half clock cycle, that is, in embodiments of the present invention, pair when The control of sequence nargin partly can be realized by the second pre-set interval, such that it is able to by rationally setting to the second pre-set interval Put to meet the requirement to the timing margins, and then reach gathered data exactly and improve the cross clock domain of data signal The effect of the reliability of transmission.

As a comparison, under above-mentioned scene, if selecting the rising edge of the 3rd clock signal to gather the 5th data signal, To data signal can be if the 4th rows of Fig. 5 are by the data signal of expression of tiltedly ruling, it will therefore be readily appreciated that the data letter for collecting Number relative to the 5th data signal timing margins be less than half clock cycle, and do not meet corresponding with the second pre-set interval right The requirement of above-mentioned timing margins, and then the relatively low problem of reliability that the cross clock domain of data signal may be caused to transmit.

By above-described embodiment, the operation principle of the scheme of the embodiment of the present invention is set forth.Accordingly, at this In bright embodiment, it is also possible to take similar mode to be processed the 6th data signal to obtain the 8th data signal, and can To solve the problems, such as identical and reach identical effect, here of the present invention does not make tired stating.

It should be noted that in embodiments of the present invention, for the first pre-set interval, its timing margins for being limited First pre-set interval itself is generally, and for the second pre-set interval, when the partial section quilt in the second pre-set interval It is set to be located at（0, T/2）When, the timing margins limited by the partial section add half clock cycle as the partial section, When the partial section in the second pre-set interval is arranged to be located at（T/2, T）When, then the sequential for being limited by the partial section is abundant Degree actually appears the partial section and deducts half clock cycle.That is, if it is desired to the cross clock domain of data signal is passed Defeated timing margins on the transmit path are larger, then can be arranged on the first pre-set interval（T/2, T）Interior, and second is preset Interval is arranged on（0, T/2）Interior, on the contrary then the two can be exchanged, the first pre-set interval is arranged on（0, T/2）Interior, and by Two pre-set intervals are arranged on（T/2, T）Interior.For the concrete setting and its application of the first pre-set interval and the second pre-set interval, this Invention is not limited in any way.

Certainly, above-mentioned conclusion is mainly based upon the 5th data signal and second clock signal alignment and the 7th data signal The corresponding relation alignd with the 3rd clock signal is derived, in some other embodiment of the present invention, for the corresponding pass Other forms of expression of system, can be in conjunction with the phase relation of the determination between the 5th data signal and second clock signal and the The phase relation of the determination between seven data signals and the 3rd clock signal, draws through corresponding with the two phase relations two The scope of the timing margins for being limited by the first pre-set interval and the second pre-set interval respectively after secondary skew, and be similarly processed Mode can also be applied to the 6th data signal and carry out the process of cross clock domain transmission to the 8th data signal, and here of the present invention is not Make tired stating.

On the basis of above description, the processing method of the data signal for providing according to embodiments of the present invention, in step In S106, the 9th data signal can be obtained according to the 7th data signal and the 8th data signal, wherein, in the embodiment of the present invention In, the process of frequency multiplication mode similar with the implementation of aforementioned step S102 can have both been taken in the realization of step S106, also may be used So that according to specific design needs, before the 9th data signal is obtained, the 7th data signal and the 8th data signal are carried out can Other capable process, such as delay, anti-phase, collection, one bat of deposit or many bats etc. again, and according to the data letter obtained after process Number generate the 9th data signal, it should be understood that, in above-mentioned processing procedure, all should work as and belong in the 3rd clock signal Clock zone in process, that is, the 9th data signal for being obtained still should be corresponding with the 3rd clock signal.

For example, alternatively, in embodiments of the present invention, step S106 can include：

S3：Execute below n times to operate：The n times are operated using the rising edge or trailing edge of the 3rd clock signal In the data signal that collected of front once-through operation gathered again, wherein, adopt in the front once-through operation of the n times operation The initial value of the data signal for collecting is the 7th data signal, and N is more than or equal to 1；And/or,

S4：Execute M following operation：Described M time is operated using the rising edge or trailing edge of the 3rd clock signal In the data signal that collected of front once-through operation gathered again, wherein, front once-through operation institute in the M operation The initial value of the data signal for collecting is the 8th data signal, and M is more than or equal to 1；

S5：When the 3rd clock signal is 1, will gather after the 7th data signal or n times operation The data signal for arriving as the 9th data signal, when first clock signal is 0, by the 8th data signal or The data signal collected after M operation described in person is used as the 9th data signal.

Under above-mentioned scene, the 5th data signal and the 6th data signal can be acquired by step S104 Afterwards, the 5th data signal and/or the 6th data signal are gathered again in step S3 and/or step S4, and should " again The operation of collection " can repeat n times and M time respectively, and N, M are more than or equal to 1, wherein it is desired to illustrate, of the invention real Apply in example, above-mentioned n times are not necessarily limited to be " using the rising edge of the 3rd clock signal " or " using the 3rd clock signal Trailing edge ", for example, in one embodiment, n times operation in certain once-through operation can be gathered using rising edge, the operation Next operation can be gathered using trailing edge, similarly, above-mentioned M operation be also not limited to be using rising edge or under Drop edge, the present invention are not construed as limiting to this.

It should be appreciated that in embodiments of the present invention, the n times for being carried out using the hopping edge of the 3rd clock signal respectively and M time Data signal obtained by acquisition operations will be in the clock zone of the 3rd clock signal again, the 9th data for obtaining accordingly Signal is also by the clock zone of the 3rd clock signal.Generally, for including counting to the 5th described in step S104 It is believed that number and the acquisition operations of the 6th data signal used the rising of the 3rd clock signal at interior above-mentioned " front once gather " The situation on edge, for the collection again carried out after the front once collection, if still using the rising edge of the 3rd clock signal, Equivalent to the front data signal for once collecting being delayed a clock cycle or saying one bat of deposit, if being changed to use The trailing edge of the 3rd clock signal, then equivalent to by the front data signal for once collecting delay half clock cycle or Person says that deposit half is clapped, accordingly, for front once collection has used the situation of the trailing edge of the 3rd clock signal, it is also possible to obtain Similar effect.Wherein, either deposit half is clapped, one claps or the situation that claps more, and the timing margins in gathering again are at least Half clock cycle, therefore can avoid accuracy caused by the not enough institute of the timing margins due to data signal on the transmit path Problem with reliability decrease.

Further, for ease of step S5 in the 9th data signal acquisition, the invention provides following two optional Specific embodiment above-mentioned n times are operated and M operation is defined, to realize counting to the 7th in step S3 and/or S4 It is believed that number and/or the 8th data signal pretreatment：

1）If above-mentioned phase contrast is located at the first pre-set interval, the n times operation in step S3 can be：Using the 3rd clock The trailing edge of signal is gathered again to the 7th data signal, and M operation in step S4 can be：Believed using the 3rd clock Number rising edge the 8th data signal is gathered again；

If above-mentioned phase contrast is located at the second pre-set interval, M operation in step S4 is：Using the 3rd clock signal Rising edge is gathered again to the 8th data signal.

2）If above-mentioned phase contrast is located at the first pre-set interval, M operation in step S4 can be：Using the 3rd clock The trailing edge of signal is gathered again to the 8th data signal；

If above-mentioned phase contrast is located at the second pre-set interval, the n times operation in step S3 can be：Believed using the 3rd clock Number rising edge the 7th data signal is gathered again, M operation in step S4 can be：Using the 3rd clock signal Trailing edge the 8th data signal is gathered again.

By above-described embodiment The present invention gives two kinds of optional specific embodiments, it being understood, however, that above-mentioned reality Apply example and be only used for the understanding to technical solution of the present invention, should not be considered as limitation of the invention.In embodiments of the present invention, also The embodiment that can have other feasible, here is not tired one by one to be stated, it will be appreciated that these embodiments are regarded as in the present invention Protection domain within.

On the basis of above description, more specifically, in embodiments of the present invention, above-mentioned first clock signal can be interior The system clock of memory controller, above-mentioned second clock signal is double frequency doubling clocks of the system clock, above-mentioned 3rd clock signal Data clock can be write for Memory Controller Hub, above-mentioned first data signal, the second data signal, the 3rd data signal and the 4th Data signal can be Memory Controller Hub data to be transmitted, above-mentioned 9th data signal can be Memory Controller Hub to internal memory core Data are write in piece transmission, and wherein, this is write data clock and the clock cycle of the internal memory clock of memory chip and with identical, and can write number According to default timing requirements can be met between clock and internal memory clock.

Under this scene, in conjunction with the processing method of data signal provided in an embodiment of the present invention, it is possible to achieve to be transmitted Effective transmission of the data from Memory Controller Hub to memory chip, wherein, the data to be transmitted can be obtained by Memory Controller Hub Or the data signal corresponding with system clock for generating, and writing data and can be and write obtained by above-mentioned process operation The corresponding data signal of data clock, receives and recognizes to writing data in order to internal memory.Wherein, also may be used although writing data clock To be obtained or generated by Memory Controller Hub, however this write should meet between data clock and internal memory clock default sequential will Ask.The adjustment operation for writing data clock will be given in subsequent embodiment.

In general, in embodiments of the present invention, above-mentioned default timing requirements can generally show as：During according to writing data The data of writing of clock generation shift to an earlier date K clock cycle when memory chip is reached relative to internal memory clock, and K is any between 0 to 1 Value.This requirement is generally related to DDR agreements, for example, when existing DDR agreements regulation is write data to up to memory chip, internal memory The hopping edge of clock should be located at the middle part that this that obtained by memory chip writes data, and this is write data to up to memory chip in other words When should shift to an earlier date about 1/4 or 3/4 clock cycle relative to internal memory clock, so as to K could be arranged to 1/4 or 3/4, however this Invention is not construed as limiting to this, and in some other embodiment of the present invention, for different internal storage data host-host protocols, K's is concrete It is worth other numerical value it can also be provided that between 0 to 1.

Still optionally further, in embodiments of the present invention, before step S102, above-mentioned processing method can also include：

S6：Before termination execution condition corresponding with default timing requirements is met, P following operation is repeated：

S7, forward or backward adjustment write data clock or relative to writing the 4th of the data clock delayed K clock cycle Clock signal, and to memory chip transmission and the 4th clock signal corresponding the after writing data clock or adjusting after adjustment Ten data signals；

The 11st data signal that S8, reception memory chip are returned according to the tenth data signal, and according to the tenth for receiving One data signal judges whether to meet termination execution condition；Wherein, P is more than or equal to 1.

May be summarized to be by the circulation formed by step S7 and S8：The process of adjustment conveying feedback, its In, to memory chip according to the 11st data signal fed back by the tenth data signal conveyed to which can generally carry with " whether meeting termination execution condition " " writes " phase in other words Corresponding information, therefore judges to may determine that whether circulation terminates by the identification to the 11st data signal, it is possible to Write data clock or according to determined by the 4th clock signal that obtains after P time operates obtained by after above-mentioned P time is operated The 3rd clock signal determined before data clock is transmitted is write as the cross clock domain for carrying out data signal, using as step S104 The middle basis for carrying out selection according to phase contrast.It should be noted that above-mentioned circulation can also have other equivalent variations, for example, A similar circulation can also be summarised as：The process that conveying feedback is adjusted according to feedback, the present invention is to P time The division of one cycle in other words of the single operation of operation is simultaneously not construed as limiting, all should based on each specific embodiment described above It is considered as within protection scope of the present invention.

In general, in embodiments of the present invention, the termination of above-mentioned P operation executes condition and can correspond to default sequential Require reach, for example, in one embodiment, the tenth data signal could be arranged to the rising edge with the 4th clock signal or The pulse signal of trailing edge alignment, the 11st data signal can represent that memory chip uses pulse signal acquisition internal memory clock institute The data signal for obtaining, wherein, if the rising edge alignment of the tenth data signal and the 4th clock signal, terminating execution condition can Think：The 11st data signal for receiving is changed into 1 from 0；If the tenth data signal is alignd with the trailing edge of the 4th clock signal, Stopping execution condition can be：The 11st data signal for receiving is changed into 0 from 1.

Wherein, as the 4th clock signal is relative to the data clock delayed K clock cycle is write, therefore if it is desired to according to writing The data of writing of data clock generation shift to an earlier date K clock cycle when memory chip is reached relative to internal memory clock, then should require According to the 4th clock signal generate the tenth data signal reach memory chip when with internal memory clock alignment.On the other hand, The 11st data signal obtained by the tenth data signal acquisition internal memory clock that memory chip is received according to which is changed into from 0 When 1, the rising edge that the pulse signal as the tenth data signal captures the 11st data signal can be considered as, when the 11st Data signal can be considered as, when 1 is changed into 0, the trailing edge that the pulse signal captures the 11st data signal.Therefore, if The rising edge alignment of ten data signals and the 4th clock signal, then termination execution condition corresponding with default timing requirements can set Be set to when the tenth data signal reaches memory chip and just capture the rising edge of internal memory clock, namely the 11st data signal by 0 is changed into 1, if the tenth data signal is alignd with the trailing edge of the 4th clock signal, termination corresponding with default timing requirements is held Row condition could be arranged to the trailing edge for just capturing internal memory clock when the tenth data signal reaches memory chip, namely the tenth One data signal is changed into 0 from 1.

Especially, for DDR3, in some embodiments of the invention, it is possible to use DDR3 internal memories are provided DDR3 internal memories, under this scene, first can be placed in write leveling patterns, and will be write by write leveling functions Data strobe signal（Write DQS）As the 4th clock signal, and then execute above-mentioned P operation.

Further, in embodiments of the present invention, due in the step s 7 to writing data clock and/or the 4th clock signal Adjustment can reflect the phase shift for writing data clock as the 3rd clock signal, therefore can also be operated according to above-mentioned P time The second clock signal and the phase contrast of the 3rd clock signal that adjust to draw alternatively foundation in step S104 for being completed. Wherein, alternatively,

Before P operation is executed, above-mentioned processing method can also include：S9, the clock signal that will be alignd with system clock As the initial value for writing data clock or the 4th clock signal；

When P operation is executed, adjusted in step S7 forward or backward write data clock and/or the 4th clock signal can be with Including：S10, postpone write data clock or the 4th clock signal 1/L clock cycle, as adjustment after write data clock or The 4th clock signal of person, L is positive integer；And,

After P operation is executed, above-mentioned processing method can also include：If the clock alignd with system clock is believed by S11 Data clock is write in number conduct, then obtain phase contrast according to following formula：Δ=（P/L）*T；If the clock that S16 will be alignd with system clock Signal then obtains phase contrast according to following formula as the 4th clock signal：Δ=（P/L-K）*T；Wherein, Δ represents phase contrast, T tables Show the clock cycle.

Under above-mentioned scene, the value of L is bigger, then to writing the adjustment of data clock or the 4th clock signal in single operation Amount is less, and the calibration for writing data clock or the 4th clock signal to this is then about accurate, writes between data clock and internal memory clock Sequential then more for being close to default timing requirements, on the other hand, the phase difference that draws accordingly be also more accurate so that The processing method of above-mentioned data signal is more also accurate to the control of the timing margins in the transmission path of its cross clock domain transmission.

The invention provides a kind of preferred embodiment is further explaining to the present invention, but noticeable It is that the preferred embodiment is intended merely to the preferably description present invention, does not constitute and the present invention is improperly limited.

Embodiment 2

According to embodiments of the present invention, a kind of data signal for implementing the processing method of above-mentioned data signal is additionally provided Processing meanss, as shown in fig. 6, the processing meanss include：

1）Acquiring unit 602, for according to the first data signal, the second data signal, the 3rd data signal and the 4th number According to the 5th data signal of signal acquisition and the 6th data signal, wherein, the first data signal, the second data signal, the 3rd data Signal and the 4th data signal are corresponding with the first clock signal, the 5th data signal and the 6th data signal and second clock signal Corresponding, and second clock signal is double frequency multiplied clock signals of the first clock signal, wherein, when second clock signal is 1, the Corresponding first data signal of five data signals, corresponding 3rd data signal of the 6th data signal, when second clock signal is 0, Corresponding second data signal of 5th data signal, corresponding 4th data signal of the 6th data signal；

2）Select unit 604, for obtaining the 3rd clock signal, and in second clock signal relative to the 3rd clock signal Phase contrast when being located at the first pre-set interval, gather the 5th data signal and the 6th data using the rising edge of the 3rd clock signal Signal, when phase contrast is located at the second pre-set interval, gathers the 5th data signal and the using the trailing edge of the 3rd clock signal Six data signals, wherein, the clock cycle of the 3rd clock signal is identical with the clock cycle of second clock signal；

3）Processing unit 606, for according to the 7th data signal obtained by the 5th data signal of collection and collection the The 8th data signal obtained by six data signals obtains the 9th data signal, wherein, when the 3rd clock signal is 1, the 9th Corresponding 7th data signal of data signal, when the 3rd clock signal is 0, corresponding 8th data signal of the 9th data signal.

It will be clear that one of technical solution of the present invention technical problem to be solved be to provide a kind of to data signal The device for being processed, to realize that the frequency multiplication cross clock domain to the data entrained by 4 circuit-switched data signals is transmitted, of the invention real Apply in example, the 4 circuit-switched data signal can be expressed as the first data signal, the second data signal, the 3rd data signal and Four data signals, the output data as result can carry the data entrained by first to fourth data signal 9th data signal, wherein, first to fourth data signal is corresponding with the first clock signal, the 9th data signal and the 3rd clock Double frequency multiplied clock signals of signal are corresponding, and the clock cycle of the first clock signal is the two of the clock cycle of the 3rd clock signal Times.

The processing meanss of the data signal for providing according to embodiments of the present invention, in acquiring unit 602, can first to the One to the 4th data signal is processed, to obtain the 5th data signal and the 6th data signal, wherein, the 5th data signal and 6th data signal can be corresponding with the second clock signal of the double frequency-doubled signals as the first clock signal, and the 5th data letter The first data signal and the data entrained by the second data signal number can be carried, and the 6th data signal can carry Data entrained by three data signals and the 4th data signal.Easy to understand, under above-mentioned scene, it is also possible to by acquiring unit 602 are considered as the 5th data signal that the first data signal and the second data signal are merged into double frequency, and by the 3rd data Signal and the 4th data signal merge into the 6th data signal of double frequency.

In embodiments of the present invention, the concrete implementation mode of acquiring unit 602 can have multiple, for example, as wherein A kind of optional mode, acquiring unit 602 can include：

1）First acquisition module, for the trailing edge using first clock signal gather first data signal and 3rd data signal, gathers second data signal and the 4th number using the rising edge of first clock signal It is believed that number；Or, first data signal and the 3rd data letter is gathered using the rising edge of first clock signal Number, second data signal and the 4th data signal is gathered using the trailing edge of first clock signal；

2）First processing module, for when first clock signal is 1, gathering the first data signal gained The data signal for arriving will gather data signal obtained by the 3rd data signal as institute as the 5th data signal The 6th data signal is stated, when first clock signal is 0, by the data signal obtained by described for collection the second data signal As the 5th data signal, the data signal obtained by described for collection the 4th data signal is believed as the 6th data Number.

On the basis of above description, the processing meanss of the data signal for providing according to embodiments of the present invention are selecting list In unit 604, can further realize the 5th data signal and the 6th data signal from the clock zone of second clock signal to the The cross clock domain transmission of the clock zone of three clock signals, in order to obtain after being transmitted according to cross clock domain in processing unit 606 The 7th data signal and the 8th data signal obtain corresponding with double frequency-doubled signals of the 3rd clock signal the 9th data signal Process operation.

Above description is based on, present invention problem to be solved in select unit 604 can also be expressed as：Will be with second When corresponding 5th data signal of clock signal and the 6th data signal are respectively converted into the corresponding with the 3rd clock signal the 7th Clock signal and the 8th clock signal, wherein, the 5th data signal is identical with the content of the 7th data signal, but sequential have different, Similarly, the 6th data signal is identical with the content of the 8th data signal, however sequential have different.As the 5th data signal is to The cross clock domain transmission of seven data signals is similar to the cross clock domain transmission of the 8th data signal with the 6th data signal, below will The scheme of the embodiment of the present invention is described to the cross clock domain transmission of the 7th data signal mainly around the 5th data signal.

For solving this problem, in embodiments of the present invention, the 5th data can be gathered along holding using the 3rd clock signal Signal is in the way of generating the 7th data signal, and obtains the 5th data signal and the 3rd clock in acquiring unit 602 Signal, but prior art is different from, the processing meanss for providing according to embodiments of the present invention, in select unit 604, can be with root Still declined using the rising edge of the 3rd clock signal according to the phase relation between second clock signal and the 3rd clock signal Selected between, wherein, if second clock signal is located at the first pre-set interval relative to the phase contrast of the 3rd clock signal, The rising edge of the 3rd clock signal can be then used to gather the 5th data signal, if phase contrast is located at the second pre-set interval, can 5th data signal is gathered with the trailing edge using the 3rd clock signal.In other words, in embodiments of the present invention, and non-static Ground gathers the 5th data signal using the rising edge or trailing edge of the 3rd clock signal, but can be directed to not with relative dynamic With situation select one of rising edge and trailing edge to be acquired, so as to realize to data signal across the transmission road of clock transfer The control of the timing margins on footpath, and then reach the requirement to the timing margins.

As shown in figure 4, under a scene of the embodiment of the present invention, when second clock signal can be as shown in the 1st row Clock signal, the 5th data signal can be the data signal as shown in the 2nd row, and the 3rd clock signal can be as shown in the 3rd row Clock signal.Under above-mentioned scene, second clock signal is all more than half clock relative to the phase contrast of the 3rd clock signal Phase, namely it is located at the first pre-set interval（T/2, T）Interior, so as to according to select unit 604, select using the 3rd clock signal Rising edge gather the 5th data signal, and obtain the data signal as shown in the 4th row as the 7th data signal.Easily see Go out, under above-mentioned scene, the 5th data signal is corresponding with second clock signal, the 7th data signal and the 3rd clock signal pair Should, and the data content of the 7th data signal is consistent with the 5th data signal, namely achieve the 5th data signal across clock Domain is transmitted, and on the other hand, the timing margins in the transmission path of the cross clock domain transmission are equal to above-mentioned phase contrast, and above-mentioned phase Potential difference is located in the first pre-set interval, is more than half clock cycle, and therefore the timing margins are more than half clock cycle, that is, In embodiments of the present invention, the control of timing margins partly can be realized by the first pre-set interval, such that it is able to pass through To the reasonable setting of the first pre-set interval to meet the requirement to the timing margins, so reach gathered data exactly and Improve the effect of the reliability of the cross clock domain transmission of data signal.

As shown in figure 5, under another scene of the embodiment of the present invention, second clock signal can be as shown in the 1st row Clock signal, the 5th data signal can be the data signal as shown in the 2nd row, and the 3rd clock signal can be such as the 3rd row institute The clock signal that shows.Under above-mentioned scene, second clock signal is less than half clock relative to the phase contrast of the 3rd clock signal Cycle, namely it is located at the second pre-set interval（0, T/2）Interior, so as to according to select unit 604, select to believe using the 3rd clock Number trailing edge gather the 5th data signal, and obtain the data signal as shown in the 5th row as the 7th data signal.Easily see Go out, under above-mentioned scene, on the basis of the cross clock domain for realizing the 5th data signal is transmitted, the transmission of the cross clock domain transmission Timing margins on path are equal to above-mentioned phase contrast and add half clock cycle, and above-mentioned phase contrast is located at the second pre-set interval Interior, be less than half clock cycle, therefore the timing margins are more than half clock cycle, that is, in embodiments of the present invention, pair when The control of sequence nargin partly can be realized by the second pre-set interval, such that it is able to by rationally setting to the second pre-set interval Put to meet the requirement to the timing margins, and then reach gathered data exactly and improve the cross clock domain of data signal The effect of the reliability of transmission.

On the basis of above description, the processing meanss of the data signal for providing according to embodiments of the present invention are single processing In unit 606, the 9th data signal can be obtained according to the 7th data signal and the 8th data signal, wherein, in present invention enforcement In example, the process of frequency multiplication side similar with the implementation of aforesaid acquiring unit 602 can have both been taken in the realization of processing unit 606 Formula, it is also possible to according to specific design needs, before the 9th data signal is obtained, to the 7th data signal and the 8th data signal Carry out other process feasible, for example postpone, anti-phase, again collection, deposit one clap or clap etc., and according to obtaining after process Data signal generates the 9th data signal, it should be understood that, in above-mentioned processing procedure, all should work as and belong at the 3rd Process in the clock zone of clock signal, that is, the 9th data signal for being obtained still should be corresponding with the 3rd clock signal.

For example, alternatively, in embodiments of the present invention, processing unit 606 can include：

1）Second acquisition module, for executing the operation of below n times：Rising edge or trailing edge pair using the 3rd clock signal The data signal collected by front once-through operation in n times operation is gathered again, wherein, the front once-through operation of n times operation In the initial value of data signal that collects be the 7th data signal, N is more than or equal to 1；And/or, execute M following operation：Make The data signal collected by the front once-through operation in M operation is carried out again with the rising edge or trailing edge of the 3rd clock signal Secondary collection, wherein, the initial value of data signal that the front once-through operation in M operation is collected is the 8th data signal, and M is big In equal to 1；

2）Second processing module, for when the 3rd clock signal is 1, will adopt after the 7th data signal or n times operation The data signal that collection is obtained, when the first clock signal is 0 the 8th data signal or M time is grasped as the 9th data signal The data signal collected after work is used as the 9th data signal.

Under above-mentioned scene, can adopted by 604 pairs of the 5th data signals of select unit and the 6th data signal After collection, the 5th data signal and/or the 6th data signal are gathered again in the second acquisition module, and " should be adopted again The operation of collection " can repeat n times and M time respectively, and N, M are more than or equal to 1, wherein it is desired to illustrate, in present invention enforcement In example, above-mentioned n times are not necessarily limited to be " using the rising edge of the 3rd clock signal " or " using the 3rd clock signal Trailing edge ", for example, in one embodiment, certain once-through operation in n times operation can be gathered using rising edge, the operation Next operation can be gathered using trailing edge, and similarly, above-mentioned M operation is also not limited to be using rising edge or decline Edge, the present invention are not construed as limiting to this.

It should be appreciated that in embodiments of the present invention, the n times for being carried out using the hopping edge of the 3rd clock signal respectively and M time Data signal obtained by acquisition operations will be in the clock zone of the 3rd clock signal again, the 9th data for obtaining accordingly Signal is also by the clock zone of the 3rd clock signal.Generally, for include described in select unit 604 to the 5th The acquisition operations of data signal and the 6th data signal have used the upper of the 3rd clock signal in interior above-mentioned " front once collection " The situation on edge is risen, for the collection again carried out after the front once collection, if still using the rising edge of the 3rd clock signal, Then equivalent to the front data signal for once collecting being delayed a clock cycle or saying one bat of deposit, if being changed to make With the trailing edge of the 3rd clock signal, then equivalent to by the front data signal for once collecting delay half clock cycle, Deposit in other words half is clapped, accordingly, for front once collection has used the situation of the trailing edge of the 3rd clock signal, it is also possible to To similar effect.Wherein, either deposit half is clapped, one claps or the situation that claps more, and the timing margins in gathering again are at least There is half clock cycle, accuracy caused by the timing margins due to data signal on the transmit path therefore can be avoided not enough Problem with reliability decrease.

Further, for ease of Second processing module in the 9th data signal acquisition, the invention provides following two Above-mentioned n times operates kind optional specific embodiment and M operation is defined, with realization in the second acquisition module to the Seven data signals and/or the pretreatment of the 8th data signal：

1）If above-mentioned phase contrast is located at the first pre-set interval, the n times operation in the second acquisition module can be：Using The trailing edge of three clock signals is gathered again to the 7th data signal, and M operation can be：Using the 3rd clock signal Rising edge is gathered again to the 8th data signal；

If above-mentioned phase contrast is located at the second pre-set interval, M operation in the second acquisition module can be：Using the 3rd The rising edge of clock signal is gathered again to the 8th data signal.

2）If above-mentioned phase contrast is located at the first pre-set interval, M operation in the second acquisition module can be：Using The trailing edge of three clock signals is gathered again to the 8th data signal；

If above-mentioned phase contrast is located at the second pre-set interval, the n times operation in the second acquisition module can be：Using the 3rd The rising edge of clock signal is gathered again to the 7th data signal, and M operation can be：Under using the 3rd clock signal Drop edge is gathered again to the 8th data signal.

Under this scene, in conjunction with the processing meanss of data signal provided in an embodiment of the present invention, it is possible to achieve to be transmitted Effective transmission of the data from Memory Controller Hub to memory chip, wherein, the data to be transmitted can be obtained by Memory Controller Hub Or the data signal corresponding with system clock for generating, and writing data and can be and write obtained by above-mentioned process operation The corresponding data signal of data clock, receives and recognizes to writing data in order to internal memory.Wherein, also may be used although writing data clock To be obtained or generated by Memory Controller Hub, however this write should meet between data clock and internal memory clock default sequential will Ask.The adjustment operation for writing data clock will be given in subsequent embodiment.

Still optionally further, in embodiments of the present invention, before acquiring unit 602, above-mentioned processing meanss can also be wrapped Include：

1）Adjustment unit, for meet corresponding with default timing requirements termination execution condition before, repeat P time with Lower operation：Adjustment writes data clock or relative to the 4th clock for writing the data clock delayed K clock cycle forward or backward Signal, and to memory chip transmission and corresponding tenth number of the 4th clock signal after writing data clock or adjusting after adjustment It is believed that number；The 11st data signal that memory chip is returned is received according to the tenth data signal, and according to the 11st number for receiving It is believed that number judge whether to meet terminating execution condition；Wherein, P is more than or equal to 1.

A circulation formed in adjustment unit may be summarized to be：The process of adjustment conveying feedback, its In, to memory chip according to the 11st data signal fed back by the tenth data signal conveyed to which can generally carry with " whether meeting termination execution condition " " writes " phase in other words Corresponding information, therefore judges to may determine that whether circulation terminates by the identification to the 11st data signal, it is possible to Write data clock or according to determined by the 4th clock signal that obtains after P time operates obtained by after above-mentioned P time is operated The 3rd clock signal determined before data clock is transmitted is write as the cross clock domain for carrying out data signal, with alternatively unit The basis of selection is carried out in 604 according to phase contrast.It should be noted that above-mentioned circulation can also have other equivalent variations, example Such as, a similar circulation can also be summarised as：The process that conveying feedback is adjusted according to feedback, the present invention are right The single operation division of one cycle in other words of P operation is simultaneously not construed as limiting, based on each specific embodiment described above It is regarded as within protection scope of the present invention.

Further, in embodiments of the present invention, due to believing to writing data clock and/or the 4th clock in adjustment unit Number adjustment can reflect the phase shift for writing data clock as the 3rd clock signal, therefore can also be grasped according to above-mentioned P time Make completed adjustment to draw the second clock signal of alternatively foundation in select unit 604 and the phase of the 3rd clock signal Potential difference.Wherein, alternatively,

Above-mentioned processing meanss can also include：Initialization unit, for clock signal that will align with system clock as Write the initial value of data clock or the 4th clock signal；Wherein,

Adjustment unit can include：Postponement module, for postponing to write data clock or the 4th clock signal 1/L clock Cycle, as adjustment after write data clock or the 4th clock signal, L is positive integer；Wherein,

The processing meanss can further include：Computing module, in the clock signal that will be alignd with system clock During as writing data clock, phase contrast is obtained according to following formula：Δ=（P/L）*T；Make in the clock signal that will be alignd with system clock For four clock signals when, according to following formula obtain phase contrast：Δ=（P/L-K）*T；Wherein, Δ represents that phase contrast, T represent clock Cycle.

Under above-mentioned scene, the value of L is bigger, then to writing the adjustment of data clock or the 4th clock signal in single operation Amount is less, and the calibration for writing data clock or the 4th clock signal to this is then about accurate, writes between data clock and internal memory clock Sequential then more for being close to default timing requirements, on the other hand, the phase difference that draws accordingly be also more accurate so that The processing meanss of above-mentioned data signal are more also accurate to the control of the timing margins in the transmission path of its cross clock domain transmission.

Embodiment 3

According to embodiments of the present invention, a kind of processing meanss of the data signal that realizes by hardware logic are additionally provided, such as Shown in Fig. 7, the device can include：

1）Depositor REG1, REG2, REG3, REG4, REG5, REG6, REG7, REG8 and REG9；

2）Selector MUX1, MUX2, MUX3, MUX4 and MUX5；

Wherein, the annexation between each device may be referred to Fig. 7, and here is not repeated one by one.

As shown in fig. 7, the clock input of REG1 and REG3 may each be the anti-phase of clock signal clk1, REG2 and REG4 Clock input can be clk1, and wherein, clk1 can be used as the first clock signal as described in example 2 above.The number of REG1 Can be data signal dq1 according to input, the data input of REG2 can be data signal dq2, can be real by selector MUX1 The now merging to dq1 and dq2, so that obtain data signal dq5 all the way of the data for carrying dq1 and dq2, wherein, the biography of dq5 Defeated speed is the twice of dq1 and dq2.Similarly, the data input of REG3 can be data signal dq3, the data input of REG4 Can be data signal dq4, the merging to dq3 and dq4 can be realized by selector MUX2, so as to obtain carry dq3 and Data signal dq6 all the way of the data of dq4, wherein, the transfer rate of dq6 is the twice of dq3 and dq4.Specifically, in the present invention In embodiment, dq1 to dq6 can correspond respectively to the first to the 6th data signal described in embodiment 2, and wherein, dq1 is extremely Dq4 is corresponding to clk1, dq5 and dq6 corresponding to the clk2 as second clock signal as described in example 2 above.

Can be realized to four ways with the first clock signal synchronization by REG1 to REG4 and MUX1 and MUX2 it is believed that Number and synchronous with the second clock signal two paths of data signal acquisition, in other words, embodiments provide strictly according to the facts A kind of feasible hardware implementation mode of the acquiring unit described in example 2 is applied, and needed for select unit as described in example 2 above The acquisition to the 3rd clock signal for executing, can realize simply by terminals, such as in Fig. 7, left side is identified with The terminals of clk3, for the input of clock signal clk3, wherein, clk3 can as described in example 2 above the 3rd when Clock signal.

Further, in embodiments of the present invention, the selectivity collection for executing needed for select unit as described in Example 2 Operation can pass through REG5, REG6, REG7 and REG8 and selector MUX3 and MUX4 are realized.

As shown in fig. 7, the clock input of REG5, REG6, REG7 and REG8 can be clock signal clk3.REG5 and It can be dq6 that the data input of REG8 can be the data input of dq5, REG6 and REG7, so as to REG5, REG6, REG7 and REG8 can play data signal dq5 of the collection in the clock zone of clk2 or dq6 to obtain the clock zone positioned at clk3 The effect of interior data signal, namely achieve the cross clock domain transmission of data signal.

Specifically, as shown in fig. 7, the clock input of REG5 and REG6 is directly clk3, namely the rising edge using clk3 It is acquired, the clock input of REG7 and REG8 is each via a phase inverter input clk3, namely the trailing edge using clk3 It is acquired, is acquired as which in the rising edge or trailing edge of specifically used clk3, selector can be passed through MUX3 and MUX4 completing, wherein, the low level input of MUX3 and MUX4 can correspondingly using the acquisition mode of clk3 rising edges, High level input can correspondingly using clk3 trailing edges acquisition mode, control input can be used for be input into corresponding to clk2 with The signal of telecommunication pm of the phase contrast between clk3, wherein, the phase contrast is located at as the first pre-set interval as described in example 2 above 's（T/2, T）When, pm can be low level, and then can gather data letter corresponding with clk2 using the rising edge of clk3 Number, the phase contrast is located at as the second pre-set interval as described in example 2 above（0, T/2）When, pm can be high level, enter And data signal corresponding with clk2 can be gathered using the trailing edge of clk3.

By above-mentioned selective acquisition mode, it can be ensured that data signal dq1 to dq4 is in cross clock domain transmission path Timing margins, and then improve the accuracy of data transfer, here of the present invention is not repeated.

Further, as shown in fig. 7, data signal in the clock zone for being pointed to clk2 by REG5, REG6 or REG7 After being acquired, the data signal obtained by collection can also be gathered again, wherein, when above-mentioned phase contrast is located at the During one pre-set interval, pm is low level, can pass through REG8, using clk3 trailing edge to by REG5 collection dq5 obtained by Data signal gathered again, to obtain the dq7 of the 7th data signal as described in example 2 above, and by REG9, make Gathered to gathering the data signal obtained by dq6 by REG6 again with the rising edge of clk3, to obtain as in embodiment 2 The 8th described data signal dq8.Certainly, for processing unit as described in example 2 above, which directly can also export The data signal that clk3 is collected first, such as, shown in Fig. 7, when above-mentioned phase contrast is located at the second pre-set interval, pm is height Level, dq5 are directly obtained second as described in example 2 above after REG8, the once collection via the trailing edge of clk3 The 7th data signal dq7 in data signal, the present invention are not construed as limiting to this.Specifically, in embodiments of the present invention, Dq7 and dq8 can correspond respectively to the 7th data signal and the 8th data signal described in embodiment 2, wherein, dq7 and dq8 Correspond to clk3.

By circuit as shown in Figure 7, the present invention in fact gives the second acquisition module as described in example 2 above Hardware implementation mode.Wherein, as a kind of optimization design, in embodiments of the present invention, REG8 is used separately as in different situations Select unit as described in Example 2 and a part for processing unit, so as to save at least one depositor, in reduce loss While improve the processing speed of processing meanss, it is notable that such equivalent or modification to the embodiment of the present invention is equal Should be regarded as within protection scope of the present invention.

Consider DDR double-speed transmission requirement, can also further by dq7 in other words dq1 and dq2 and dq8 or Person says that the data represented by dq3 and dq4 are combined, and is output as data signal dq9 all the way, specifically, as shown in fig. 7, can To realize merging to dq7 and dq8 by selector MUX5, wherein, the high level input of MUX5 can be REG8 data defeated Go out, the input of the low level of MUX5 can be the data output of REG9, and control input can be clk3, so as to being high level in clk3 When, processing meanss can export dq7 to MUX5 in other words, and when clk3 is low level, processing meanss can be exported MUX5 in other words Dq8, this just meets requirements of the DDR to data transfer, and gives a kind of feasible of processing unit as described in example 2 above Hardware implementation mode, here of the present invention do not make tired stating.

Further, in embodiments of the present invention, processing meanss as shown in Figure 7 can be used as the physics of Memory Controller Hub A part for PHY modules, due to the processing meanss simple structure and time delay is less, therefore relative to existing or by soft Part logic realization with the Memory Controller Hub of identical function is realized for, using the interior of the PHY modules for including the processing meanss The processing speed of memory controller will be obviously improved.Specifically, clk1 can be the system clock of Memory Controller Hub, Clk3 can be internal memory clock, and dq1 to dq4 could be for four circuit-switched datas that transmits, and dq9 can be into internal memory transmission Deposit and write data, wherein, this is write data and is combined by the data content of dq1 to dq4, its message transmission rate is system clock frequency Four times of rate, and by processing meanss provided in an embodiment of the present invention, it can be ensured that the sequential in cross clock domain transmission path is abundant Degree is more than or equal to half clock cycle, and then improves the accuracy of data transfer.

It should be noted that above-described embodiment is only used for the understanding to technical solution of the present invention, and it is not construed as to this Bright constitute any unnecessary restriction, for example, in processing meanss as shown in Figure 7, can also add on the transmit path More depositors carry out a bat or the purpose for clapping deposit to reach more to data signal, and similar embodiment has no effect on this The enforcement of inventive technique scheme and its realization of technique effect, the present invention are not also limited in any way to this.It should be appreciated that class As extension and the extension of the present invention are regarded as within protection scope of the present invention.

As can be seen from the above description, present invention achieves following technique effect：

1）Employ according to the phase contrast between second clock signal and the 3rd clock signal using the 3rd clock signal Rising edge or trailing edge pair the 5th data signal corresponding with second clock signal and the 6th data signal are acquired it Between carry out the mode of selection, with obtain corresponding with the 3rd clock signal, relative to the 3rd clock signal with Double Data Rate transmission and Meet the 9th data signal of the requirement that timing margins on the transmit path are transmitted to cross clock domain, it is achieved thereby that to data The control of timing margins of the signal in the transmission path that cross clock domain is transmitted；

2）By the reasonable setting to the first pre-set interval and the second pre-set interval can meet to data signal across when The design requirement of clock domain transmission, and improve the reliability of the cross clock domain transmission of data signal.

The preferred embodiments of the present invention are the foregoing is only, the present invention is not limited to, for the skill of this area For art personnel, the present invention can have various modifications and variations.All within the spirit and principles in the present invention, made any repair Change, equivalent, improvement etc., should be included within the scope of the present invention.

Claims

1. a kind of processing method of data signal, it is characterised in that include：

5th data signal is obtained according to the first data signal, the second data signal, the 3rd data signal and the 4th data signal With the 6th data signal, wherein, first data signal, second data signal, the 3rd data signal and described 4th data signal is corresponding with the first clock signal, and the 5th data signal and the 6th data signal are believed with second clock Number corresponding, the second clock signal is double frequency multiplied clock signals of first clock signal, and first clock signal Rising edge and the second clock signal rising edge alignment, wherein, when first clock signal is 1, the described 5th Corresponding first data signal of data signal, corresponding 3rd data signal of the 6th data signal, described first When clock signal is 0, corresponding second data signal of the 5th data signal, the 6th data signal corresponding described the Four data signals；

Obtain the 3rd clock signal, and the is located in the second clock signal relative to the phase contrast of the 3rd clock signal During one pre-set interval, the 5th data signal and the 6th data letter is gathered using the rising edge of the 3rd clock signal Number, when the phase contrast is located at the second pre-set interval, using the trailing edge collection of the 3rd clock signal the 5th number It is believed that number and the 6th data signal, wherein, the clock cycle of the 3rd clock signal and the second clock signal Clock cycle is identical；

According to the 7th data signal obtained by collection the 5th data signal and collection the 6th data signal gained The 8th data signal for arriving obtains the 9th data signal, wherein, when the 3rd clock signal is 1, the 9th data letter Number corresponding 7th data signal, when the 3rd clock signal is 0, corresponding 8th number of the 9th data signal It is believed that number,

Wherein, first pre-set interval is (T/2, T), and second pre-set interval is (0, T/2), when T represents described second The clock cycle of clock signal.

2. processing method according to claim 1, it is characterised in that described believed according to the first data signal, the second data Number, the 3rd data signal and the 4th data signal obtain the 5th data signal and the 6th data signal includes：

First data signal and the 3rd data signal are gathered using the trailing edge of first clock signal, using institute The rising edge for stating the first clock signal gathers second data signal and the 4th data signal；Or, using described The rising edge of one clock signal gathers first data signal and the 3rd data signal, using first clock signal Trailing edge gather second data signal and the 4th data signal；

When first clock signal is 1, data signal obtained by first data signal will be gathered as described the Five data signals, using the data signal obtained by described for collection the 3rd data signal as the 6th data signal, described When first clock signal is 0, using the data signal obtained by described for collection the second data signal as the 5th data signal, Using the data signal obtained by described for collection the 4th data signal as the 6th data signal.

3. processing method according to claim 1, it is characterised in that described according to gathering the 5th data signal gained The 8th data signal obtained by the 7th data signal for arriving and collection the 6th data signal obtains the 9th data signal Including：

Execute below n times to operate：Previous in being operated to the n times using the rising edge or trailing edge of the 3rd clock signal The collected data signal of secondary operation is gathered again, wherein, the number that collects in the front once-through operation of the n times operation It is believed that number initial value be the 7th data signal, N be more than or equal to 1；And/or, execute M following operation：Using described The rising edge or trailing edge of three clock signals is carried out again to the data signal collected by the front once-through operation in described M time operation Secondary collection, wherein, the initial value of the data signal collected by the front once-through operation in the M operation is the 8th data Signal, M are more than or equal to 1；

When the 3rd clock signal is 1, will the data that collect after the 7th data signal or n times operation Signal as the 9th data signal, when first clock signal is 0, by the 8th data signal or the M The data signal collected after secondary operation is used as the 9th data signal.

4. processing method according to claim 3, it is characterised in that

If the phase contrast is located at first pre-set interval, the n times operation includes：Using the 3rd clock signal Trailing edge is gathered again to the 7th data signal, and the M operation includes：Using the upper of the 3rd clock signal Rise edge to gather the 8th data signal again；If the phase contrast is located at second pre-set interval, described M time Operation includes：The 8th data signal is gathered again using the rising edge of the 3rd clock signal；Or,

If the phase contrast is located at first pre-set interval, the M operation includes：Using the 3rd clock signal Trailing edge is gathered again to the 8th data signal；If the phase contrast is located at second pre-set interval, the N Secondary operation includes：The 7th data signal is gathered again using the rising edge of the 3rd clock signal, described M time Operation includes：The 8th data signal is gathered again using the trailing edge of the 3rd clock signal.

5. method according to any one of claim 1 to 4, it is characterised in that first clock signal is internal memory control The system clock of device processed, the second clock signal is double frequency doubling clocks of the system clock, and the 3rd clock signal is The Memory Controller Hub writes data clock, first data signal, second data signal, the 3rd data signal With the data to be transmitted that the 4th data signal is the Memory Controller Hub, the 9th data signal is the Memory control Device writes data to what memory chip was transmitted, and wherein, write data clock is all with the clock of the internal memory clock of the memory chip Phase is identical, and meets default timing requirements between write data clock and the internal memory clock.

6. method according to claim 5, it is characterised in that the default timing requirements are according to write data clock The write data of generation shift to an earlier date K clock cycle when the memory chip is reached relative to the internal memory clock, and K is 0 to 1 Between arbitrary value, wherein, described acquisition the 3rd clock signal before, methods described also includes：

Meet corresponding with the default timing requirements terminate execution condition before, repeat P following operation：Forward or to Write data clock or fourth clock signal relative to write data clock delayed K clock cycle are adjusted afterwards, and Corresponding with the write data clock after adjustment or the 4th clock signal after adjustment to memory chip transmission Tenth data signal；Receive the 11st data signal that the memory chip is returned according to the tenth data signal, and according to The 11st data signal for receiving judges whether to meet the termination execution condition；Wherein, P is more than or equal to 1.

7. method according to claim 6, it is characterised in that the tenth data signal is and the 4th clock signal Rising edge or trailing edge alignment pulse signal, the 11st data signal believed using the pulse for the memory chip Data signal obtained by number collection internal memory clock, wherein, if the tenth data signal and the 4th clock signal Rising edge alignment, then described termination execution condition be：The 11st data signal for receiving is changed into 1 from 0；

If the tenth data signal is alignd with the trailing edge of the 4th clock signal, the termination execution condition is：Connect The 11st data signal that receives is changed into 0 from 1.

8. method according to claim 6, it is characterised in that

Before the P operation is executed, methods described also includes：Using the clock signal that aligns with the system clock as described Write the initial value of data clock or the 4th clock signal；

When the P operation is executed, adjustment write data clock and/or the 4th clock signal forward or backward Including：Postpone write data clock or the 4th clock signal 1/L clock cycle, as number being write described in after adjustment According to clock or the 4th clock signal, L is positive integer；

After the P operation is executed, methods described also includes：If using the clock signal that aligns with the system clock as institute State and write data clock, then the phase contrast is obtained according to following formula：Δ=(P/L) * T；If by align with the system clock when Clock signal then obtains the phase contrast according to following formula as the 4th clock signal：Δ=(P/L-K) * T；Wherein, Δ is represented The phase contrast, T represent the clock cycle.

9. a kind of processing meanss of data signal, it is characterised in that include：

Acquiring unit, for obtaining according to the first data signal, the second data signal, the 3rd data signal and the 4th data signal 5th data signal and the 6th data signal, wherein, first data signal, second data signal, the 3rd number It is believed that number and the 4th data signal corresponding with the first clock signal, the 5th data signal and the 6th data signal Corresponding with second clock signal, the second clock signal is double frequency multiplied clock signals of first clock signal, and described The rising edge alignment of the rising edge of the first clock signal and the second clock signal, wherein, is 1 in first clock signal When, corresponding first data signal of the 5th data signal, corresponding 3rd data signal of the 6th data signal, When first clock signal is 0, corresponding second data signal of the 5th data signal, the 6th data signal Corresponding 4th data signal；

Select unit, for obtaining the 3rd clock signal, and in the second clock signal relative to the 3rd clock signal Phase contrast when being located at the first pre-set interval, using the rising edge of the 3rd clock signal gather the 5th data signal and 6th data signal, when the phase contrast is located at the second pre-set interval, using the trailing edge of the 3rd clock signal Gather the 5th data signal and the 6th data signal, wherein, the clock cycle of the 3rd clock signal with described The clock cycle of second clock signal is identical；

Processing unit, for according to the 7th data signal obtained by collection the 5th data signal and collection the described 6th The 8th data signal obtained by data signal obtains the 9th data signal, wherein, when the 3rd clock signal is 1, institute State corresponding 7th data signal of the 9th data signal, when the 3rd clock signal is 0, the 9th data signal pair The 8th data signal is answered,

10. processing meanss according to claim 9, it is characterised in that the acquiring unit includes：

First acquisition module, gathers first data signal and described for the trailing edge using first clock signal Three data signals, gather second data signal and the 4th data letter using the rising edge of first clock signal Number；Or, first data signal and the 3rd data signal is gathered using the rising edge of first clock signal, make Second data signal and the 4th data signal are gathered with the trailing edge of first clock signal；

First processing module, for when first clock signal is 1, by the number obtained by described for collection the first data signal It is believed that number as the 5th data signal, data signal obtained by the 3rd data signal will be gathered as the described 6th Data signal, when first clock signal is 0, using the data signal obtained by described for collection the second data signal as institute The 5th data signal is stated, using the data signal obtained by described for collection the 4th data signal as the 6th data signal.

11. processing meanss according to claim 9, it is characterised in that the processing unit includes：

Second acquisition module, for executing the operation of below n times：Rising edge or trailing edge using the 3rd clock signal is to institute The data signal that collected of front once-through operation that states in n times operation is gathered again, wherein, the n times operation previous The initial value of the data signal collected in secondary operation is the 7th data signal, and N is more than or equal to 1；And/or, execute M time with Lower operation：The front once-through operation in described M time operation is gathered using the rising edge or trailing edge of the 3rd clock signal To data signal gathered again, wherein, the data signal that collected of front once-through operation in the M operation just Initial value is the 8th data signal, and M is more than or equal to 1；

Second processing module, for when the 3rd clock signal is 1, the 7th data signal or the n times being grasped The data signal collected after work as the 9th data signal, when first clock signal is 0, by the described 8th The data signal collected after data signal or the M operation is used as the 9th data signal.

12. processing meanss according to claim 11, it is characterised in that

If the phase contrast is located at first pre-set interval, the n times operation includes：Using the 3rd clock signal Trailing edge is gathered again to the 7th data signal, and the M operation includes：Using the upper of the 3rd clock signal Rise edge to gather the 8th data signal again；If the phase contrast is located at second pre-set interval, described M time Operation includes：The 8th data signal is gathered again using the rising edge of the 3rd clock signal；Or, if institute Phase contrast is stated positioned at first pre-set interval, then the M operation includes：Trailing edge pair using the 3rd clock signal 8th data signal is gathered again；If the phase contrast is located at second pre-set interval, the n times operation bag Include：The 7th data signal is gathered again using the rising edge of the 3rd clock signal, the M operation bag Include：The 8th data signal is gathered again using the trailing edge of the 3rd clock signal.

13. devices according to any one of claim 9 to 12, it is characterised in that first clock signal is interior

The system clock of memory controller, the second clock signal are double frequency doubling clocks of the system clock, when the described 3rd Clock signal is that the Memory Controller Hub writes data clock, first data signal, second data signal, the described 3rd Data signal and the data to be transmitted that the 4th data signal is the Memory Controller Hub, the 9th data signal are described Memory Controller Hub writes data to what memory chip was transmitted, wherein, the internal memory clock of write data clock and the memory chip Clock cycle identical, and between write data clock and the internal memory clock, meet default timing requirements.

14. devices according to claim 13, it is characterised in that when the default timing requirements are according to write data The write data that clock is generated shift to an earlier date K clock cycle when the memory chip is reached relative to the internal memory clock, and K is 0 Arbitrary value between 1, wherein, before the 3rd clock signal of the acquisition, described device also includes：

Adjustment unit, for meet corresponding with the default timing requirements terminate execution condition before, repeat P time below Operation：Adjustment write data clock or relative to the write data clock delayed K clock cycle the forward or backward Four clock signals, and during to the write data clock after memory chip transmission and adjustment or the described 4th after adjustment Corresponding tenth data signal of clock signal；The 11st data that the memory chip is returned are received according to the tenth data signal Signal, and judge whether to meet the termination execution condition according to the 11st data signal for receiving；Wherein, P more than etc. In 1.

15. devices according to claim 14, it is characterised in that the tenth data signal is to believe with the 4th clock Number rising edge or trailing edge alignment pulse signal, the 11st data signal be the memory chip use the pulse Data signal obtained by internal memory clock described in signals collecting, wherein, if the tenth data signal is believed with the 4th clock Number rising edge alignment, then described termination execution condition be：The 11st data signal for receiving is changed into 1 from 0；

16. devices according to claim 14, it is characterised in that

Described device also includes：Initialization unit, for writing number using the clock signal that aligns with the system clock as described According to clock or the initial value of the 4th clock signal；

The adjustment unit includes：Postponement module, for postponing write data clock or the 4th clock signal 1/L Clock cycle, as adjustment after write data clock or the 4th clock signal, L is positive integer；

Described device also includes：Computing module, for writing number using the clock signal that aligns with the system clock as described During according to clock, the phase contrast is obtained according to following formula：Δ=(P/L) * T；In the clock signal that will be alignd with the system clock During as four clock signal, the phase contrast is obtained according to following formula：Δ=(P/L-K) * T；Wherein, Δ represents the phase Potential difference, T represent the clock cycle.