CN103646225B - Method and circuit for ultrahigh frequency radio frequency identification tag reverse communication speed - Google Patents
Method and circuit for ultrahigh frequency radio frequency identification tag reverse communication speed Download PDFInfo
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- CN103646225B CN103646225B CN201310637156.6A CN201310637156A CN103646225B CN 103646225 B CN103646225 B CN 103646225B CN 201310637156 A CN201310637156 A CN 201310637156A CN 103646225 B CN103646225 B CN 103646225B
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Abstract
The invention is a method used for realizing reverse communication speed of an ultrahigh frequency passive radio frequency identification (RFID) national standard. According to the regulations in an ultrahigh frequency national standard "information technology RFID 800/900 MHz air interface protocol ", the tag-to-reader-writer reverse communication speed is determined by query command (Query) parameters sent by a reader. The invention provides the corresponding realization method on the basis of analyzing the return communication speed and frequency point tolerance in details and combining the RFID 800/900 MHz air interface protocol. According to the method, the circuit is simple in structure, resource consumption is small, and the requirement for low power consumption of the passive ultrahigh frequency tag is met.
Description
Technical field
The invention belongs to technical field of RFID, relate to ultrahigh-frequency passive electronic tag national standard " RF identification
800/900MHz air interface protocol " in label return communication speed problem of implementation.
Background technology
Super high frequency radio frequency identification national standard " RF identification 800/900MHz air interface protocol " is to label reverse link communication
The regulation of speed, is sent inquiry command by reader, by inquiry command parameter determination label return communication speed.
Start querying command (Query) startup once to be made an inventory circulation.Start querying command regulation to participate in this time making an inventory instead
To the link rate factor, the frame format starting querying command is shown in Table 1.
Table 1 starts the frame format of querying command
Regulation reverse link communication speed rule as follows: reverse link frequencies startup querying command in reverse link rate because of
Subdata territory determines, reverse link frequencies occurrence is shown in Table 2.
Table 2 reverse link frequencies
This agreement defines label and allows for supporting the traffic rate of all returns, each speed be fix, discrete frequency
Point, and part prime number each other, the error of frequency meets 20% just can meet requirement, but under hyperfrequency extremely low power dissipation requires,
Agitator to export these Frequency points and there is challenge.
The present invention combines chip and realizes, and provides corresponding overall implementation.
Summary of the invention
First return communication rate requirement is done one analyze such as table 3.
Table 3 reverse link frequencies
By this table it can be seen that return communication speed 349.09KHz to be replaced by 320KHz, or it is 384KHz, can
All return frequencies are become the integral frequency divisioil of 1.92MHz frequency, meets agreement error requirements simultaneously.
1) 349.09Khz uses 320KHz to substitute, i.e. 1.92MHz/6, and error ＜-10% meets requirement.
2) 349.09Khz uses 384KHz, i.e. 1.92MHz/5, and error is+10%
In like manner, it is possible to use 3.84MHz is as dominant frequency, and return speed with the relation of frequency dividing is the most accordingly:
Table 4 reverse link frequencies
Can be seen that agitator can select higher frequency (dominant frequency is the multiple of 1.92MHz) from principle, but frequency
The highest, chip power-consumption is the biggest, and therefore to take 1.92MHz or 3.84MHz proper for the mid frequency of chip oscillator.
After above-mentioned analysis, it is achieved method such as Fig. 1:
Whole functional module is by agitator, trimming circuit, frequency dividing circuit, logic control, non-volatile memory circuits
Five part compositions.
1) structure that agitator (OSC): local oscillator is conventional by ring oscillator, relaxation oscillator, based on Schmidt
The agitator of trigger.Agitator dominant frequency is 1.92MHz or 3.84MHz, and owing to agitator is in free-running operation, it produces
Raw is that clock frequency is very big, typically-20%～20% with temperature, process deviation.
2) Trimming circuit: use the value Trimming agitator being stored in NVM, agitator dominant frequency Trimming is arrived
1.92MHz, clock jitter reaches 1%.
3) frequency dividing circuit (divide): need agitator output (CLK) is divided according to controlling logic, returned
Communication frequency (BLF)
4) logic control circuit (control): carry out protocol integrated test system, memory data input and output, Trimming circuit
Sequential and divide ratio.
5) NVM circuitry, stores Trimming data.
Accompanying drawing explanation
Fig. 1 passive tag chip return communication speed realizes schematic diagram
Detailed description of the invention
After above-mentioned analysis, it is achieved method such as Fig. 1:
Whole functional module is by agitator, trimming circuit, frequency dividing circuit, logic control, non-volatile memory circuits
Five part compositions.
1) structure that agitator (OSC): local oscillator is conventional by ring oscillator, relaxation oscillator, based on Schmidt
The agitator of trigger.Agitator dominant frequency is 1.92MHz or 3.84MHz, and owing to agitator is in free-running operation, it produces
Raw is that clock frequency is very big, typically-20%～20% with temperature, process deviation.
2) Trimming circuit: use the value Trimming agitator being stored in NVM, agitator dominant frequency Trimming is arrived
1.92MHz, clock jitter reaches 1%.
3) frequency dividing circuit (divide): need agitator output (CLK) is divided according to controlling logic, returned
Communication frequency (BLF)
4) logic control circuit (control): carry out protocol integrated test system, memory data input and output, Trimming circuit
Sequential and divide ratio.
5) NVM circuitry, stores Trimming data.
Module routine is as follows:
1), after chip electrification reset, control logic and agitator Trimming value in memorizer sent into Trimming circuit,
The shapes to be received such as oscillator output frequencies is adjusted 1.92MHz (or 3.84MHz) according to Trimming, chip entrance
State.
2) in the state of reception, when receiving the Query order that reader sends, label interpretation order obtains analyzing system
Number, sends coefficient into frequency dividing circuit.
3) frequency dividing circuit exports corresponding return communication frequency according to coefficient of analysis.
It should be appreciated that the present embodiment is used for illustrative purposes only, rather than limitation of the present invention.Relevant technology is led
The technical staff in territory, without departing from the spirit and scope of the present invention, it is also possible to make various conversion or change, therefore
The technical scheme of all equivalents also should belong to scope of the invention and be limited by each claim.
Claims (2)
1. one kind realizes circuit for ultra-high-frequency passive RF identification national standard reverse link communication speed, it is characterised in that by vibrating
Device, trimming circuit, frequency dividing circuit, logic control circuit, nonvolatile storage five part form, wherein:
Agitator dominant frequency is 1.92MHz or 3.84MHz；
The Trimming circuit value Trimming agitator being stored in nonvolatile storage, by agitator dominant frequency Trimming
To 1.92MHz or 3.84MHz；
Frequency dividing circuit needs the output of agitator dominant frequency is carried out integral frequency divisioil according to controlling logic, obtains return communication frequency；
Logic control circuit carry out protocol integrated test system, nonvolatile storage data input and output, control Trimming circuit sequence and
Divide ratio；
Non-volatile memory circuits, stores Trimming data.
2., for a ultra-high-frequency passive RF identification national standard reverse link communication speed implementation method, it is applied to claim 1
In described circuit, it is characterised in that all return frequencies of protocol requirement will can be become 1.92MHz or 3.84MHz frequency
Integral frequency divisioil, meet passive radio frequency identification national standard error requirements simultaneously, step is as follows:
1), after chip electrification reset, agitator Trimming value in nonvolatile storage is sent into Trimming by logic control circuit
Circuit, oscillator output frequencies is adjusted 1.92MHz or 3.84MHz according to Trimming value, and chip entrance etc. is waiting
Receipts state；
2) when receiving the Query order that reader sends, label interpretation order obtains coefficient of analysis, and coefficient is sent into frequency dividing electricity
Road；
3) frequency dividing circuit exports corresponding return communication frequency according to coefficient of analysis；
4) integral frequency divisioil relation has:
During dominant frequency 1.92MHz, 349.09Khz uses 320KHz to substitute, i.e. 1.92MHz/6
Or 349.09Khz uses 384KHz to substitute, i.e. 1.92MHz/5
The relation that divides during dominant frequency 3.84MHz is: 349.09Khz, i.e. 3.84MHz/11.
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| CN201310637156.6A CN103646225B (en) | 2013-12-03 | 2013-12-03 | Method and circuit for ultrahigh frequency radio frequency identification tag reverse communication speed |
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| CN201310637156.6A CN103646225B (en) | 2013-12-03 | 2013-12-03 | Method and circuit for ultrahigh frequency radio frequency identification tag reverse communication speed |
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| CN103646225A CN103646225A (en) | 2014-03-19 |
| CN103646225B true CN103646225B (en) | 2017-01-11 |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105117674B (en) * | 2015-09-11 | 2018-03-13 | 深圳市远望谷信息技术股份有限公司 | Obtain the method and device of the internal oscillation frequency of RFID label tag |
| CN105389612A (en) * | 2015-11-09 | 2016-03-09 | 中国人民解放军国防科学技术大学 | Circuit and method for realizing reverse link frequency in electronic tag chip |
| CN109041203B (en) * | 2018-08-31 | 2020-12-29 | 深圳市金溢科技股份有限公司 | Electronic license plate reader-writer and reverse link frequency capturing method of electronic license plate |
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| CN1246219A (en) * | 1997-02-05 | 2000-03-01 | 福克斯企业股份有限公司 | Programmable crystal oscillator |
| JP2000341121A (en) * | 1999-05-26 | 2000-12-08 | Denso Corp | Frequency synthesizer circuit used for radio unit |
| CN1943126A (en) * | 2004-02-27 | 2007-04-04 | 智能宇宙研究院 | RFID tag device |
| CN102110221A (en) * | 2009-12-23 | 2011-06-29 | 北京中电华大电子设计有限责任公司 | Method for realizing block-write function of ultrahigh-frequency passive RFID |
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|---|---|---|---|---|
| CN1246219A (en) * | 1997-02-05 | 2000-03-01 | 福克斯企业股份有限公司 | Programmable crystal oscillator |
| JP2000341121A (en) * | 1999-05-26 | 2000-12-08 | Denso Corp | Frequency synthesizer circuit used for radio unit |
| CN1943126A (en) * | 2004-02-27 | 2007-04-04 | 智能宇宙研究院 | RFID tag device |
| CN102110221A (en) * | 2009-12-23 | 2011-06-29 | 北京中电华大电子设计有限责任公司 | Method for realizing block-write function of ultrahigh-frequency passive RFID |
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| 基于EPCClass0协议无源电子标签射频前端设计;沈红伟;《固体电子学研究与进展》;20080331;第66-69页 * |
| 基于NVM修复的模拟电路Trimming技术;高慧等;《微处理机》;20111030;第18-25页 * |
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Address after: 102209 Beijing, Beiqijia, the future of science and technology in the south area of China electronic network security and information technology industry base C building, Applicant after: Beijing CEC Huada Electronic Design Co., Ltd. Address before: 100102 Beijing City, Chaoyang District Lize two Road No. 2, Wangjing science and Technology Park A block five layer Applicant before: Beijing CEC Huada Electronic Design Co., Ltd. |
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