CN103631182A - HART (highway addressable remote transducer) communication hardware circuit device and HART communication method by same - Google Patents
HART (highway addressable remote transducer) communication hardware circuit device and HART communication method by same Download PDFInfo
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Abstract
The invention discloses an HART (highway addressable remote transducer) communication hardware circuit device and an HART communication method by the same. The circuit device comprises a microprocessor, an HART modulation-demodulation circuit, an HART communication-switch isolating circuit and a multichannel-switch isolating circuit. The microprocessor receives a channel selection instruction from hardware configuration and equipment management software and selects one channel of HART equipment through the multichannel-switch isolating circuit to realize HART communication such as point-to-point equipment parameter configuration between a mainframe and the HART equipment so as to enable multichannel HART equipment to share the public HART modulation-demodulation circuit. Compared with conventional point-to-point communication modes, the HART communication hardware circuit device has the advantages that costs of the HART modulation-demodulation circuit and the device are reduced; compared with conventional one-to-many all-digital communication modes, the device has the advantages that both analog communication and digital communication can be realized, mutual influences among the multiple channels are avoided, interference is small, and failure rate is low.
Description
Technical field
The present invention relates to HART communication technique field, especially relate to a kind of HART Communication hardware circuit device and communication means thereof.
Background technology
HART is the abbreviation of highway addressable remote sensor bus.HART agreement is the frequency shift keying digital signal that superposeed in 4～20mA simulating signal.Therefore, analog communication and digital communication can be carried out simultaneously, and digital communication can interference simulation communication, is a kind of for the communication protocol between field intelligent instrument and pulpit equipment.
HART agreement is the transitional technology occurring from analogue instrument to field bus system transition process, has over a period to come certain vitality.At present, HART product under the contract is widely used in automation control area.Because HART communication protocol is retaining on the basis of traditional 4～20mA current signal, expanded the ability of bi-directional digital communication, this agreement makes existing analogue instrument under improved situation, can progressively realizing digitizing, thereby greatly reduces costs, and enhances competitiveness.But at present HART equipment, must point-to-point communication when analog communication and digital communication are carried out, and is furnished with a HART communication device for each HART equipment simultaneously, cost is high like this, and profit is low, very uneconomical; And existing other can be realized the digital communication modes of one-to-many, so communication modes is complicated, and between its multiplexer channel, interference is large, and failure rate is high.
Summary of the invention
In order to address the above problem, realize multichannel HART point-to-point communication, and can reduce costs, guarantee that reliability is high, the advantage of failure rate is low simultaneously, the technical solution used in the present invention is as follows:
A HART Communication hardware circuit device, comprises that buffer circuit is switched in microprocessor, HART modulation-demodulation circuit, HART communication and multichannel is switched buffer circuit, wherein:
Described microprocessor is for sendaisle selection instruction and HART command information, and a HART device responds information receiving returns to external management terminal;
Described HART modulation-demodulation circuit, for according to the direction control signal of microprocessor, is modulated the data that send from described microprocessor or the data of switching buffer circuit transmission from described HART communication is carried out to demodulation;
Described HART communication switch buffer circuit for data transmission that described HART modulation-demodulation circuit is sent to corresponding HART equipment and the data of HART device responds are returned to described HART modulation-demodulation circuit;
Described multichannel switching buffer circuit is used to HART modulation-demodulation circuit and n road HART equipment to carry out data transmission provides line channel;
Described microprocessor switches buffer circuit by HART modulation-demodulation circuit and HART communication and is connected, described HART communication is switched buffer circuit and is connected with multichannel switching buffer circuit, described multichannel is switched buffer circuit and is connected with n road HART device signal output terminal respectively, and the control signal input end that buffer circuit and multichannel switching buffer circuit are switched in described HART modulation-demodulation circuit, HART communication is connected with the I/O end of microprocessor respectively.
Further, described n is 16, described multichannel is switched buffer circuit and is comprised that multichannel is switched buffer circuit one and multichannel is switched buffer circuit two, described multichannel is switched the HART device signal output terminal that buffer circuit one connects respectively 1 ~ 8 tunnel, multichannel is switched the HART device signal output terminal that buffer circuit two connects respectively 9 ~ 16 tunnels, the control signal input end that the control signal input end of described multichannel switching buffer circuit one and multichannel are switched buffer circuit two is connected respectively the I/O end of microprocessor, described multichannel is switched buffer circuit one and is connected with HART communication switching buffer circuit with multichannel switching buffer circuit two.
Further, described HART Communication hardware circuit device also comprises data acquisition circuit and channel switch, described multichannel is switched buffer circuit and by channel switch, is connected with n road HART device signal output terminal respectively, described data acquisition circuit is connected with microprocessor, the data input pin of described data acquisition circuit is connected with n road HART device signal output terminal by channel switch respectively, and the I/O end of described data acquisition circuit is connected with the Enable Pin of channel switch respectively.
Further, described n is 16, described multichannel is switched buffer circuit and is comprised that multichannel is switched buffer circuit one and multichannel is switched buffer circuit two, described multichannel is switched buffer circuit one and by channel switch, is connected respectively the HART device signal output terminal on 1 ~ 8 tunnel, multichannel is switched buffer circuit two and by channel switch, is connected respectively the HART device signal output terminal on 9 ~ 16 tunnels, the control signal input end that the control signal input end of described multichannel switching buffer circuit one and multichannel are switched buffer circuit two is connected respectively the I/O end of microprocessor, described multichannel is switched buffer circuit one and is connected with HART communication switching buffer circuit with multichannel switching buffer circuit two.
Further, described data acquisition circuit comprises 16 circuit-switched data Acquisition Circuit, 8 circuit-switched data Acquisition Circuit one and 8 circuit-switched data Acquisition Circuit two, described 8 circuit-switched data Acquisition Circuit one connect respectively the HART device signal output terminal on 1 ~ 8 tunnel by channel switch, described 8 circuit-switched data Acquisition Circuit two connect respectively the HART device signal output terminal on 9 ~ 16 tunnels by channel switch, described 8 circuit-switched data Acquisition Circuit one are connected with microprocessor by 16 circuit-switched data Acquisition Circuit respectively with 8 circuit-switched data Acquisition Circuit two, the I/O end of described 8 circuit-switched data Acquisition Circuit one is connected with the channel switch Enable Pin on 1 ~ 8 tunnel respectively, the I/O end of described 8 circuit-switched data Acquisition Circuit two is connected with the channel switch Enable Pin on 9 ~ 16 tunnels respectively.
Another object of the present invention is to provide the method that adopts above-mentioned HART Communication hardware circuit device to realize HART communication, comprise the steps:
S1: microprocessor sends the channel selecting instruction of HART communication to data acquisition circuit;
S2: data acquisition circuit finishes current channel sample and sends switch controlling signal to corresponding channel switch, and backward channel has switched information to microprocessor;
S3: microprocessor switches to multichannel the channel selecting control signal that buffer circuit sends communication, completes the foundation of corresponding HART communication channel;
S4: microprocessor sends HART command information to HART modulation-demodulation circuit, information is transferred to HART communication and switches buffer circuit after ovennodulation, then is transferred to selected HART equipment via multichannel switching buffer circuit;
S5:HART equipment sends response message, and information is transferred to microprocessor after the demodulation of HART modulation-demodulation circuit;
S6:HART communication completes, and microprocessor sends cut-off signal and switches buffer circuit to multichannel, sends HART communication Stop message to data acquisition circuit;
S7: multichannel is switched buffer circuit and disconnected when prepass connection, and data acquisition circuit finishes current HART communication and gets back to sampling pattern.
The present invention's beneficial effect compared with prior art:
1, by microprocessor, control multichannel switching buffer circuit and select a wherein road HART equipment, realizing main frame the HART such as arranges and communicates by letter with point-to-point device parameter between HART equipment, make the HART modulation-demodulation circuit of multichannel HART equipment sharing of common, compare with traditional point-to-point communication mode, reduced the cost that uses HART modulation-demodulation circuit, made the cost of this device.
2, failure rate is low.Between the multiplexer channel of this device, be independent of each other, interference is little, compares with the digital communication modes of traditional one-to-many, and failure rate is low, can realize analog communication and digital communication simultaneously.
3, in this device, use HART communication to switch buffer circuit and multichannel switching buffer circuit, realize the feature of isolation completely, reliability is high, is independent of each other between multiplexer channel simultaneously, and interference is little.
4, in this device, by microprocessor control channel switch and multichannel, switch buffer circuit and realize the switching between traditional sampling process and HART communication process, improved the versatility of system.
Accompanying drawing explanation
Fig. 1 is the principle schematic of a kind of HART Communication hardware circuit of the present invention device embodiment mono-.
Fig. 2 is the principle schematic of a kind of HART Communication hardware circuit of the present invention device embodiment bis-.
Fig. 3 is the principle schematic of a kind of HART Communication hardware circuit of the present invention device embodiment tri-.
Fig. 4 is the principle schematic of a kind of HART Communication hardware circuit of the present invention device embodiment tetra-.
Fig. 5 is the step schematic diagram of the embodiment of the method for HART communication of the present invention.
Embodiment
A kind of HART Communication hardware circuit device, as shown in Figure 1, comprise microprocessor 1, HART modulation-demodulation circuit 2, buffer circuit 3 is switched in HART communication and multichannel is switched buffer circuit 4, described microprocessor 1 switches buffer circuit 3 by HART modulation-demodulation circuit 2 and HART communication and is connected, I/O end and the HART modulation-demodulation circuit 2 of microprocessor 1, HART communication is switched buffer circuit 3 and is connected with the control signal input end of multichannel switching buffer circuit 4, for sendaisle selection instruction and HART command information, and the HART device responds information receiving is returned to external management terminal.Described HART modulation-demodulation circuit 2, for according to the direction control signal of the microprocessor 1 of receiving, is modulated the data that send from described microprocessor 1 or the data of switching buffer circuit 3 transmissions from described HART communication is carried out to demodulation.Described HART communication is switched buffer circuit 3 and is connected with multichannel switching buffer circuit 4, simultaneously, described multichannel is switched buffer circuit 4 and is connected with n road HART device signal output terminal respectively, and wherein port number n can be according to the needs of actual HART device talk and actual set.HART communication switch buffer circuit 3 for data transmission that described HART modulation-demodulation circuit 2 is sent to corresponding HART equipment and the data of HART device responds are returned to described HART modulation-demodulation circuit 2.Described multichannel switching buffer circuit 4 is used to HART modulation-demodulation circuit 3 and n road HART equipment to carry out data transmission provides line channel.
The course of work of described HART modulator-demodular unit and HART Communication hardware circuit device is as follows:
1, HART command information process of transmitting:
Described microprocessor 1 receives from channel selecting instruction and HART command information that hardware configuration and device management software are sent, by I/O port, to HART modulation-demodulation circuit 2 and HART communication switching buffer circuit 3, transmit control signal, by I/O port, to multichannel, switch buffer circuit 4 simultaneously and send selection signal, microprocessor 1 sends HART command information by serial ports to HART modulation-demodulation circuit 2 afterwards, information is transferred to HART communication and switches buffer circuit 3 after HART modulation-demodulation circuit 2 is modulated, via multichannel, switch buffer circuit 4 again and be transferred to selected HART equipment.
2, HART response message transmitting procedure:
Selected HART equipment receives after HART command information, device responds information is switched to buffer circuit 4 through multichannel and be transferred to HART communication switching buffer circuit 3, via HART communication, switch buffer circuit 3 again and be transferred to HART modulation-demodulation circuit 2, response message is transferred to the serial ports end of microprocessor 1 after 2 demodulation of HART modulation-demodulation circuit.Microprocessor 1 is from reading information in serial ports buffer zone, and the response message of acquisition is resolved and processed, and the information of HART device responds is returned to hardware configuration and device management software.
Fig. 2 is another embodiment of a kind of HART Communication hardware circuit of the present invention device, in itself and Fig. 1, the difference of embodiment is, port number n is 16, multichannel is switched buffer circuit 4 and is divided into multichannel switching buffer circuit 1 and multichannel switching buffer circuit 2 42, described multichannel is switched the HART device signal output terminal that buffer circuit one connects respectively 1 ~ 8 tunnel, multichannel is switched the HART device signal output terminal that buffer circuit two connects respectively 9 ~ 16 tunnels, the control signal input end that the control signal input end of described multichannel switching buffer circuit one and multichannel are switched buffer circuit two is connected respectively the I/O end of microprocessor, described multichannel is switched buffer circuit one and is connected with HART communication switching buffer circuit with multichannel switching buffer circuit two.
Described microprocessor 1 selects multichannel to switch buffer circuit according to the sequence number of selected special modality N: if 0≤N≤7, described microprocessor is sent out control signal to multichannel switching buffer circuit 1, makes the HART equipment of special modality N and microprocessor 1 carry out HART communication; If 8≤N≤15, described microprocessor 1 transmits control signal and switches buffer circuit 2 42 to multichannel, makes the HART equipment of special modality N and microprocessor 1 carry out HART communication.After the HART communication of HART equipment and microprocessor 1 completes, described microprocessor disconnects multichannel and switches buffer circuit 1 or multichannel switching buffer circuit 42.
Fig. 3 is the 3rd embodiment of a kind of HART Communication hardware circuit of the present invention device, data acquisition circuit 5 and the channel switch H1 ~ Hn that is arranged at each HART device signal output terminal on the basis of Fig. 1 embodiment, have been increased, described multichannel is switched buffer circuit 4 and by channel switch H1 ~ Hn, is connected with n road HART device signal output terminal respectively, described data acquisition circuit 5 is connected with microprocessor 1, the data input pin of described data acquisition circuit 5 is connected with n road HART device signal output terminal by channel switch H1 ~ Hn respectively, the I/O end of described data acquisition circuit 5 is connected with the Enable Pin of channel switch H1 ~ Hn respectively.
When starting to carry out HART communication, microprocessor 1 sends the channel selecting instruction of HART communication to data acquisition circuit 5, data acquisition circuit 5 interrupts current channel sample and sends switch controlling signal to the channel switch Enable Pin of corresponding HART device signal output terminal, and backward channel has switched information to microprocessor 1.Then microprocessor 1 switches buffer circuit 4 sendaisles selection control signals to multichannel, completes the foundation of corresponding HART communication channel, starts to carry out HART communication.
Fig. 4 is the 4th embodiment of a kind of HART Communication hardware circuit of the present invention device, it has increased by 16 circuit-switched data Acquisition Circuit 51 on the basis of Fig. 2 embodiment, 8 circuit-switched data Acquisition Circuit 1 and 8 circuit-switched data Acquisition Circuit 2 53, described 8 circuit-switched data Acquisition Circuit 1 connect respectively the HART device signal output terminal on 1 ~ 8 tunnel by channel switch H1 ~ H8, described 8 circuit-switched data Acquisition Circuit 2 53 connect respectively the HART device signal output terminal on 9 ~ 16 tunnels by channel switch H9 ~ H16, described 8 circuit-switched data Acquisition Circuit 1 are connected with microprocessor 1 by 16 circuit-switched data Acquisition Circuit 51 respectively with 8 circuit-switched data Acquisition Circuit 2 53, the I/O end of described 8 circuit-switched data Acquisition Circuit 1 is connected with the Enable Pin of the channel switch H1 ~ H8 on 1 ~ 8 tunnel respectively, the I/O end of described 8 circuit-switched data Acquisition Circuit two is connected with the Enable Pin of the channel switch H9 ~ H16 on 9 ~ 16 tunnels respectively.
When starting to carry out HART communication, microprocessor 1 sends the channel selecting instruction of HART communication to 16 circuit-switched data Acquisition Circuit 51,16 circuit-switched data Acquisition Circuit 51 are selected to transmit control signal to 8 circuit-switched data Acquisition Circuit 1 or 8 circuit-switched data Acquisition Circuit 2 53 according to the port number of the HART equipment of concrete required communication, make it interrupt current channel sample and send switch controlling signal to the channel switch Enable Pin of corresponding HART device signal output terminal, and backward channel has switched information to microprocessor 1.Then microprocessor 1 switches buffer circuit 4 sendaisles selection control signals to multichannel, completes the foundation of corresponding HART communication channel, starts to carry out HART communication.
Fig. 5, for using HART Communication hardware circuit device of the present invention to realize the method for HART communication, specifically comprises the steps:
S1: microprocessor sends the channel selecting instruction of HART communication to data acquisition circuit;
S2: data acquisition circuit finishes current channel sample and sends switch controlling signal to corresponding channel switch, and backward channel has switched information to microprocessor;
S3: microprocessor switches buffer circuit sendaisle to multichannel selects control signal, completes the foundation of corresponding HART communication channel;
S4: microprocessor sends HART command information to HART modulation-demodulation circuit, information is transferred to HART communication and switches buffer circuit after ovennodulation, then is transferred to selected HART equipment via multichannel switching buffer circuit;
S5:HART equipment sends response message, and information is transferred to microprocessor after the demodulation of HART modulation-demodulation circuit;
S6:HART communication completes, and microprocessor sends cut-off signal and switches buffer circuit to multichannel, sends HART communication Stop message to data acquisition circuit;
S7: multichannel is switched buffer circuit and disconnected when prepass connection, and data acquisition circuit finishes current HART communication and gets back to sampling pattern.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; any innovation and creation, modification that is no more than connotation scope of the present invention, all falls into protection scope of the present invention.
Claims (6)
1. a HART Communication hardware circuit device, is characterized in that, comprises that buffer circuit is switched in microprocessor, HART modulation-demodulation circuit, HART communication and multichannel is switched buffer circuit, wherein:
Described microprocessor is for sendaisle selection instruction and HART command information, and a HART device responds information receiving returns to external management terminal;
Described HART modulation-demodulation circuit, for according to the direction control signal of microprocessor, is modulated the data that send from described microprocessor or the data of switching buffer circuit transmission from described HART communication is carried out to demodulation;
Described HART communication switch buffer circuit for data transmission that described HART modulation-demodulation circuit is sent to corresponding HART equipment and the data of HART device responds are returned to described HART modulation-demodulation circuit;
Described multichannel switching buffer circuit is used to HART modulation-demodulation circuit and n road HART equipment to carry out data transmission provides line channel;
Described microprocessor switches buffer circuit by HART modulation-demodulation circuit and HART communication and is connected, described HART communication is switched buffer circuit and is connected with multichannel switching buffer circuit, described multichannel is switched buffer circuit and is connected with n road HART device signal output terminal respectively, and the control signal input end that buffer circuit and multichannel switching buffer circuit are switched in described HART modulation-demodulation circuit, HART communication is connected with the I/O end of microprocessor respectively.
2. HART Communication hardware circuit device according to claim 1, it is characterized in that, n is 16, described multichannel is switched buffer circuit and is comprised that multichannel is switched buffer circuit one and multichannel is switched buffer circuit two, described multichannel is switched the HART device signal output terminal that buffer circuit one connects respectively 1 ~ 8 tunnel, multichannel is switched the HART device signal output terminal that buffer circuit two connects respectively 9 ~ 16 tunnels, the control signal input end that the control signal input end of described multichannel switching buffer circuit one and multichannel are switched buffer circuit two is connected respectively the I/O end of microprocessor, described multichannel is switched buffer circuit one and is connected with HART communication switching buffer circuit with multichannel switching buffer circuit two.
3. HART Communication hardware circuit device according to claim 1, it is characterized in that, also comprise data acquisition circuit and channel switch, described multichannel is switched buffer circuit and by channel switch, is connected with n road HART device signal output terminal respectively, described data acquisition circuit is connected with microprocessor, the data input pin of described data acquisition circuit is connected with n road HART device signal output terminal by channel switch respectively, and the I/O end of described data acquisition circuit is connected with the Enable Pin of channel switch respectively.
4. HART Communication hardware circuit device according to claim 3, it is characterized in that, n is 16, described multichannel is switched buffer circuit and is comprised that multichannel is switched buffer circuit one and multichannel is switched buffer circuit two, described multichannel is switched buffer circuit one and by channel switch, is connected respectively the HART device signal output terminal on 1 ~ 8 tunnel, multichannel is switched buffer circuit two and by channel switch, is connected respectively the HART device signal output terminal on 9 ~ 16 tunnels, the control signal input end that the control signal input end of described multichannel switching buffer circuit one and multichannel are switched buffer circuit two is connected respectively the I/O end of microprocessor, described multichannel is switched buffer circuit one and is connected with HART communication switching buffer circuit with multichannel switching buffer circuit two.
5. HART Communication hardware circuit device according to claim 4, it is characterized in that, described data acquisition circuit comprises 16 circuit-switched data Acquisition Circuit, 8 circuit-switched data Acquisition Circuit one and 8 circuit-switched data Acquisition Circuit two, described 8 circuit-switched data Acquisition Circuit one connect respectively the HART device signal output terminal on 1 ~ 8 tunnel by channel switch, described 8 circuit-switched data Acquisition Circuit two connect respectively the HART device signal output terminal on 9 ~ 16 tunnels by channel switch, described 8 circuit-switched data Acquisition Circuit one are connected with microprocessor by 16 circuit-switched data Acquisition Circuit respectively with 8 circuit-switched data Acquisition Circuit two, the I/O end of described 8 circuit-switched data Acquisition Circuit one is connected with the channel switch Enable Pin on 1 ~ 8 tunnel respectively, the I/O end of described 8 circuit-switched data Acquisition Circuit two is connected with the channel switch Enable Pin on 9 ~ 16 tunnels respectively.
6. adopt arbitrary described circuit arrangement in claim 3-5 to realize the method that HART communicates by letter, it is characterized in that, comprise the steps:
S1: microprocessor sends the channel selecting instruction of HART communication to data acquisition circuit;
S2: data acquisition circuit finishes current channel sample and sends switch controlling signal to corresponding channel switch, and backward channel has switched information to microprocessor;
S3: microprocessor switches to multichannel the channel selecting control signal that buffer circuit sends communication, completes the foundation of corresponding HART communication channel;
S4: microprocessor sends HART command information to HART modulation-demodulation circuit, information is transferred to HART communication and switches buffer circuit after ovennodulation, then is transferred to selected HART equipment via multichannel switching buffer circuit;
S5:HART equipment sends response message, and information is transferred to microprocessor after the demodulation of HART modulation-demodulation circuit;
S6:HART communication completes, and microprocessor sends cut-off signal and switches buffer circuit to multichannel, sends HART communication Stop message to data acquisition circuit;
S7: multichannel is switched buffer circuit and disconnected when prepass connection, and data acquisition circuit finishes current HART communication and gets back to sampling pattern.
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