CN103578985B - Semiconductor devices and preparation method thereof - Google Patents
Semiconductor devices and preparation method thereof Download PDFInfo
- Publication number
- CN103578985B CN103578985B CN201310532887.4A CN201310532887A CN103578985B CN 103578985 B CN103578985 B CN 103578985B CN 201310532887 A CN201310532887 A CN 201310532887A CN 103578985 B CN103578985 B CN 103578985B
- Authority
- CN
- China
- Prior art keywords
- layer
- semiconductor devices
- gan
- compound layer
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 144
- 238000002360 preparation method Methods 0.000 title claims abstract description 7
- 150000001875 compounds Chemical class 0.000 claims abstract description 101
- 239000000758 substrate Substances 0.000 claims abstract description 91
- 238000000034 method Methods 0.000 claims abstract description 22
- 206010040844 Skin exfoliation Diseases 0.000 claims abstract description 19
- 230000035618 desquamation Effects 0.000 claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 claims abstract description 17
- 238000005468 ion implantation Methods 0.000 claims abstract description 12
- 239000010410 layer Substances 0.000 claims description 252
- 229910052751 metal Inorganic materials 0.000 claims description 40
- 239000002184 metal Substances 0.000 claims description 40
- 229910002704 AlGaN Inorganic materials 0.000 claims description 24
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 20
- 239000011521 glass Substances 0.000 claims description 19
- 239000011241 protective layer Substances 0.000 claims description 19
- 229910052594 sapphire Inorganic materials 0.000 claims description 15
- 239000010980 sapphire Substances 0.000 claims description 15
- 230000005669 field effect Effects 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 11
- 230000002269 spontaneous effect Effects 0.000 claims description 10
- 229910052731 fluorine Inorganic materials 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 7
- 238000002513 implantation Methods 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 125000005842 heteroatom Chemical group 0.000 claims description 4
- 238000001459 lithography Methods 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 239000013589 supplement Substances 0.000 claims 1
- 229910002601 GaN Inorganic materials 0.000 description 86
- 150000002500 ions Chemical class 0.000 description 37
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 33
- 230000015556 catabolic process Effects 0.000 description 33
- 239000010703 silicon Substances 0.000 description 33
- 229910052710 silicon Inorganic materials 0.000 description 33
- 238000002161 passivation Methods 0.000 description 31
- 238000004088 simulation Methods 0.000 description 15
- 239000000463 material Substances 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- 230000008859 change Effects 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 238000010992 reflux Methods 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 230000005611 electricity Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000002905 metal composite material Substances 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 230000005533 two-dimensional electron gas Effects 0.000 description 3
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 239000008186 active pharmaceutical agent Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910021478 group 5 element Inorganic materials 0.000 description 2
- -1 oxonium ion Chemical class 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 229910015363 Au—Sn Inorganic materials 0.000 description 1
- INQLNSVYIFCUML-QZTLEVGFSA-N [[(2r,3s,4r,5r)-5-(6-aminopurin-9-yl)-3,4-dihydroxyoxolan-2-yl]methoxy-hydroxyphosphoryl] [(2r,3s,4r,5r)-5-(4-carbamoyl-1,3-thiazol-2-yl)-3,4-dihydroxyoxolan-2-yl]methyl hydrogen phosphate Chemical compound NC(=O)C1=CSC([C@H]2[C@@H]([C@H](O)[C@@H](COP(O)(=O)OP(O)(=O)OC[C@@H]3[C@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=N1 INQLNSVYIFCUML-QZTLEVGFSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The present invention provides a kind of semiconductor devices and preparation method thereof, and the production method of the semiconductor devices includes at least：First semiconductor chip is provided；Three-five compound layer is formed in the upper surface of first semiconductor chip；Three-five semiconductor devices is prepared in the three-five compound layer, the three-five semiconductor devices is located at the upper surface of the three-five compound layer；The second semiconductor chip is bonded in the upper surface of the three-five compound layer；First semiconductor chip is removed using the technique of substrate desquamation, to expose the lower surface of the three-five compound layer；Using ion implantation technology strong electronegativity ion is injected from the three-five compound layer lower surface.Technical scheme of the present invention has blocked device that can improve the pressure resistance of device from the channel of the first semiconductor chip electric leakage as substrate.
Description
Technical field
The present invention relates to a kind of semiconductor technology, more particularly to a kind of semiconductor devices and preparation method thereof.
Background technology
Generally, the heterojunction field effect transistor in traditional technology（HEMT）As shown in Figure 1, including being formed in silicon substrate
The first semiconductor layer 200, the second semiconductor layer 400, source electrode 320, drain electrode 310 and grid 330 on 100.Described the first half lead
Body layer 200 and second semiconductor layer 400 form hetero-junctions, and there are two-dimensional electron gas at the heterojunction boundary.The source
Pole 310, drain electrode 320 and grid 330 are metal, and the source electrode 310, drain electrode 320 are located at 400 both ends of the second semiconductor layer,
And Ohmic contact is formed with first semiconductor layer 200, the grid 330 is located on second semiconductor layer 400, with institute
It states the second semiconductor layer 400 and forms Schottky contacts.When heterojunction field effect transistor works, by controlling under grid 330
Schottky barrier controls the concentration of the two-dimensional electron gas, so as to fulfill the control to electric current.First semiconductor layer 200
It is three-five compound layer with second semiconductor layer 400.Generally, the first semiconductor layer 200 is generally GaN, described the
Two semiconductor layers 400 are generally AlGaN, and the two forms AlGaN/GaN hetero-junctions.
It is highly difficult due to directly producing three-five compound substrate, currently based on the making work of heterojunction field effect transistor
In skill, three-five compound layer is grown on substrate base, then make electronics on the epitaxial layer of gallium nitride by general use
The mode of device.The material of these substrate bases has Si, SiC, sapphire（Sapphire）Or GaN（Bulk GaN）Deng.
Wherein, due to GaN growth silicon substrate have the advantages such as large scale, low cost, especially suitable for power electronic
Device application.However, compared to SiC, sapphire（Sapphire）Or GaN（Bulk GaN）, silicon substrate particularly low-resistance silicon lining
Bottom has the characteristics that resistivity is low, electric leakage is high.Therefore when epitaxial layer of gallium nitride is grown on a silicon substrate, the height prepared on it is electric
Transport factor transistor（HEMT）, Schottky diode（SBD）Wait transversal devices can because flow through silicon substrate longitudinal direction leak electricity without
There can be very high breakdown voltage.Thus, at present, super-pressure（>2000V）Gallium nitride power electronic device be concentrated mainly on by
GaN epitaxial layer is grown in SiC substrate or the mode by GaN growth on a sapphire substrate, and there are no be grown in GaN epitaxial layer
It is applied on Si, limits the popularization of gallium nitride power electronic device.
In order to solve this problem, the method that HRL laboratories in the U.S. propose backplate, as shown in Figure 2.In this device
Silicon substrate under drift region is cut through, and overleaf cut through region deposit back metal electrode be connected to source electrode, physically every
The channel of silicon substrate electric leakage absolutely.However, the longitudinal direction electric leakage that this backplate is had also been introduced simultaneously from backplate to drain electrode is logical
Road, objectively the backplate of well conducting substantially can not instead of semiconductive silicon substrate, the breakdown voltage of device
Higher than longitudinal breakdown voltage of the GaN epitaxial layer commonly based on Si substrates.
Invention content
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of semiconductor devices and its making
Method, for solving the problems, such as that three-five semiconductor devices cannot be formed on a silicon substrate in the prior art.
In order to achieve the above objects and other related objects, the present invention provides a kind of production method of semiconductor devices, at least
Including：
First semiconductor chip is provided；
Three-five compound layer is formed in the upper surface of first semiconductor chip；
Three-five semiconductor devices is prepared in the three-five compound layer, the three-five semiconductor devices is located at institute
State the upper surface of three-five compound layer；
The second semiconductor chip is bonded in the upper surface of the three-five compound layer；
First semiconductor chip is removed using the technique of substrate desquamation, to expose under the three-five compound layer
Surface；
Using ion implantation technology strong electronegativity ion is injected from the three-five compound layer lower surface.
Preferably, it is described to inject strong electronegativity ion from the three-five compound layer lower surface using ion implantation technology
The step of after further include step：Protective layer is formed in the lower surface of the three-five compound layer.
Preferably, after forming protective layer in the lower surface of the three-five compound layer, step is further included：
The protective layer and the three-five compound layer are performed etching using lithography and etching technique, formation is connected to
The through-hole of the three-five semiconductor devices；
Metal is filled in the through-hole, to form the electrode of the three-five semiconductor devices.
Preferably, the element that ion is injected in the ion implantation technology is O or F, implantation dosage 1e18cm-3~
1e20cm-3, Implantation Energy is more than or equal to 50keV.
Preferably, it is described to include the step of the upper surface of first semiconductor chip forms three-five compound layer：
Using depositing operation GaN layer is formed in the described first semiconductor-based on piece；
AlGaN layer is formed in the GaN layer or formed in the GaN layer using depositing operation using depositing operation
InAIN layer.
Preferably, after described the step of three-five semiconductor devices is prepared in the three-five compound layer, in institute
The upper surface for stating three-five compound layer is bonded before the second semiconductor chip, in addition on the three-five semiconductor devices
The step of forming Metal field plate.
Preferably, the three-five semiconductor devices is hetero junction field effect pipe and Schottky diode.
Preferably, first semiconductor chip is Si substrates.
Preferably, second semiconductor chip for Si substrates, SiC substrate, Sapphire Substrate, Glass substrates（Glass lined
Bottom）Or GaN substrate.
Correspondingly, technical scheme of the present invention additionally provides a kind of semiconductor devices, the semiconductor devices includes at least：
Three-five compound layer, the upper surface of the three-five compound layer is formed with three-five semiconductor devices, described
The lower surface of three-five compound layer, the three-five compound layer lower surface are injected with strong electronegativity ion；
Second semiconductor chip, positioned at the upper surface of the three-five compound layer.
Preferably, the lower surface of the three-five compound layer is also formed with protective layer.
Preferably, it is also formed in the semiconductor devices through the logical of the protective layer and the three-five compound layer
Hole；
Filled with metal in the through-hole, it is suitable for the electrode of the three-five semiconductor devices.
Preferably, the element of the strong electronegativity ion is O or F, and depth is 1 μm~2 μm.
Preferably, the three-five compound layer includes：GaN layer and AlGaN layer in the GaN layer or positioned at institute
State the InAIN layer in GaN layer.
Preferably, it is also formed with Metal field plate on the three-five semiconductor devices.
Preferably, the three-five semiconductor devices is hetero junction field effect pipe and Schottky diode.
Preferably, second semiconductor chip for Si substrates, SiC substrate, Sapphire Substrate, Glass substrates（Glass lined
Bottom）Or GaN substrate.
As described above, semiconductor devices of the present invention and preparation method thereof, has the advantages that：
Compared to traditional silicon based gallium nitride electronic device, technical scheme of the present invention takes the mode for removing silicon substrate,
Because having blocked channel of the device from substrate leakage, Gu the limit that the breakdown voltage of the device will not longitudinally be punctured by silicon substrate
System, can realize the pressure resistance more than two kilovolts.Meanwhile there is no sacrifice when device is opened while superelevation pressure resistance is realized
On state characteristic, have with traditional comparable current capacity of GaN-on-Si devices, be a kind of low cost and high reliability in GaN-
The method that the resistance to voltage device of superelevation is formed on on-Si materials.It can select to be bonded on the top of gallium nitride electronic device simultaneously a variety of
Material is as top substrate, such as Si, SiC, Sapphire, Glass or Bulk GaN, Gu its can device performance and device into
It is flexibly selected in this.It, can be with the work(such as HEMT, SBD integrated on a piece of silicon based gallium nitride chip with the technology of substrate desquamation
Rate electronic device is to form power electronics modules.
Description of the drawings
Fig. 1 is shown as the structure diagram of the heterojunction field effect transistor in traditional technology.
The heterojunction field effect transistor on a silicon substrate that Fig. 2 is shown as in traditional technology forms the signal of backplate
Figure.
Fig. 3 is shown as the flow chart of the production method of the semiconductor devices provided in technical scheme of the present invention.
Fig. 4 to Figure 16 is shown as the schematic diagram of formation field-effect transistor provided in embodiment one.
Figure 17 to Figure 29 is shown as the schematic diagram of formation Schottky diode provided in embodiment two.
Figure 30 to Figure 34 is shown as carrying out device performance simulation to the semiconductor devices provided in technical scheme of the present invention
Schematic diagram.
Component label instructions
100 silicon substrates
200 first semiconductor layers
201 two-dimensional electron gas
310 drain electrodes
320 source electrodes
330 grids
400 second semiconductor layers
11 AlGaN layers
12 GaN layers
13 first semiconductor chips
14 source electrodes
15 drain electrodes
16 gate dielectric layers
17 gate electrode layers
18 first passivation layers
19 Metal field plates
20 second passivation layers
21 bonded layers
22 second semiconductor chips
23 strong electronegativity ions
24 protective layers
34 negative electrodes
37 positive electrodes
S10~S60 steps
Specific embodiment
For convenience of description, first the vocabulary that this specification is related to is annotated.In this specification, relative words contain
Justice is subject to be annotated herein.
Iii v compound semiconductor：Semiconductor for the compound that group iii elements and group-v element are combined into.As Ga,
In, Al etc. belong to group iii elements；As, N etc. belong to group-v element.For example GaN, AlN, InN, GaAs, AlAs etc. belong to three or five
Compound semiconductor.
Technical scheme of the present invention provides a kind of production method of new semiconductor devices, it can be achieved that three-five is partly led
Body device is formed in based on the epitaxial layer of gallium nitride grown on a silicon substrate.Correspondingly, technical scheme of the present invention also provides
Semiconductor devices prepared by the production method, corresponding to HEMT in traditional traditional silicon based gallium nitride electronic device, this
The new semiconductor devices that technical scheme of the present invention provides is referred to as SLHEMT in embodiment, corresponding to traditional SBD, sheet
The new semiconductor devices provided in technical scheme of the present invention is referred to as SLSBD in embodiment.
Compared to traditional silicon based gallium nitride electronic device, technical scheme of the present invention takes the mode for removing silicon substrate,
Because having blocked channel of the device from substrate leakage, Gu the limit that the breakdown voltage of the device will not longitudinally be punctured by silicon substrate
System, can realize the pressure resistance more than two kilovolts.Meanwhile there is no sacrifice when device is opened while superelevation pressure resistance is realized
On state characteristic, have with traditional comparable current capacity of GaN-on-Si devices, be a kind of low cost and high reliability in GaN-
The method that the resistance to voltage device of superelevation is formed on on-Si materials.It can select to be bonded on the top of gallium nitride electronic device simultaneously a variety of
Material is as top substrate, such as Si, SiC, Sapphire, Glass or Bulk GaN, Gu its can device performance and device into
It is flexibly selected in this.It, can be with the work(such as HEMT, SBD integrated on a piece of silicon based gallium nitride chip with the technology of substrate desquamation
Rate electronic device is to form power electronics modules.
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Please refer to Fig. 3.It should be noted that the diagram provided in the present embodiment only illustrates the present invention's in a schematic way
Basic conception, component count, shape when only display is with related component in the present invention rather than according to actual implementation in schema then
And size is drawn, kenel, quantity and the ratio of each component can be a kind of random change during actual implementation, and its assembly layout
Kenel may also be increasingly complex.
The production method of the semiconductor devices provided in the present embodiment includes at least：
First, step S10 is performed：First semiconductor chip is provided；
Next, perform step S20：Three-five compound layer is formed in the upper surface of first semiconductor chip；
Next, perform step S30：The preparation three-five semiconductor devices in the three-five compound layer, described three
Five race's semiconductor devices are located at the upper surface of the three-five compound layer；
Next, perform step S40：The second semiconductor chip is bonded in the upper surface of the three-five compound layer；
Next, perform step S50：First semiconductor chip is removed using the technique of substrate desquamation, to expose
State the lower surface of three-five compound layer；
Next, perform step S60：Using ion implantation technology forceful electric power is injected from the three-five compound layer lower surface
Negativity ion.
Wherein, after the technique of substrate desquamation removes first semiconductor chip, then under three-five compound layer
Strong electronegativity ion is injected on surface, the lower surface of three-five compound layer can be given to introduce fixed negative electrical charge, so as to compensate nitrogen
Change the spontaneous influence intensified of gallium, form the back side isolated layer of a floor height electronic barrier, three-five compound layer is flowed through in effectively isolation
Longitudinal direction electric leakage, the semiconductor devices so as to provide in technical scheme of the present invention obtains higher breakdown voltage, realizes base
In the production of the three-five semiconductor devices of silicon substrate.
Correspondingly, technical scheme of the present invention additionally provides the semiconductor devices that above-mentioned production method is formed, it is described partly to lead
Body device includes at least：
Three-five compound layer, the upper surface of the three-five compound layer is formed with three-five semiconductor devices, described
The lower surface of three-five compound layer, the three-five compound layer lower surface are injected with strong electronegativity ion；
Second semiconductor chip, positioned at the upper surface of the three-five compound layer.
Specifically, the situation of technical solution provided by the invention is elaborated with two embodiments below.
Embodiment one
In the present embodiment, to form the field-effect transistor of three-five compound in the three-five compound layer
（HEMT）For.
First, with reference to shown in Fig. 3, with reference to figure 4, silicon substrate 13 is provided, 13 surface of silicon substrate is formed with three-five
Close nitride layer.
The silicon substrate 13 includes being located at first surface and corresponding second surface.The first surface is upper table
Face.
The three-five compound layer is formed in the first surface of the silicon substrate 13.In the present embodiment, the three-five
Compound layer includes AlGaN layer 11 and GaN layer 12, and the two forms AlGaN/GaN hetero-junctions.Those skilled in the art can understand
, AlGaN/GaN hetero-junctions is the current most important and most basic material system for making HEMT.Wherein, due to three-five
Compound has larger piezoelectric modulus（The piezoelectric modulus of AlN and GaN is 8.9 and 8.5）, meanwhile, the crystalline substance between AlN and GaN
Lattice mismatch is 2.5%, and big piezoelectric modulus and lattice mismatch there are one very strong piezoelectricity to intensify between GaN and AlGaN layer
Effect.On the other hand, three-five compound has low symmetrical crystal structure, this so that also there is very strong in AlGaN layer
Spontaneous intensify effect.It is spontaneous to intensify effect and piezoelectricity intensifies effect and is mutually reinforcing, this cause in AlGaN layer intensifying it is strong
Degree can reach the MV/cm orders of magnitude.In addition, due to conduction band discontinuity big at AlGaN/GaN heterostructure interfaces, one is provided
Very deep Quantum Well and the very 2DEG of high concentration, it is higher by an order of magnitude than traditional AlGaAs/GaAs systems.
In other embodiments, the three-five compound layer can also be other three-five compound layers and three or five
The combination of compounds of group layer.Such as the InAIN layer in GaN layer and GaN layer.
The generation type of the three-five compound layer is deposition.
Next, with reference to shown in Fig. 3, with reference to figure 5, formed in the AlGaN layer 11 and GaN layer 12 using etching technics
Opening.The position of the opening is the position of the source electrode and drain electrode of the HEMT.
In the present embodiment, the etching technics includes, and forms photoresist layer in the AlGaN layer 11, is shown through overexposure
Shadow forms the photoetching offset plate figure of source electrode and drain electrode on the photoresist layer, then utilizes the photoresist with source electrode and drain electrode
The photoresist of figure is as mask, using Cl2/ Ar carries out dry etching as etching gas, progress inductively coupled plasma,
Opening is formed in the AlGaN layer 11 and GaN layer 12.
Next, with reference to shown in Fig. 3, with reference to figure 6, metal is formed in said opening, to be formed Europe with the GaN layer 12
Nurse contacts, and forms the source electrode 14 of the HEMT and drain electrode 15.Wherein, the metal be high-work-function metal, generally Ni, Pt,
The metals such as Ti, Au or metal composites.
Next, with reference to shown in Fig. 3, with reference to figure 7, institute is formed in the GaN layer 12 between the source electrode 14 and drain electrode 15
State the grid of HEMT.The grid includes gate dielectric layer 16 and gate electrode layer 17.The grid and GaN layer 12 form schottky junctions
It touches.The material of the gate electrode layer 17 is metals or the metal composites such as Ti, Au, Pd, Ni, Cr or Pt.Gate dielectric layer 16 can
For Al2O3、HfO2Or SiN etc..
Next, with reference to shown in Fig. 3, with reference to figure 8, first is formed in the AlGaN layer 11 and the gate electrode layer 17
Passivation layer 18, the material of first passivation layer 18 is silica, boron-phosphorosilicate glass, silicon nitride etc..Generation type can be heavy
Product or reflux.First passivation layer 18 exposes the source electrode 14 and drain electrode 15.First passivation layer 18 is act as
AlGaN layer surface is protected, reduces surface defect charge.
Next, with reference to shown in Fig. 3, with reference to figure 9, the Metal field plate 19 of the HEMT is formed.The Metal field plate 19 wraps
It includes and is drawn from 14 surface of source electrode, is covered on the first passivation layer 18 between grid and drain electrode 15 across grid.The metal field
Plate 19 can electric field is distributed between smooth grid leak effect, improve device stability and resistance to pressure energy with reference to first passivation layer 18
Power.Metal field plate material can be metals or the metal composites such as Ti, Al, Ni, Au.With the Metal field plate principle class in silicon device
Seemingly, source bias can be introduced into above passivation layer by Metal field plate 19, with the electricity in the conducting channel below smooth passivation layer
Field distribution.
Next, with reference to shown in Fig. 3, with reference to figure 10, in first passivation layer 18, the Metal field plate 19, source electrode 14
The second flat passivation layer 20 is formed in drain electrode 15.The material of second passivation layer 20 is silica, boron-phosphorosilicate glass, nitrogen
SiClx etc..Generation type can be to first pass through deposition or reflux.Second passivation layer 20 can fill and lead up first passivation
Layer 18, the Metal field plate 19, source electrode 14 and the uneven of 15 surfaces that drain, and play a protective role.
Next, with reference to shown in Fig. 3, with reference to figure 11, the second semiconductor is bonded in the upper surface of second passivation layer 20
Substrate 22；
Second semiconductor chip 22 can be the substrates such as Si, SiC, Sapphire, Glass or Bulk GaN.This reality
It applies in example, second semiconductor chip 22 is Si substrates.
Specifically, in this step, the upper surface of second passivation layer 20 is bonded the technique packet of the second semiconductor chip 22
It includes：Bonded layer 21 is formed on the second passivation layer 20 by the method that metal or oxide layer deposit, then by bonded layer 21 by the
The methods of two semiconductor chips 22 are bonded with the second passivation layer 20 by metal bonding or oxide layer is bonded.Using the gold
When belonging to bonding technology, the bonded layer 21 can be Au-Sn, Au-Au.During using the oxide layer bonding technology, the bonding
Layer 21 can be silica.
Next, with reference to shown in Fig. 3, with reference to figure 12, first semiconductor chip is removed using the technique of substrate desquamation
13。
Next, with reference to shown in Fig. 3, with reference to figure 13, then using ion implantation technology from the three-five compound layer
Lower surface injection strong electronegativity ion 23；
The element that ion is injected in the ion implantation technology is O or F, implantation dosage 1e18cm-3~1e20cm-3, note
Enter energy more than or equal to 50keV.
These fluorine or oxonium ion can give the GaN back sides to introduce fixed negative electrical charge, so as to compensate the spontaneous shadows intensified of GaN
It rings, forms the back side isolated layer of a floor height electronic barrier.The longitudinal direction electric leakage for flowing through the GaN back sides can effectively be completely cut off in this way, so as to obtain
Obtain high breakdown voltage.
Next, with reference to shown in Fig. 3, with reference to figure 14, protective layer 24 is formed in the lower surface of the three-five compound layer.
The protective layer 24 can be silica, boron-phosphorosilicate glass, silicon nitride etc..Generation type can be deposition or reflux.
Next, with reference to shown in Fig. 3, with reference to figure 15, using lithography and etching technique to the protective layer and described 35
Compounds of group layer performs etching, and forms the through-hole for being connected to the three-five semiconductor devices；
Next, with reference to shown in Fig. 3, with reference to figure 16, metal is filled in the through-hole, is partly led with forming the three-five
The electrode of body device.
By above-mentioned technique, that is, form the field-effect transistor of three-five compound provided in this embodiment（SLHEMT）,
Including：Three-five compound layer, the field-effect transistor that the upper surface of the three-five compound layer is formed with（HEMT）, it is described
The lower surface of three-five compound layer, the three-five compound layer lower surface are injected with strong electronegativity ion 23；It is described strong
The element of electronegativity ion 23 is O or F, and depth is 1 μm~2 μm.
The three-five compound layer includes：GaN layer and AlGaN layer in the GaN layer or positioned at the GaN layer
On InAIN layer.Second semiconductor chip 22, positioned at the upper surface of the three-five compound layer.The three-five
The lower surface for closing nitride layer is also formed with protective layer 24.
The through-hole through the protective layer 24 and the three-five compound layer, institute are also formed in the semiconductor devices
It states in through-hole filled with metal, is suitable for the electrode of the three-five semiconductor devices.
In addition, it is also formed with Metal field plate 19 on the three-five semiconductor devices.
The three-five semiconductor devices is hetero junction field effect pipe（HEMT）.
Second semiconductor chip 22 is Si substrates, SiC substrate, Sapphire Substrate, Glass substrates（Glass substrate）Or
GaN substrate.
Embodiment two
In the present embodiment, to form Schottky diode in the three-five compound layer（SBD）For.
First, similar embodiment one with reference to shown in Fig. 3, with reference to figure 17, provides silicon substrate 13, shape on the silicon substrate 13
Into there is three-five compound layer.The three-five compound layer is formed in the first surface of the silicon substrate 13.In the present embodiment,
The three-five compound layer includes AlGaN layer 11 and GaN layer 12, in other embodiments, the three-five compound layer
It can also be the combination of other three-five compounds and three-five compound layer.Such as the InAlN in GaN layer and upper GaN layer
Layer.
Next, similar embodiment one, with reference to shown in Fig. 3, with reference to figure 18, using etching technics in the AlGaN layer 11
It is open with being formed in GaN layer 12.The position of the opening is the electrode of the SBD.
Next, similar embodiment one, with reference to shown in Fig. 3, with reference to figure 19, forms metal in said opening, with institute
It states GaN layer 12 and forms Ohmic contact, form the negative electrode 34 of the SBD.
Next, similar embodiment one, with reference to shown in Fig. 3, with reference to figure 20, in one end far from the negative electrode 34
Metal is formed in GaN layer 12, to be formed Schottky contacts with the GaN layer 12, forms the positive electrode 37 of the SBD.
Next, similar embodiment one, with reference to shown in Fig. 3, with reference to figure 21, forms the first passivation in the GaN layer 12
Layer 18.The both ends of first passivation layer 18 also partly cover the negative electrode 34 of the SBD and positive electrode 37.
Next, similar embodiment one, with reference to shown in Fig. 3, with reference to figure 22, is not covered in first passivation layer 18
The negative electrode 34 of SBD and the Metal field plate 19 of negative electrode 34 and blunt described first is formed in the GaN layer of negative electrode 34
The Metal field plate 19 of positive electrode 37 is formed on the SBD positive electrodes 37 and the GaN layer of close positive electrode 37 that change layer 18 does not cover.
Next, similar embodiment one, with reference to shown in Fig. 3, with reference to figure 23, in first passivation layer 18, the metal
The second flat passivation layer 20 is formed on field plate 19, negative electrode 34 and positive electrode 37.The material of second passivation layer 20 is oxygen
SiClx, boron-phosphorosilicate glass, silicon nitride etc..Generation type can be to first pass through deposition or reflux.Second passivation layer, 20 energy
First passivation layer 18, the Metal field plate 19, source electrode 14 and the uneven of 15 surfaces that drain enough are filled and led up, and plays guarantor
Shield acts on.
Next, similar embodiment one, with reference to shown in Fig. 3, with reference to figure 24, in the upper surface key of second passivation layer 20
Close the second semiconductor chip 22；
Second semiconductor chip 22 can be the substrates such as Si, SiC, Sapphire, Glass or Bulk GaN.This reality
It applies in example, second semiconductor chip 22 is Si substrates.
Specifically, in this step, the method deposited by metal or oxide layer of second passivation layer 20 is blunt second
Change and bonded layer 21 is formed on layer 20, then the second semiconductor chip 22 and the second passivation layer 20 are passed through by metallic bond by bonded layer 21
The methods of conjunction or oxide layer are bonded bonding is got up.
Next, similar embodiment one, with reference to shown in Fig. 3, with reference to figure 25, the technique stripping of substrate desquamation described the is utilized
Semiconductor substrate, to expose the lower surface of the three-five compound layer；
Next, similar embodiment one, with reference to shown in Fig. 3, with reference to figure 26, using ion implantation technology from the three-five
Compound layer lower surface injection strong electronegativity ion 23；
The element that ion is injected in the ion implantation technology is O or F, and implantation dosage is 1e18cm-3~1e20cm-3,
Implantation Energy is more than or equal to 50keV.
These fluorine or oxonium ion can give the GaN back sides to introduce fixed negative electrical charge, so as to compensate the spontaneous shadows intensified of GaN
It rings, forms the back side isolated layer of a floor height electronic barrier.The longitudinal direction electric leakage for flowing through the GaN back sides can effectively be completely cut off in this way, so as to obtain
Obtain high breakdown voltage.
Next, similar embodiment one, with reference to shown in Fig. 3, with reference to figure 27, in the lower surface of the three-five compound layer
Form protective layer 24.The protective layer 24 can be silica, boron-phosphorosilicate glass, silicon nitride etc..Generation type can be deposition
Or reflux.
Next, similar embodiment one, with reference to shown in Fig. 3, with reference to figure 28, using lithography and etching technique to the protection
Layer and the three-five compound layer perform etching, and form the through-hole for being connected to the three-five semiconductor devices；
Next, similar embodiment one, with reference to shown in Fig. 3, with reference to figure 29, metal is filled in the through-hole, to be formed
The electrode of the three-five semiconductor devices；
By above-mentioned technique, that is, form the Schottky diode of three-five semiconductor devices provided in this embodiment
（SLSBD）, including：Three-five compound layer, the Schottky diode that the upper surface of the three-five compound layer is formed with
（SBD）, the lower surface of the three-five compound layer, the three-five compound layer lower surface be injected with strong electronegativity from
Son.
The three-five compound layer includes：GaN layer and AlGaN layer in the GaN layer or positioned at the GaN layer
On InAIN layer.Second semiconductor chip 22, positioned at the upper surface of the three-five compound layer.The three-five
The lower surface for closing nitride layer is also formed with protective layer 24.
The through-hole through the protective layer 24 and the three-five compound layer, institute are also formed in the semiconductor devices
It states in through-hole filled with metal, is suitable for the electrode of the three-five semiconductor devices.
In addition, it is also formed with Metal field plate 19 on the three-five semiconductor devices.
The three-five semiconductor devices is Schottky diode（SBD）.
Second semiconductor chip 22 is Si substrates, SiC substrate, Sapphire Substrate, Glass substrates（Glass substrate）Or
GaN substrate.
In addition, inventor in order to verify the device performance of SLHEMT and SLSBD, uses Synopsys Sentaurus
TCAD softwares are to substrate desquamation but are not injected into the device of strong electronegativity ion and SLHEMT/SLSBD has carried out comparative simulation, specifically
Situation is as follows：
1. model structure
Each layer composition：
The material of passivation layer is SiN, thickness 200nm；
GaN layer includes cap layers of GaN and buffer layers of GaN, and the thickness that cap layers of GaN is 4nm；Buffer layers of GaN's
Thickness is 3 μm.
AlGaN layer thickness is 20nm；
At the back side of GaN buffer, SLHEMT/SLSBD has the strong electronegativity ion implanted layer of 200nm.
2. analog result
Figure 30 show the shutdown leakage current characteristic for carrying out substrate desquamation and injecting strong electronegativity ion SLSBD（Off-state
I-V）Schematic diagram, in figure, abscissa biases V for diode positive and negative anodesA, unit kV；Ordinate is diode current IA, unit
For A/mm.Including the BISDB of following several different situations：Channel length is 10 μm, simulates obtained device breakdown voltage
For 1.4kV；；Channel length is 20 μm, and simulation obtained device breakdown voltage is 4.1kV；Channel length is 30 μm, simulation gained device
Part breakdown voltage is 7.1kV；Channel length is 40 μm, and simulation obtained device breakdown voltage is 9.9kV；Channel length is 50 μm,
It is 12.8kV to simulate obtained device breakdown voltage.
Figure 31 show the shutdown leakage current characteristic for carrying out substrate desquamation and injecting strong electronegativity ion SLHEMT（Off-
state I-V）Schematic diagram.In figure, abscissa biases V for drain-sourceDS, unit kV；Ordinate is shutdown electric leakage ID, unit is
A/mm.Including the SLHEMT of following several different situations：Channel length is 10 μm, and simulation obtained device breakdown voltage is
1.4kV；Channel length is 20 μm, and simulation obtained device breakdown voltage is 4.2kV；Channel length is 30 μm, simulates obtained device
Breakdown voltage is 7.1kV；Channel length is 40 μm, and simulation obtained device breakdown voltage is 9.9kV；Channel length is 50 μm, mould
It is 12.8kV to intend obtained device breakdown voltage.
In Figure 30 and Figure 31 as it can be seen that carried out substrate desquamation and strong electronegativity ion implanting isolation after, SLSBD and
The breakdown voltage of SLHEMT increases with the growth of channel length, is not limited by GaN-on-Si chips longitudinal direction breakdown voltage（Its
In, chip longitudinal direction breakdown voltage is limited by GaN buffer layer thickness, is herein 3 μm）.When channel length is 50 microns,
Breakdown voltage can be more than 10,000 volts.
After Figure 32 show progress substrate desquamation, inject strong electronegativity ion and be not injected into strong electronegativity ion SLSBD's
Shutdown electric leakage（Off-state I-V）Comparison figure.In figure, abscissa biases V for diode positive and negative anodesA, unit kV；It is vertical to sit
It is designated as diode current IA, unit A/mm.Including the SLSDB of following several different situations：Channel length is 10 μm,
Strong electronegativity ion implanting is not injected into, simulation obtained device breakdown voltage is 800V；Channel length is 10 μm, injects strong electronegativity
Ion, simulation obtained device breakdown voltage are 1.4kV；Channel length is 50 μm, is not injected into strong electronegativity ion implanting, simulates institute
It is 800V to obtain device electric breakdown strength；Channel length is 50 μm, injects strong electronegativity ion, and simulation obtained device breakdown voltage is
12.8kV。
After Figure 33 show progress substrate desquamation, inject strong electronegativity ion and be not injected into strong electronegativity ion SLHEMT's
Shutdown electric leakage（Off-state I-V）Comparison figure.In figure, abscissa biases V for drain-sourceDS, unit kV；Ordinate is shutdown
Leak electricity ID, unit A/mm.Including the BISDB of following several different situations：Channel length is 10 μm, is not injected into forceful electric power
Negativity ion implanting, simulation obtained device breakdown voltage are 800V；Channel length is 10 μm, injects strong electronegativity ion, simulation
Obtained device breakdown voltage is 1.4kV；Channel length is 50 μm, is not injected into strong electronegativity ion implanting, and simulation obtained device is hit
Voltage is worn as 800V；Channel length is 50 μm, injects strong electronegativity ion, and simulation obtained device breakdown voltage is 12.8kV.
If as it can be seen that only having carried out substrate desquamation without doing the isolation of strong electronegativity ion implanting in Figure 32 and Figure 33, no matter
It is the influence that the breakdown voltage of SBD or HEMT device all can longitudinally be punctured by GaN-on-Si chips, no matter how raceway groove increases
Long, breakdown voltage is all limited in 800V or so.
After Figure 34 is carries out substrate desquamation, injection strong electronegativity ion and the GaN hetero-junctions for being not injected into strong electronegativity ion
Conduction band diagram.On GaN-on-Si epitaxial structures, after substrate desquamation is finished so as to expose buffer layers of GaN, because
Exclusive spontaneous of gallium nitride material intensifies characteristic, can be generated at buffer layers of back sides of GaN it is positive intensify charge, so as to drag down
The conduction band at the GaN back sides forms a back channel.In this way when device works, this back channel can help to flow through longitudinal electric leakage, shape
Into the effect similar to low-resistance silicon substrate.So substrate desquamation is only finished, even eliminating silicon substrate, but because nitridation
Gallium spontaneous the reason of intensifying, still cannot completely cut off to fall longitudinal electric leakage, and device electric breakdown strength is not helped.
But it ought overleaf inject after strong electronegativity ion, these ions can give the GaN back sides to introduce fixed negative electrical charge, from
And compensate the spontaneous influence intensified of gallium nitride, form the back side isolated layer of a floor height electronic barrier.Stream can effectively be completely cut off in this way
The longitudinal direction electric leakage at the GaN back sides is crossed, so as to obtain high breakdown voltage.
In conclusion the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (15)
1. a kind of production method of semiconductor devices, which is characterized in that the production method of the semiconductor devices includes at least：
First semiconductor chip is provided；
Three-five compound layer is formed in the upper surface of first semiconductor chip：It is led using depositing operation described the first half
GaN layer is formed on body substrate, AlGaN layer is formed in the GaN layer using depositing operation or utilizes depositing operation in the GaN
InAIN layer is formed on layer；
Three-five semiconductor devices is prepared in the three-five compound layer, the three-five semiconductor devices is located at described three
The upper surface of five compounds of group layers；
The second semiconductor chip is bonded in the upper surface of the three-five compound layer；
First semiconductor chip is removed using the technique of substrate desquamation, to expose the lower surface of the GaN layer；
Strong electronegativity ion O or F are injected from the GaN layer lower surface using ion implantation technology, to draw at the GaN layer back side
Enter fixed negative electrical charge, so as to supplement the spontaneous influence intensified of GaN layer, form the back side isolated layer of a floor height electronic barrier.
2. the production method of semiconductor devices according to claim 1, it is characterised in that：It is described to utilize ion implantation technology
Step is further included after the step of injecting strong electronegativity ion from the three-five compound layer lower surface：In the three-five
The lower surface for closing nitride layer forms protective layer.
3. the production method of semiconductor devices according to claim 2, it is characterised in that：In the three-five compound layer
Lower surface formed protective layer after, further include step：
The protective layer and the three-five compound layer are performed etching using lithography and etching technique, formation is connected to described
The through-hole of three-five semiconductor devices；
Metal is filled in the through-hole, to form the electrode of the three-five semiconductor devices.
4. the production method of semiconductor devices according to claim 1, it is characterised in that：It is noted in the ion implantation technology
The implantation dosage for entering ion is 1e18cm-3~1e20cm-3, Implantation Energy is more than or equal to 50keV.
5. the production method of semiconductor devices according to claim 1, it is characterised in that：In the three-five compound layer
After the step of middle preparation three-five semiconductor devices, in the upper surface of the three-five compound layer, bonding second is semiconductor-based
Before piece, in addition on the three-five semiconductor devices formed Metal field plate the step of.
6. the production method of semiconductor devices according to claim 1, it is characterised in that：The three-five semiconductor devices
For hetero junction field effect pipe and Schottky diode.
7. the production method of semiconductor devices according to claim 1, it is characterised in that：First semiconductor chip is
Si substrates.
8. the production method of semiconductor devices according to claim 1, it is characterised in that：Second semiconductor chip is
Si substrates, SiC substrate, Sapphire Substrate, glass substrate or GaN substrate.
9. a kind of semiconductor devices, which is characterized in that the semiconductor devices includes at least：
Three-five compound layer, the upper surface of the three-five compound layer are formed with three-five semiconductor devices, and described 35
Compounds of group layer includes：GaN layer and the AlGaN layer in the GaN layer or the InAIN layer in the GaN layer；It is described
GaN layer lower surface is injected with strong electronegativity ion O or F, to introduce fixed negative electrical charge at the GaN layer back side, so as to mend
It fills the spontaneous influence intensified of GaN layer, forms the back side isolated layer of a floor height electronic barrier；
Second semiconductor chip, positioned at the upper surface of the three-five compound layer.
10. semiconductor devices according to claim 9, it is characterised in that：The lower surface of the three-five compound layer is also
Form matcoveredn.
11. semiconductor devices according to claim 10, it is characterised in that：It is also formed with running through in the semiconductor devices
The through-hole of the protective layer and the three-five compound layer；
Filled with metal in the through-hole, it is suitable for the electrode of the three-five semiconductor devices.
12. semiconductor devices according to claim 9, it is characterised in that：The depth of the strong electronegativity ion for 1 μm~
2μm。
13. semiconductor devices according to claim 9, it is characterised in that：It is also formed on the three-five semiconductor devices
There is Metal field plate.
14. semiconductor devices according to claim 9, it is characterised in that：The three-five semiconductor devices is hetero-junctions
Field-effect tube and Schottky diode.
15. semiconductor devices according to claim 9, it is characterised in that：Second semiconductor chip for Si substrates,
SiC substrate, Sapphire Substrate, glass substrate or GaN substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310532887.4A CN103578985B (en) | 2013-11-01 | 2013-11-01 | Semiconductor devices and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310532887.4A CN103578985B (en) | 2013-11-01 | 2013-11-01 | Semiconductor devices and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103578985A CN103578985A (en) | 2014-02-12 |
| CN103578985B true CN103578985B (en) | 2018-06-26 |
Family
ID=50050497
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310532887.4A Active CN103578985B (en) | 2013-11-01 | 2013-11-01 | Semiconductor devices and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103578985B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9978844B2 (en) | 2013-08-01 | 2018-05-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | HEMT-compatible lateral rectifier structure |
| CN103943677B (en) * | 2014-04-16 | 2016-08-17 | 中国科学院半导体研究所 | A kind of chip scale gallium nitride based transistor and preparation method thereof |
| KR101750158B1 (en) * | 2014-12-26 | 2017-06-22 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Hemt-compatible lateral rectifier structure |
| CN112382664A (en) * | 2020-11-03 | 2021-02-19 | 广东省科学院半导体研究所 | Flip MOSFET device and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101336482A (en) * | 2005-11-29 | 2008-12-31 | 香港科技大学 | Low density drain hemts |
| CN102651385A (en) * | 2011-02-25 | 2012-08-29 | 富士通株式会社 | Method of producing semiconductor device and semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8076699B2 (en) * | 2008-04-02 | 2011-12-13 | The Hong Kong Univ. Of Science And Technology | Integrated HEMT and lateral field-effect rectifier combinations, methods, and systems |
| CN102097483B (en) * | 2010-12-31 | 2012-08-29 | 中山大学 | GaN-base heterostructure enhancement type insulated gate field effect transistor and preparation method thereof |
| JP2012190936A (en) * | 2011-03-09 | 2012-10-04 | Sharp Corp | Device mounting structure of semiconductor device |
-
2013
- 2013-11-01 CN CN201310532887.4A patent/CN103578985B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101336482A (en) * | 2005-11-29 | 2008-12-31 | 香港科技大学 | Low density drain hemts |
| CN102651385A (en) * | 2011-02-25 | 2012-08-29 | 富士通株式会社 | Method of producing semiconductor device and semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103578985A (en) | 2014-02-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10686064B2 (en) | Nitride semiconductor device and fabrication method therefor | |
| CN103890923B (en) | Semiconductor device | |
| TWI671908B (en) | Semiconductor device, electrical machine, bi-directional field effect transistor and mounting structure | |
| Lu et al. | High-performance integrated dual-gate AlGaN/GaN enhancement-mode transistor | |
| CN104319238B (en) | Form the method and its structure of high electron mobility semiconductor device | |
| TWI515874B (en) | Semiconductor device, method for manufacturing the same, power supply, and high-frequency amplifier | |
| JP5789967B2 (en) | Semiconductor device, manufacturing method thereof, and power supply device | |
| CN106158948B (en) | III-nitride enhanced HEMT device and manufacturing method thereof | |
| CN104022148A (en) | Heterostructure power transistor with AlSiN passivation layer | |
| CN103972284A (en) | Semiconductor device | |
| CN101924128B (en) | Field-effect transistor | |
| JP2010287725A (en) | Semiconductor device | |
| TWI706566B (en) | A high power semiconductor device | |
| CN104465745A (en) | Method Of Manufacturing A Semiconductor Device And The Semiconductor Device | |
| CN104269433B (en) | Gallium-nitride-based enhancement type heterojunction field effect transistor with composite channel layer | |
| CN103578985B (en) | Semiconductor devices and preparation method thereof | |
| JP5510544B2 (en) | Compound semiconductor device and manufacturing method thereof | |
| CN111900203A (en) | GaN-based high-hole mobility transistor and preparation method thereof | |
| Chowdhury | GaN-on-GaN power device design and fabrication | |
| US20120080724A1 (en) | Semiconductor device | |
| CN102856374A (en) | GaN enhanced MIS-HFET device and preparation method of same | |
| CN102194819A (en) | Enhanced GaN heterojunction field effect transistor based on metal oxide semiconductor (MOS) control | |
| CN104599957B (en) | Semiconductor devices and preparation method thereof | |
| KR20140112272A (en) | High Electron Mobility Transistor and method of manufacturing the same | |
| CN106449746B (en) | The GaN HEMT of current collapse effect can be improved |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 401331 No. 25 Xiyong Avenue, Shapingba District, Chongqing Patentee after: Huarun Microelectronics (Chongqing) Co., Ltd. Address before: 401331 No. 25 Xiyong Avenue, Xiyong Town, Shapingba District, Chongqing Patentee before: China Aviation (Chongqing) Microelectronics Co., Ltd. |
|
| CP03 | Change of name, title or address |