CN103516656B - Inverse fast fourier transform implementation method and device - Google Patents
Inverse fast fourier transform implementation method and device Download PDFInfo
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Abstract
The invention discloses a kind of inverse fast fourier transform implementation method and device.Wherein, this method includes：The multi-antenna data stream of input is received, multi-antenna data stream is merged into the first data flow；Multiplication operation is carried out to the first data flow according to multiple antenna weights of acquisition, obtains the second data flow, and inverse fast fourier transform is carried out to the second data flow（IFFT）Processing, obtains the 3rd data flow, wherein, the corresponding antenna weights of each antenna；Exported after carrying out multiple stage circulation iteration multiply-add operation to the 3rd data flow according to the twiddle factor prestored, wherein, twiddle factor supports various bandwidth configuration.By the present invention, so as to reach reduction processing delay, improve flexible structure autgmentability, the flexible and changeable networking requirements of operator can be met.
Description
Technical field
The present invention relates to the communications field, in particular to a kind of inverse fast fourier transform implementation method and device.
Background technology
OFDM（Orthogonal Frequency Division Multiplexing, referred to as OFDM）Skill
Art can be applied in the communication system of bandwidth varying, for example, Long Term Evolution（Long Term Evolution, referred to as LTE）System
System needs to support 20MHz bandwidth, 15MHz bandwidth, 10MHz bandwidth, 5MHz bandwidth, 3MHz bandwidth and 1.4MHz bandwidth simultaneously, no
Number with subcarrier corresponding to bandwidth also differs, correspondingly, when the subcarrier to different numbers is modulated, it is necessary to hold
The inverse fast fourier transform of the different points of row（Inverse Fast Fourier Transform, referred to as IFFT）Processing.
Common IFFT processing units typically take following three kinds of processing modes：
When mode one, the n times power that points are 2, field programmable gate array can be directly invoked（Filed
Programmable Gate Array, referred to as FPGA）IP core built in producer are realized；
When mode two, the n times power that points are non-2, first by the n times power of interpolation of data 0 to 2 to count recently, then using side
Formula one completes the IFFT processing of corresponding scale, then carries out extraction operation to output data again；
When mode three, the n times power that points are non-2, the IFFT for first carrying out full-page proof point is decomposed step by step, then the butterfly decomposed entirely
Shape computing.
Above-mentioned three kinds of processing modes are specific as follows in actual applications in place of equal Shortcomings：
Mode one can not meet all band width configurations supported needed for LTE system；
Mode two uses interpolating operations, causes time domain sequences to introduce leakage interference and can not filter out sampling, performance reduction
And corresponding hardware cost is high；
Mode three is implemented complex, and is taken more FPGA and patrolled using the IFFT full operation splittings of big sampling point
Collect resource and storage resource.
Asking for drawbacks described above is respectively present for three kinds of processing modes that the IFFT processing units in correlation technique are taken
Topic, not yet proposes effective solution at present.
The content of the invention
The invention provides a kind of inverse fast fourier transform implementation method and device, at least to solve the above problems.
According to an aspect of the invention, there is provided a kind of inverse fast fourier transform implementation method, including：Receive input
Multi-antenna data stream, multi-antenna data stream is merged into the first data flow；Counted according to multiple antenna weights of acquisition to first
Multiplication operation is carried out according to stream, obtains the second data flow, and inverse fast fourier transform is carried out to the second data flow（IFFT）Processing,
The 3rd data flow is obtained, wherein, the corresponding antenna weights of each antenna；According to the twiddle factor prestored to the 3rd data
Stream exports after carrying out multiple stage circulation iteration multiply-add operation, wherein, twiddle factor supports various bandwidth configuration.
Preferably, multi-antenna data stream is merged into the first data flow, including：The P point multi-antenna data streams of input are received,
P point multi-antenna datas stream is extracted and is mapped as M circuit-switched data streams；For each circuit-switched data stream, rule is redirected according to predetermined address
After reading P/2M data, insertion is further continued for reading remaining P/2M data for Q 0, is finished when being read to each circuit-switched data stream
When, N number of data flow is obtained, wherein, N=P+M*Q；By N number of data stream merging it is the first data flow according to antenna order.
Preferably, multiple antenna weights are obtained in the following manner：System type is judged, when system type is time division duplex
（TDD）When, acquisition system carries out the N number of antenna weights obtained after antenna calibration operation, when system type is FDD（FDD）
When, N number of antenna weights are set as 1.
Preferably, multiplication operation is carried out to the first data flow according to multiple antenna weights of acquisition, obtains the second data flow,
And inverse fast fourier transform is carried out to the second data flow（IFFT）Processing, obtains the 3rd data flow, including：N number of antenna is weighed
Value carries out multiplication operation with the first data flow, obtains the second data flow；M IFFT processing is carried out to the second data flow, in IFFT
In the case that the amplitude of data flow after processing is without departing from predetermined amplitude threshold value, the data flow after IFFT is handled is as the 3rd number
According to stream, in the case where the amplitude of the data flow after IFFT is handled exceeds predetermined amplitude threshold value, according to the power control being pre-configured with
Data flow after factor pair IFFT processing processed carries out cut position processing, obtains the 3rd data flow.
Preferably, according to the twiddle factor prestored to defeated after the 3rd data flow progress multiple stage circulation iteration multiply-add operation
Go out, including：3rd data flow is respectively written into M different cachings, obtains M pending data stream；Rule are redirected according to address
Then, read respectively per pending data stream all the way from M different cachings；According to predetermined reading rule, respectively from storage
Twiddle factor corresponding with per pending data stream all the way is read in the spatial cache of twiddle factor；To per pending data all the way
Stream and corresponding twiddle factor carry out complex multiplication operation, Bing Duigai roads pending data stream and complex multiplication operation result
Complex addition operations are carried out, obtain interative computation result, wherein, twiddle factor WN -n, n span is（0, N-1）；It is right
Interative computation result exports after carrying out successive ignition computing, wherein, the number of interative computation is determined by band width configuration.
According to another aspect of the present invention, there is provided a kind of inverse fast fourier transform realization device, including：Merge mould
Block, for receiving the multi-antenna data stream of input, multi-antenna data stream is merged into the first data flow；First processing module, use
Multiplication operation is carried out to the first data flow in multiple antenna weights according to acquisition, obtains the second data flow, and to the second data
Stream carries out inverse fast fourier transform（IFFT）Processing, obtains the 3rd data flow, wherein, the corresponding antenna power of each antenna
Value；Second processing module, for carrying out the multiply-add fortune of multiple stage circulation iteration to the 3rd data flow according to the twiddle factor prestored
Exported after calculation, wherein, twiddle factor supports various bandwidth configuration.
Preferably, merging module includes：Map unit, for receiving the P point multi-antenna data streams of input, by more days of P points
Line data flow extracts and is mapped as M circuit-switched data streams；First reading unit, for for each circuit-switched data stream, according to predetermined address
After redirecting rule P/2M data of reading, insertion is further continued for reading remaining P/2M data for Q 0, when to each circuit-switched data stream
When reading finishes, N number of data flow is obtained, wherein, N=P+M*Q；Combining unit, for closing N number of data flow according to antenna order
And it is the first data flow.
Preferably, first processing module includes：Judging unit, for judging system type；Acquiring unit, for working as system
Standard is time division duplex（TDD）When, acquisition system carries out the N number of antenna weights obtained after antenna calibration operation；Setup unit, use
In being FDD when system type（FDD）When, N number of antenna weights are set as 1.
Preferably, first processing module also includes：Computing unit, for N number of antenna weights and the progress of the first data flow
Multiplication operates, and obtains the second data flow；Processing unit, M IFFT processing is carried out to the second data flow, the number after IFFT processing
According to the amplitude of stream without departing from predetermined amplitude threshold value in the case of, data flow after IFFT is handled as the 3rd data flow,
In the case that the amplitude of data flow after IFFT processing exceeds predetermined amplitude threshold value, according to the power control factor pair being pre-configured with
Data flow after IFFT processing carries out cut position processing, obtains the 3rd data flow.
Preferably, Second processing module includes：Memory cell, for the 3rd data flow to be stored in respectively, M is individual different to be delayed
Deposit, obtain M pending data stream；Second reading unit, for redirecting rule according to address, divide in the caching different from M
Du Qu not be per pending data stream all the way；3rd reading unit, for according to predetermined reading rule, respectively from storage rotation because
Twiddle factor corresponding with per pending data stream all the way is read in the spatial cache of son；First arithmetic element, for each
Road pending data stream and corresponding twiddle factor carry out complex multiplication operation, Bing Duigai roads pending data stream and plural number
Multiplication result carries out complex addition operations, obtains interative computation result, wherein, twiddle factor WN -n, n span
For（0, N-1）；Second arithmetic element, for being exported after carrying out successive ignition computing to interative computation result, wherein, interative computation
Number determined by band width configuration.
By the present invention, multichannel data is carried out at IFFT computings respectively using reception data are divided into after multichannel data
Reason operation, and the data of IFFT calculation process are multiplied with the mode of iterative processing again, solve the various bandwidth mixing of LTE system
The problem of flexible configuration, while avoided performance loss and the full complicated algorithm for decomposing IFFT that interpolating operations are brought, so as to reach
Arrive that reduction processing delay is low, improves flexible structure autgmentability, the effects of the flexible and changeable networking requirements of operator can be met.
Brief description of the drawings
Accompanying drawing described herein is used for providing a further understanding of the present invention, forms the part of the application, this hair
Bright schematic description and description is used to explain the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings：
Fig. 1 is inverse fast fourier transform implementation method flow chart according to embodiments of the present invention；
Fig. 2 is inverse fast fourier transform implementation method according to embodiments of the present invention answering in down physical layer processing
Use position（Ofdm signal produces the stage）Schematic diagram；
Fig. 3 is the inverse fast fourier transform implementation process figure of present system according to the preferred embodiment of the invention；
Fig. 4 is multiple antennas carrier wave mapping according to the preferred embodiment of the invention and multiplexing process flow chart；
Fig. 5 is multiple antennas carrier wave mapping according to the preferred embodiment of the invention and multiplexing schematic diagram；
Fig. 6 is IFFT processing schematic diagram according to the preferred embodiment of the invention；
Fig. 7 is according to the preferred embodiment of the invention to multiply iterative processing schematic diagram again；
Fig. 8 is the structured flowchart of inverse fast fourier transform realization device according to embodiments of the present invention；
Fig. 9 is the structured flowchart of inverse fast fourier transform realization device in accordance with a preferred embodiment of the present invention；
Figure 10 is the structural representation according to the inverse fast fourier transform realization device of another preferred embodiment of the present invention
Figure.
Embodiment
Describe the present invention in detail below with reference to accompanying drawing and in conjunction with the embodiments.It should be noted that do not conflicting
In the case of, the feature in embodiment and embodiment in the application can be mutually combined.
Fig. 1 is inverse fast fourier transform implementation method flow chart according to embodiments of the present invention, as shown in figure 1, the party
Method mainly includes the following steps that（Step S102- steps S106）.
Step S102, receives the multi-antenna data stream of input, and multi-antenna data stream is merged into the first data flow.
Step S104, multiplication operation is carried out to the first data flow according to multiple antenna weights of acquisition, obtains the second data
Stream, and inverse fast fourier transform is carried out to the second data flow（IFFT）Processing, obtains the 3rd data flow, wherein, each antenna
A corresponding antenna weights.
Step S106, after carrying out multiple stage circulation iteration multiply-add operation to the 3rd data flow according to the twiddle factor prestored
Output, wherein, twiddle factor supports various bandwidth configuration.
In the step S102 of the present embodiment, when multi-antenna data stream is merged into the first data flow, this can be passed through
The mode of sample is implemented：The P point multi-antenna data streams of input are first received, P point multi-antenna datas stream is extracted and is mapped as M circuit-switched datas
Stream；Each circuit-switched data stream is directed to again, is redirected according to predetermined address after rule reads P/2M data, and insertion Q individual 0 is followed by resuming studies
Remaining P/2M data are taken, when being finished to the reading of each circuit-switched data stream, obtain N number of data flow, wherein, N=P+M*Q；Most
Afterwards, it is the first data flow by N number of data stream merging according to antenna order.
In the step S104 of the present embodiment, multiple antenna weights are obtained in the following manner：System type is judged, when being
Controlling formula is time division duplex（TDD）When, acquisition system carries out the N number of antenna weights obtained after antenna calibration operation, when system system
Formula is FDD（FDD）When, N number of antenna weights are set as 1.
The step S104 of the present embodiment can be achieved in that：Multiplication operation is carried out to N number of antenna weights and the first data flow,
Obtain the second data flow；M IFFT processing is carried out to the second data flow, the amplitude of the data flow after IFFT processing is without departing from width
In the case of being worth threshold value, the data flow after IFFT is handled is as the 3rd data flow, the amplitude of the data flow after IFFT processing
In the case of amplitude thresholds, the data flow after IFFT processing is carried out at cut position according to the power control factor being pre-configured with
Reason, obtains the 3rd data flow.
The step S106 of the present embodiment can be achieved in that：The 3rd data flow is first respectively written into M different cachings, obtained
To M pending data stream；Rule is redirected according still further to address, is read respectively per number pending all the way in the caching different from M
According to stream；According to predetermined reading rule, read respectively from the spatial cache of storage twiddle factor and every pending data all the way
Twiddle factor corresponding to stream；Complex multiplication operation is carried out to every pending data stream all the way and corresponding twiddle factor, and
Complex addition operations are carried out to the road pending data stream and complex multiplication operation result, obtain interative computation result, wherein, rotation
Transposon is WN -n, n span is（0, N-1）；Exported after carrying out successive ignition computing to interative computation result, wherein, repeatedly
Determined for the number of computing by band width configuration.
First, in order to better understand above-described embodiment, lower simple declaration is done to the application site of the embodiment.It refer to
Fig. 2, Fig. 2 are that inverse fast fourier transform implementation method according to embodiments of the present invention applies position in down physical layer processing
Put（Ofdm signal produces the stage）Schematic diagram, as shown in Fig. 2 this method is mainly used in the ofdm signal of down physical layer processing
The generation stage（The schematic diagram in the stage has made background mark）.
Inverse fast fourier transform implementation method with reference to Fig. 3 to Fig. 7 and preferred embodiment to the embodiment of the present invention
It is described in detail.
Fig. 3 is the inverse fast fourier transform implementation process figure of present system according to the preferred embodiment of the invention, such as
Shown in Fig. 3, this method mainly includes the following steps that（Step S302- steps S310）.
Step S302, the P point data streams of input are received, are respectively written into the spatial cache each specified.
Step S304, multiplexing process unit is mapped according to configured bandwidth, from each spatial cache, reads the common N of M circuit-switched datas
Point, for rear class data processing.
Step S306, N point datas are sequentially inputted, 1 512 point IFFT processing unit of recursive call, complete M IFFT fortune
Calculate.
Step S308, by the M circuit-switched datas of Serial output, M different spatial caches are respectively written into by control module.
Step S310, the twiddle factor stored in data, with another spatial cache is read from M different spatial caches
Complete M complex multiplication operation.Scale operation is completed in output data, prevents data from overflowing.
It is further detailed with reference to the mapping of Fig. 4 and Fig. 5 multiple antennas carrier wave and multiplexing process flow.
Fig. 5 is multiple antennas carrier wave mapping according to the preferred embodiment of the invention and multiplexing schematic diagram, in Figure 5, multiple antennas
Carrier wave maps and multiplexing process flow can be implemented.
（1）According to configured bandwidth, computing scale and multiplexing scale now, the data that prime has been handled, write-in are determined
The spatial cache specified, the Various types of data stream of write-in switch processing at interval of between a data symbol data flow of progress
（According to the data symbol where odd positions and even number position data are write to different spatial caches）.
（2）According to configured bandwidth, data are read from spatial cache, for rear class data processing.Now, Fig. 4 is refer to,
Fig. 4 is multiple antennas carrier wave mapping according to the preferred embodiment of the invention and multiplexing process flow chart, as shown in figure 4, flow master
Comprise the following steps（Step S402- steps S410）.
Step S402, the P point datas having been written into spatial cache are read, be divided into the output of M circuit-switched datas.
In the preferred embodiment, the common P data flow of a data symbol, extraction are mapped as M roads, per P/M number all the way
According to stream.It is 1 that address is read in initialization, and address adds M to be incremented by, and redirecting rule according to M roads address below calculates M roads address.
Step S404, the reading address ram_raddr_ch1 for calculating the first via are：1, M+1,2M+1,3M+1, P-M+
1。
Step S406, the reading address ram_raddr_ch2 for calculating the second tunnel are：2, M+2,2M+2,3M+2, P-M+
2。
Step S408, the reading address ram_raddr_chM for calculating M roads are：M, 2M, 3M, 4M, P.
Step S410, M roads reading address is sequentially serially merged, reads N point datas.
Wherein, during each road address serial Sequential output, for each circuit-switched data, P/2M data are being read
Afterwards, Q data 0 are inserted, then complete the reading of each data of P/2M again, M times is circulated and obtains M roads N number of data flow altogether.
Wherein P, M, N value are determined that the calculated relationship between several parameters is by the tupe of current system：P+
M*Q=N。
The span of each parameter is：M span is that 1 ~ 4, P span is 72 ~ 1200, Q span
Span for 112 ~ 212, N is 512 ~ 2048.
In data read process, the hand-off process between a data flow is carried out at interval of a data symbol（According to
Data symbol where odd positions and even number position reads data from different spatial caches）, in actual applications, can be by
Successively read according to antenna order, the data of final multiple antennas merge into a data flow, then carry out multiple antennas serial i FFT processing.
In actual applications, can also be to a piece of slow every time after the completion of different spatial cache read data operations
Deposit space and be zeroed out operation, it is ensured that the processing between each data symbol is independently independent of each other.
Fig. 6 is IFFT processing schematic diagram according to the preferred embodiment of the invention, and in figure 6, IFFT handling processes can be with this
Sample is implemented.
（1）The standard to be worked according to system, decide whether to carry out antenna calibration operation.
（2）In time division duplex（Time Division Duplexing, referred to as TDD）Under pattern, it is necessary to according to configuration band
Multiple antenna weights that wide storage system obtains after being corrected to multiple antennas.In FDD（Frequency Division
Duplexing, referred to as FDD）Under pattern, weights replace using complete 1.The size of lower total resources block is configured according to various scales,
It is determined that shared memory space.
（3）According to different configuration of bandwidth, the address of reading antenna correction weights is produced, N number of weights stream is obtained, is divided into M
The value on road, wherein N and M is determined by the tupe of current system, and is the integer more than or equal to 1.
（4）N number of weights stream that multiple antennas carrier wave is mapped and N number of data flow of multiplexing process unit output is read with step 3
Complete multiplication operation.Multi-antenna data serially completes M IFFT processing.Data to completing IFFT processing, use the work(of configuration
The control factor enters the processing of Mobile state cut position, it is ensured that the amplitude of data flow is in predetermined amplitude range.
Fig. 7 be it is according to the preferred embodiment of the invention multiply iterative processing schematic diagram again, in the figure 7, multiply iterative processing stream again
Journey can be implemented.
（1）The N number of data flow in M roads after cut position is handled, M different spatial caches are respectively written into by control module.
The 1 ~ N/M data flow, write the 1st caching；The N/M+1 ~ 2*N/M data flow, write the 2nd caching；(M-1) * N/M
+ 1 ~ N number of data flow, write-in m-th caching.
（2）The address of control enable signal such as step 1 redirects rule unanimously, is required to be adjusted online according to configured bandwidth
It is whole.
（3）Hand-off process between data flow：Carried out at interval of N/M data stream at the switching between once data flow
Reason.
（4）From specified spatial cache, data are read.Because data divide M roads, control data is needed to circulate M reading herein
Go out, it is necessary to do complex multiplication operation with twiddle factor.
（5）, it is necessary to multiply a twiddle factor W in a stream during every grade of interative computationN -n, n span
For（0, N-1）.Because the band width configuration that system needs are supported is more, simplest design is that various bandwidth are both needed to one rotation of storage
The table of transposon.
It should be noted that for herein, following more optimal scheme can also be used in actual applications.
In actual applications, the real and imaginary parts of twiddle factor can be divided into four quadrants.Found according to the derivation of equation
Certain corresponding relation is respectively present, therefore, spatial cache can be saved using symmetry.For example, cosine can be set
The point of one quadrant is A, and the point of the second quadrant is B, the value of other two quadrants of cosine and four sinusoidal quadrants value,
To be derived from.The method can save 80% spatial cache.
（5a）Address is read in initialization, and the reading address initialization for reading cosine twiddle factor is 0, reads sinusoidal twiddle factor
Reading address initialization is N/M.
（5b）According to the bandwidth parameter of configuration, determine that address redirects rule and reads the content of which spatial cache.Tool
Body, it is assumed that with a width of 20M, then the shared spatial caches of 20M and 10M are read, now N=2048, M=4.Cosine twiddle factor is read
Address adds 1 to be incremented by, and sinusoidal twiddle factor is read address decrement and successively decreased.In actual applications, at the beginning of cosine twiddle factor being read into address
Beginning turns to 0, adds 1 increment operation, and when reading to be incremented to 1023, address jumps to 0 again, continues reading address and adds 1 increment operation；Will
It is 512 that sinusoidal twiddle factor, which reads address initialization, the decrement operations that subtract 1, and when reading decreasing addresses to 0, address jumps to 1023, after
Resume studies address decrement decrement operations；The operation completes the reading of the twiddle factor of 1 symbol after having traveled through at 2048 points.
（5c）Read spatial cache（The spatial cache is exclusively used in data storage）In M circuit-switched datas, while read another
Twiddle factor in spatial cache, the two is completed complex multiplication operations, completes scale operation in output data, prevent data from overflowing
Go out.
（5d）The M-1 circuit-switched datas in spatial cache are read, are gone forward side by side the H cycle of line delay, when H is step 5c processing
Prolong.The data obtained after the H cycle of delay, the output data with step 5c, complex addition operation is carried out, it is complete in output data
Into scale operation, prevent data from overflowing.
（5e）Read spatial cache（The spatial cache is exclusively used in storing selective factor B, and the spatial cache with data storage is
Different spatial caches）In twiddle factor, method is shown in step 5b, goes forward side by side the K cycle of line delay, and K is step 5c+5d processing
Time delay.The twiddle factor obtained after the K cycle of delay, the output data with step 5d, complex multiplication operations are carried out, in output number
According to when complete scale operation, prevent data from overflowing.
（5f）The M-2 circuit-switched datas in spatial cache are read, are gone forward side by side the L cycle of line delay, L is step 5c+5d+5e place
Manage time delay.The data obtained after the L cycle of delay, the output data with step 5e, complex addition operation is carried out, in output data
When complete scale operation, prevent data from overflowing.
Above-mentioned 5e ~ 5f operations are repeated, until reading the 1st circuit-switched data in spatial cache.
（6）The N number of data flow in M roads after multiplying iterative processing again, by antenna Serial output, is pressed by write buffer control module
Antenna is respectively written into the spatial cache of respective antenna.
Below by taking LTE system configured bandwidth 20MMHz bandwidth as an example, to the inverse fast fourier transform of the embodiment of the present invention
Implementation method is more specifically illustrated.In LTE system configured bandwidth 20MMHz bandwidth, system needs to support 2048 simultaneously
Point and 1536 point IFFT processing, preceding 2 antennas support 2048 point IFFT, and rear 2 antennas support 1536 point IFFT.
1st, 1200 point data streams are inputted, are respectively written into the spatial cache that respective antenna is specified.Carry out 2048 point IFFT number
4 tunnels are mapped as according to extraction, per 512 data flows all the way；The data pick-up for carrying out 1536 point IFFT is mapped as 3 tunnels, per all the way 512
Individual data flow.
2nd, 2048 point IFFT data flow is carried out, it is 1 that address is read in initialization, and address adds 4 to be incremented by.4 tunnels address redirect rule
It is as follows：
The reading address ram_raddr_ch1 of the first via is：1,5,9,13,1197；
The reading address ram_raddr_ch2 on the second tunnel is：2,6,10,14,1198；
The reading address ram_raddr_ch3 on the 3rd tunnel is：3,7,11,15,1199；
The reading address ram_raddr_ch4 on the 4th tunnel is：4,8,12,16,1200；
Each road address serial Sequential output, each circuit-switched data, after 150 data are read, 212 data 0 are inserted, then
The reading of 150 data is completed again.Circulate 4 times and obtain 4 tunnels totally 2048 data flows.
3rd, 1536 point IFFT data flow is carried out, it is 1 that address is read in initialization, and address adds 3 to be incremented by.3 tunnels address redirect rule
It is as follows：
The reading address ram_raddr_ch1 of the first via is：Isosorbide-5-Nitrae, 7,10,1198；
The reading address ram_raddr_ch2 on the second tunnel is：2,5,8,13,1199；
The reading address ram_raddr_ch3 on the 3rd tunnel is：3,6,9,12,1200；
Each road address serial Sequential output, each circuit-switched data, after 200 data are read, 112 data 0 are inserted, then
The reading of 200 data is completed again.Circulate 3 times and obtain 3 tunnels totally 1536 data flows.
4th, front-end module data write-in is in units of symbol, and the duration in symbol does not know.Therefore cache
Space is according to ping-pong operation come what is opened up, and the Various types of data stream of write-in is at interval of between a data symbol data flow of progress
Hand-off process.
5th, carry out 2048 point IFFT data flow and carry out 1536 point IFFT data flow, be serially to enter each processing module
, only take up a set of resource.
6th, reading antenna corrects weights from weights spatial cache.Under tdd mode, the weights of configuration, fdd mode are used
Under, no weights, replaced using complete 1, ensure the uniformity of handling process.Preceding 2 antennas support 2048 point IFFT, read 2048
Weights, it is divided into 4 tunnels；2 antennas support 1536 point IFFT afterwards, read 1536 weights, are divided into 3 tunnels.
7th, the data of the mapping of multiple antennas carrier wave and the output of multiplexing process unit complete multiplication with the corresponding weights that step 6 is read
Operation.Complete the serial mode after multiplication operation and be sent into IFFT processing, support 2048 point IFFT need to complete 4 times 512 point IFFT
Operation, 1536 point IFFT need are supported to complete 3 times 512 point IFFT operations.
8th, the data handled completing IFFT, enter Mobile state cut position using the power control factor of configuration and handle, it is ensured that data flow
Amplitude in predetermined amplitude range.
9th, the data flow of the point IFFT of 4 tunnel 2048 after cut position is handled, by control module be respectively written into 4 it is different slow
Deposit space.1st ~ 512 data flow, write the 1st caching；513rd ~ 1024 data flow, write the 2nd caching；1025th ~
1536 data flows, write the 3rd caching；1537th ~ 2048 data flow, write the 4th caching.
10th, the data flow of the point IFFT of 3 tunnel 1536 after cut position is handled, by control module be respectively written into 3 it is different
Spatial cache.1st ~ 512 data flow, write the 1st caching；513rd ~ 1024 data flow, write the 2nd caching；The
1025 ~ 1536 data flows, write the 3rd caching.
11st, from specified spatial cache, data are read.It is that circulation is carried out because rear class multiplies iterative operation again, herein
Spatial cache is also to be opened up according to ping-pong operation.
12nd, it is necessary to be multiplied by twiddle factor W in a stream during every grade of interative computationN -n.The point IFFT of 4 tunnel 2048
Data flow, read the shared spatial cache of 20MHz and 10MHz bandwidth；The point IFFT of 3 tunnel 1536 data flow, read 15MHz bands
Wide spatial cache.
13rd, the specific steps of the shared spatial cache of 20MHz and 10MHz bandwidth are read：
It is 0 that cosine twiddle factor is read into address initialization, adds 1 increment operation, and when reading to be incremented to 1023, address is jumped again
0 is gone to, continues reading address and adds 1 increment operation.
It is 512 that sinusoidal twiddle factor is read into address initialization, and the decrement operations that subtract 1, when reading decreasing addresses to 0, address is jumped
1023 are gone to, continues to read address decrement decrement operations.
The operation is after circulation travel through at 2048 points 4 times, i.e. the reading of the twiddle factor of 1 symbol of completion.
14th, the specific steps of the spatial cache of 15MHz bandwidth are read：
It is 0 that cosine twiddle factor is read into address initialization, adds 1 increment operation, and when reading to be incremented to 767, address is jumped again
0 is gone to, continues reading address and adds 1 increment operation.
It is 384 that sinusoidal twiddle factor is read into address initialization, and the decrement operations that subtract 1, when reading decreasing addresses to 0, address is jumped
767 are gone to, continues to read address decrement decrement operations.
The operation is after circulation travel through at 1536 points 3 times, i.e. the reading of the twiddle factor of 1 symbol of completion.
15th, the point IFFT of 4 tunnel 2048 answering for data flow multiplies iterative processing：
15a：The 4th circuit-switched data in spatial cache is read, while such as the reading twiddle factor of operation 13, the two completion CM
Method operates.Scale operation is completed in output data, prevents data from overflowing.
15b：The 3rd circuit-switched data in spatial cache is read, is gone forward side by side the H cycle of line delay, H is step 15a processing delay,
Size is related to the time delay that selected multiplication operates, and general range is 2 ~ 6 clock cycle.Data after the H cycle of delay,
With step 15a output data, complex addition operation is carried out.
15c：Such as operate 13 reading twiddle factors, be delayed K cycle, K is step 15a+15b processing delay, size and
Selected multiplication is related to the time delay of add operation, and general range is 3 ~ 7 clock cycle.Obtained after the K cycle of delay
Twiddle factor, the output data with step 15b, carry out complex multiplication operations.Scale operation is completed in output data, prevents from counting
According to spilling.
15d：The 2nd circuit-switched data in spatial cache is read, is gone forward side by side the L cycle of line delay, L is step 15a+15b+15c's
Processing delay, general range are 5 ~ 13 clock cycle.Data after the L cycle of delay, the output data with step 15c, enter
Row complex addition operates.
15e：13 reading twiddle factors are such as operated, are delayed G cycle, when G is step 15a+15b+15c+15d processing
Prolong, general range is in 6 ~ 14 clock cycle.The twiddle factor obtained after the G cycle of delay, the output data with step 15d,
Carry out complex multiplication operations.Scale operation is completed in output data, prevents data from overflowing.
15f：The 1st circuit-switched data in spatial cache is read, is gone forward side by side the J cycle of line delay, J is step 15a+15b+15c+
15d+15e processing delay, general range are 8 ~ 20 clock cycle.Data after the J cycle of delay, it is defeated with step 15e
Go out data, carry out complex addition operation.
16th, 2048, the 4 tunnel data flow after step 15 multiplies iterative processing again, by antenna Serial output, by write buffer
Control module is respectively written into the spatial cache of respective antenna by antenna.
17th, the point IFFT of 3 tunnel 1536 answering for data flow multiplies iterative processing：
17a：The 3rd circuit-switched data in spatial cache is read, is gone forward side by side the H cycle of line delay, H is step 15a processing delay,
Size is related to the time delay that selected multiplication operates, and general range is 3 ~ 7 clock cycle.
17b：Such as operate 14 reading twiddle factors, be delayed K cycle, K is step 17a processing delay, general range 3
~ 7 clock cycle.The twiddle factor obtained after the K cycle of delay, the output data with step 17a, carry out complex multiplication behaviour
Make.Scale operation is completed in output data, prevents data from overflowing.
17c：The 2nd circuit-switched data in spatial cache is read, is gone forward side by side the L cycle of line delay, L is step 17a+17b processing
Time delay, general range are 5 ~ 13 clock cycle.Data after the L cycle of delay, the output data with step 14c, are answered
Number add operation.
17d：Such as operate 14 reading twiddle factors, be delayed G cycle, G for step 17a+17b+17c processing delay, one
As scope in 7 ~ 19 clock cycle.The twiddle factor obtained after the G cycle of delay, the output data with step 17c, is answered
Number multiplication operation.Scale operation is completed in output data, prevents data from overflowing.
17e：The 1st circuit-switched data in spatial cache is read, is gone forward side by side the J cycle of line delay, J is step 17a+17b+17c+
17d processing delay, general range are 8 ~ 20 clock cycle.Data after the J cycle of delay, the output number with step 17d
According to progress complex addition operation.
18th, 1536, the 3 tunnel data flow after step 17 multiplies iterative processing again, by antenna Serial output, by write buffer
Control module is respectively written into the spatial cache of respective antenna by antenna.
The inverse fast fourier transform implementation method provided using above-described embodiment, is solved the various bandwidth of LTE system and mixed
The problem of closing flexible configuration, while avoided performance loss and the full complicated algorithm for decomposing IFFT that interpolating operations are brought, so as to
Reach that reduction processing delay is low, improves flexible structure autgmentability, the effects of the flexible and changeable networking requirements of operator can be met
Fruit.
Fig. 8 is the structured flowchart of inverse fast fourier transform realization device according to embodiments of the present invention, the device to
Realize that the inverse fast fourier transform that above-described embodiment provides is realized, as shown in figure 8, the device mainly includes：Merging module 10,
First processing module 20 and Second processing module 30.Wherein, merging module 10, for receiving the multi-antenna data stream of input,
Multi-antenna data stream is merged into the first data flow；First processing module 20, merging module 10 is connected to, for according to acquisition
Multiple antenna weights carry out multiplication operation to the first data flow, obtain the second data flow, and the second data flow are carried out inverse quick
Fourier transformation（IFFT）Processing, obtains the 3rd data flow, wherein, the corresponding antenna weights of each antenna；Second processing mould
Block 30, first processing module 20 is connected to, for carrying out multiple stage circulation to the 3rd data flow according to the twiddle factor prestored
Exported after iteration multiply-add operation, wherein, twiddle factor supports various bandwidth configuration.
Fig. 9 is the structured flowchart of inverse fast fourier transform realization device in accordance with a preferred embodiment of the present invention, such as
Shown in Fig. 9, in the preferred embodiment, merging module 10 can include：Map unit 12, for receiving the P point multiple antennas of input
Data flow, P point multi-antenna datas stream is extracted and is mapped as M circuit-switched data streams；First reading unit 14, is connected to map unit 12,
For for each circuit-switched data stream, redirected according to predetermined address after rule reads P/2M data, insertion Q individual 0 is followed by resuming studies
Remaining P/2M data are taken, when being finished to the reading of each circuit-switched data stream, obtain N number of data flow, wherein, N=P+M*Q；Merge
Unit 16, the first reading unit 14 is connected to, for by N number of data stream merging being the first data flow according to antenna order.
In the device that the preferred embodiment provides, first processing module 20 can include：Judging unit 22, for judging
System type；Acquiring unit 24, judging unit 22 is connected to, for being time division duplex when system type（TDD）When, obtain system
Carry out the N number of antenna weights obtained after antenna calibration operation；Setup unit 26, judging unit 22 is connected to, for when system system
Formula is FDD（FDD）When, N number of antenna weights are set as 1.
In the device that the preferred embodiment provides, first processing module 20 can also include：Computing unit 27, for pair
N number of antenna weights and the first data flow carry out multiplication operation, obtain the second data flow；Processing unit 28, is connected to computing unit
27, to the second data flow carry out M IFFT processing, IFFT handle after data flow amplitude without departing from amplitude thresholds situation
Under, the data flow after IFFT is handled exceeds amplitude thresholds as the 3rd data flow, the amplitude of the data flow after IFFT processing
In the case of, cut position processing is carried out to the data flow after IFFT processing according to the power control factor being pre-configured with, obtains the 3rd
Data flow.
In the device that the preferred embodiment provides, Second processing module 30 can include：Memory cell 32, for by
Three data flows are stored in M different cachings respectively, obtain M pending data stream；Second reading unit 34, it is single to be connected to storage
Member 32, for redirecting rule according to address, read respectively per pending data stream all the way in the caching different from M；Third reading
Unit 36 is taken, is connected to the second reading unit 34, for regular according to predetermined reading, respectively from the caching of storage twiddle factor
Twiddle factor corresponding with per pending data stream all the way is read in space；First arithmetic element 37, it is single to be connected to the 3rd reading
Member 36, for carrying out complex multiplication operation per pending data stream all the way and corresponding twiddle factor, Bing Duigai to be treated on road
Processing data stream and complex multiplication operation result carry out complex addition operations, obtain interative computation result, wherein, twiddle factor is
WN -n, n span is（0, N-1）；Second arithmetic element 38, the first arithmetic element 37 is connected to, for interative computation knot
Fruit exports after carrying out successive ignition computing, wherein, the number of interative computation is determined by band width configuration.
Certainly in actual applications, inverse fast fourier transform realization device can also use following building form.
For example, refer to Figure 10, Figure 10 is the inverse fast fourier transform reality according to another preferred embodiment of the present invention
The structural representation of existing device, as shown in Figure 10, the preferred embodiment mainly includes：Multiple antennas carrier wave maps and multiplexing process list
Member, IFFT processing units, multiply iterative processing unit again.The function of unit is introduced below：
Multiple antennas carrier wave maps and multiplexing process unit：According to configured bandwidth information, to the multiple antennas of front-end module input
Data flow, calculated using different read/write address and redirect rule, the hand-off process between data flow is completed when reading data,
The multi-antenna data time-division merges into a data flow, serial to be sent into rear class IFFT processing.
IFFT processing units：According to system type, can choose whether to carry out antenna calibration operation.It is corrected weights
Read/write address controls, and the multiplication for completing multiple antennas weights and data flow operates.Data to completing IFFT processing, use configuration
The power control factor enters the processing of Mobile state cut position.
Multiply iterative processing unit again：Indicated according to the valid data that are exported from IFFT processing units, produce address of cache and
Switching law.Meanwhile according to twiddle factor and the corresponding relation of data flow, the reading of one side control data stream and redirect, separately
On the one hand the reading address of twiddle factor look-up table, the output of controlling elements are controlled.Carry out the multiple stage circulation of data and twiddle factor
Iteration multiply-add operation, while the calibration of output data is controlled, avoid overflowing.
The inverse fast fourier transform realization device provided using above-described embodiment, is solved the various bandwidth of LTE system and mixed
The problem of closing flexible configuration, while avoided performance loss and the full complicated algorithm for decomposing IFFT that interpolating operations are brought, so as to
Reach that reduction processing delay is low, improves flexible structure autgmentability, the effects of the flexible and changeable networking requirements of operator can be met
Fruit.
As can be seen from the above description, the present invention realizes following technique effect：Solve the various bands of LTE system
The problem of width mixing flexible configuration, while avoided performance loss and the full complicated algorithm for decomposing IFFT that interpolating operations are brought.
The occupancy of fpga chip resource is not only reduced, processing delay is low, and flexible structure autgmentability is high, can meet operator's spirit
Changeable networking requirements living, improve product competitiveness.
Obviously, those skilled in the art should be understood that above-mentioned each module of the invention or each step can be with general
Computing device realize that they can be concentrated on single computing device, or be distributed in multiple computing devices and formed
Network on, alternatively, they can be realized with the program code that computing device can perform, it is thus possible to they are stored
Performed in the storage device by computing device, and in some cases, can be with different from shown in order execution herein
The step of going out or describing, they are either fabricated to each integrated circuit modules respectively or by multiple modules in them or
Step is fabricated to single integrated circuit module to realize.So, the present invention is not restricted to any specific hardware and software combination.
The preferred embodiments of the present invention are the foregoing is only, are not intended to limit the invention, for the skill of this area
For art personnel, the present invention can have various modifications and variations.Within the spirit and principles of the invention, that is made any repaiies
Change, equivalent substitution, improvement etc., should be included in the scope of the protection.
Claims (10)
- A kind of 1. inverse fast fourier transform implementation method, it is characterised in that including：The multi-antenna data stream of input is received, the multi-antenna data stream is merged into the first data flow；Multiplication operation is carried out to first data flow according to multiple antenna weights of acquisition, obtains the second data flow, and to institute State the second data flow and carry out inverse fast fourier transform IFFT processing, obtain the 3rd data flow, wherein, each antenna is corresponding one Antenna weights；Exported after carrying out multiple stage circulation iteration multiply-add operation to the 3rd data flow according to the twiddle factor prestored, its In, the twiddle factor supports various bandwidth configuration.
- 2. according to the method for claim 1, it is characterised in that the multi-antenna data stream is merged into the first data flow, Including：The P point multi-antenna data streams of input are received, the P point multi-antenna datas stream is extracted and is mapped as M circuit-switched data streams；For each circuit-switched data stream, redirected according to predetermined address after rule reads P/2M data, insertion Q individual 0 is followed by resuming studies Remaining P/2M data are taken, when being finished to the reading of each circuit-switched data stream, obtain N number of data flow, wherein, N=P+M*Q；By N number of data stream merging it is first data flow according to antenna order.
- 3. according to the method for claim 2, it is characterised in that obtain the multiple antenna weights in the following manner：Judge system type, when the system type is TDD, acquisition system obtains after carrying out antenna calibration operation N number of antenna weights, when the system type is FDD, N number of antenna weights are set as 1.
- 4. according to the method for claim 3, it is characterised in that according to multiple antenna weights of acquisition to first data Stream carries out multiplication operation, obtains second data flow, and carry out inverse fast fourier transform IFFT to second data flow Processing, obtains the 3rd data flow, including：Multiplication operation is carried out to N number of antenna weights and first data flow, obtains second data flow；M IFFT processing is carried out to second data flow, the amplitude of the data flow after IFFT processing is without departing from amplitude thresholds In the case of, the data flow after IFFT is handled surpasses as the 3rd data flow, the amplitude of the data flow after IFFT processing In the case of going out the amplitude thresholds, cut position is carried out to the data flow after IFFT processing according to the power control factor being pre-configured with Processing, obtains the 3rd data flow.
- 5. method according to any one of claim 1 to 4, it is characterised in that according to the twiddle factor pair prestored 3rd data flow exports after carrying out multiple stage circulation iteration multiply-add operation, including：3rd data flow is respectively written into M different cachings, obtains M pending data stream；Rule is redirected according to address, is read respectively per pending data stream described all the way in the caching different from the M；According to predetermined reading rule, read respectively from the spatial cache for storing the twiddle factor with per all the way it is described treat from Manage twiddle factor corresponding to data flow；Complex multiplication operation, Bing Duigai roads are carried out to every pending data stream described all the way and the corresponding twiddle factor Pending data stream and complex multiplication operation result carry out complex addition operations, obtain interative computation result, wherein, the rotation The factor is WN -n, n span is (0, N-1)；Exported after carrying out successive ignition computing to the interative computation result, wherein, the number of the interative computation is by the band Width configuration determines.
- A kind of 6. inverse fast fourier transform realization device, it is characterised in that including：Merging module, for receiving the multi-antenna data stream of input, the multi-antenna data stream is merged into the first data flow；First processing module, multiplication operation is carried out to first data flow for multiple antenna weights according to acquisition, obtained Second data flow, and inverse fast fourier transform IFFT processing is carried out to second data flow, the 3rd data flow is obtained, its In, the corresponding antenna weights of each antenna；Second processing module, multiply for carrying out multiple stage circulation iteration to the 3rd data flow according to the twiddle factor prestored Exported after adding computing, wherein, the twiddle factor supports various bandwidth configuration.
- 7. device according to claim 6, it is characterised in that the merging module includes：Map unit, for receiving the P point multi-antenna data streams of input, the P point multi-antenna datas stream is extracted and is mapped as M roads Data flow；First reading unit, for for each circuit-switched data stream, redirected according to predetermined address after rule reads P/2M data, Insertion is further continued for reading remaining P/2M data for Q 0, when being finished to the reading of each circuit-switched data stream, obtains N number of data flow, Wherein, N=P+M*Q；Combining unit, for by N number of data stream merging being first data flow according to antenna order.
- 8. device according to claim 7, it is characterised in that the first processing module includes：Judging unit, for judging system type；Acquiring unit, for when the system type is TDD, acquisition system to obtain after carrying out antenna calibration operation N number of antenna weights；Setup unit, for when the system type is FDD, N number of antenna weights to be set as into 1.
- 9. device according to claim 8, it is characterised in that the first processing module also includes：Computing unit, for carrying out multiplication operation to N number of antenna weights and first data flow, obtain second number According to stream；Processing unit, to second data flow carry out M IFFT processing, IFFT handle after data flow amplitude without departing from In the case of amplitude thresholds, the data flow after IFFT is handled is as the 3rd data flow, the data flow after IFFT processing Amplitude exceed the amplitude thresholds in the case of, according to the power control factor being pre-configured with to IFFT processing after data flow Cut position processing is carried out, obtains the 3rd data flow.
- 10. the device according to any one of claim 6 to 9, it is characterised in that the Second processing module includes：Memory cell, for the 3rd data flow to be stored in into M different cachings respectively, obtain M pending data stream；Second reading unit, for redirecting rule according to address, read respectively per described all the way in the caching different from the M Pending data stream；3rd reading unit, for according to predetermined reading rule, being read respectively from the spatial cache for storing the twiddle factor Take twiddle factor corresponding with per pending data stream described all the way；First arithmetic element, for carrying out plural number to every pending data stream described all the way and the corresponding twiddle factor Multiplying, Bing Duigai roads pending data stream and complex multiplication operation result carry out complex addition operations, obtain interative computation As a result, wherein, the twiddle factor is WN -n, n span is (0, N-1)；Second arithmetic element, for being exported after carrying out successive ignition computing to the interative computation result, wherein, the iteration fortune The number of calculation is determined by the band width configuration.
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