CN103489399B - Electroluminescent pixel circuit - Google Patents
Electroluminescent pixel circuit Download PDFInfo
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- CN103489399B CN103489399B CN201310339702.8A CN201310339702A CN103489399B CN 103489399 B CN103489399 B CN 103489399B CN 201310339702 A CN201310339702 A CN 201310339702A CN 103489399 B CN103489399 B CN 103489399B
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- 239000013078 crystal Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 21
- 230000000630 rising effect Effects 0.000 description 10
- 238000005401 electroluminescence Methods 0.000 description 8
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- 230000003139 buffering effect Effects 0.000 description 4
- CVOFKRWYWCSDMA-UHFFFAOYSA-N 2-chloro-n-(2,6-diethylphenyl)-n-(methoxymethyl)acetamide;2,6-dinitro-n,n-dipropyl-4-(trifluoromethyl)aniline Chemical compound CCC1=CC=CC(CC)=C1N(COC)C(=O)CCl.CCCN(CCC)C1=C([N+]([O-])=O)C=C(C(F)(F)F)C=C1[N+]([O-])=O CVOFKRWYWCSDMA-UHFFFAOYSA-N 0.000 description 2
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Abstract
The invention discloses an electroluminescent pixel circuit, which comprises an organic light-emitting diode, a compensation unit and a switch transistor. The cathode terminal of the organic light emitting diode is electrically connected to the first voltage source. The compensation unit is electrically connected to the second voltage source and is used for receiving the control signal, the first scanning signal and the second scanning signal, wherein the pulse enabling period of the first scanning signal and the pulse enabling period of the second scanning signal are within the pulse enabling period of the control signal, and the pulse enabling period of the first scanning signal is before the pulse enabling period of the second scanning signal. The switch transistor has a first end, a second end and a gate end, wherein the two ends of the switch transistor are electrically connected between the compensation unit and the anode end of the organic light emitting diode and are turned on according to the control signal.
Description
Technical field
The invention relates to the technical field of organic light-emitting diode display, and relate to a kind of el pixel circuit of organic light emitting diode display especially.
Background technology
Please refer to Fig. 1, it is the schematic diagram of traditional OLED (Organic Light Emitting Diode, OLED) el pixel circuit.This kind of el pixel circuit 100 includes driving transistors 102, switching transistor 104, electric capacity 106 and Organic Light Emitting Diode 110.The first end of driving transistors 102 is electrically connected to voltage source OVDD.The gate terminal of switching transistor 104 receives sweep signal SCAN because of electrical connection, and the first end of switching transistor 104 receives data voltage Vdata because of electrical connection, the second end is then electrically connected to the gate terminal of driving transistors 102.Between the gate terminal that the two ends of electric capacity 106 are connected across driving transistors 102 and first end.The anode tap of Organic Light Emitting Diode 110 is electrically connected to the second end of driving transistors 102, and cathode terminal is then electrically connected to another voltage source OVSS.Aforementioned dot structure produces pixel current I according to the potential difference (PD) Vsg of the first end of driving transistors 102 and gate terminal
oleddrive Organic Light Emitting Diode 110 shinny, the pixel current flowing through Organic Light Emitting Diode 110 is I
oled=K* (V
sg-| V
tH|)
2.K is constant, V
sgsize be relevant to the size of voltage source OVDD and data voltage Vdata, VTH is the critical voltage of driving transistors 102.
Due to the impact of manufacturing process, the critical voltage VTH of the driving transistors 102 of each pixel is all not identical, causes having pixel current I between organic light emitting diode display interior pixels and pixel
oleddifference, electric current its brightness produced different making to flow through each Organic Light Emitting Diode OLED will be different, thus cause the problem that Display panel is uneven.
Summary of the invention
The present invention proposes a kind of el pixel circuit, includes OLED, compensating unit and switching transistor.Organic Light Emitting Diode has anode tap and cathode terminal, and the cathode terminal of Organic Light Emitting Diode is electrically connected to the first voltage source.Compensating unit is electrically connected to the second voltage source, and in order to reception control signal, the first sweep signal and the second sweep signal, during the pulse activation of wherein the first sweep signal and the second sweep signal all during the pulse activation of control signal in, and during the pulse activation of the first sweep signal during the pulse activation of the second sweep signal before.Switching transistor has first end, the second end and gate terminal, two ends of switching transistor are electrically connected between compensating unit and the anode tap of Organic Light Emitting Diode, and according to control signal actuating switch transistor, wherein the first voltage source and the second voltage source are all fixed voltage, and the accurate position in contrast to the second voltage source, the position of the first voltage source is accurate.
The present invention reintroduces a kind of el pixel circuit, includes OLED, switching transistor, the first transistor, transistor seconds, third transistor, the 4th transistor, the 5th transistor and the first electric capacity.Wherein, Organic Light Emitting Diode has anode tap and cathode terminal, and the cathode terminal of Organic Light Emitting Diode is electrically connected to the first voltage source.Switching transistor has first end, the second end and gate terminal, and the second end of switching transistor is electrically connected to the anode tap of Organic Light Emitting Diode, and the gate terminal of switching transistor is then in order to reception control signal, and foundation control signal actuating switch transistor.The first transistor has first end, the second end and gate terminal, and wherein the first end of the first transistor is electrically connected to the second voltage source, and the gate terminal of the first transistor is then in order to reception control signal.Transistor seconds has first end, the second end and gate terminal, and wherein the first end of transistor seconds is electrically connected to the second end of the first transistor, and the second end of transistor seconds is electrically connected to the first end of switching transistor.Third transistor has first end, the second end and gate terminal, wherein the first end of third transistor is in order to receive data voltage, second end of third transistor is electrically connected to the first end of transistor seconds, and the gate terminal of third transistor is then in order to receive the second sweep signal.4th transistor has first end, the second end and gate terminal, wherein the first end of the 4th transistor is electrically connected to the second end of transistor seconds, second end of the 4th transistor is electrically connected to the gate terminal of transistor seconds, and the gate terminal of the 4th transistor is then in order to receive the second sweep signal.5th transistor has first end, the second end and gate terminal, and the first end of the 5th transistor and the gate terminal of the 5th transistor are all electrically connected to the second voltage source, and the second end of the 5th transistor is electrically connected to the gate terminal of transistor seconds.First electric capacity, wherein one end of the first electric capacity is in order to receive the first sweep signal, and the other end of the first electric capacity is then electrically connected to the gate terminal of transistor seconds.
The present invention proposes again a kind of el pixel circuit, and it comprises light-emitting component, switching transistor, the first transistor, transistor seconds, third transistor, the 4th transistor, the 5th transistor, the first electric capacity and the second electric capacity.Light-emitting component has anode tap and cathode terminal, and the cathode terminal of light-emitting component is electrically connected to the first voltage source.Switching transistor, switching transistor has first end, the second end and gate terminal, and the second end of switching transistor is electrically connected to the anode tap of light-emitting component, and the gate terminal of switching transistor is then in order to reception control signal.The first transistor has first end, the second end and gate terminal, and the first end of the first transistor is electrically connected to the second voltage source, and the gate terminal of the first transistor is then in order to reception control signal.Transistor seconds has first end, the second end and gate terminal, and the first end of transistor seconds is electrically connected to the second end of the first transistor, and the second end of transistor seconds is then electrically connected to the first end of switching transistor.Third transistor has first end, the second end and gate terminal, the first end of third transistor is electrically connected to the second end of transistor seconds, second end of third transistor is electrically connected to the gate terminal of transistor seconds, and the gate terminal of third transistor is then in order to receive the first sweep signal.4th transistor has first end, the second end and gate terminal, the first end of the 4th transistor is in order to receive data voltage, second end of the 4th transistor is electrically connected to the gate terminal of transistor seconds, and the gate terminal of the 4th transistor is then in order to receive the 3rd sweep signal.5th transistor has first end, the second end and gate terminal, the first end of the 5th transistor is electrically connected to the second voltage source, second end of the 5th transistor is electrically connected to the second end of transistor seconds, and the gate terminal of the 5th transistor is then in order to receive the first sweep signal.First electric capacity is electrically connected between the gate terminal of transistor seconds and the first end of transistor seconds.Second electric capacity is electrically connected between the first end of transistor seconds and the second sweep signal.
For above and other object of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and coordinate accompanying drawing, be described in detail below.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of existing el pixel circuit.
Fig. 2 is the schematic diagram of the el pixel circuit according to one embodiment of the invention.
Fig. 3 is the schematic diagram of the compensating unit inside according to one embodiment of the invention.
Fig. 4 is the sequential chart of the part signal of el pixel circuit shown in Fig. 3.
Fig. 5 is the schematic diagram of another compensating unit of el pixel circuit inside according to one embodiment of the invention.
Fig. 6 is the schematic diagram of a compensating unit again of el pixel circuit inside according to one embodiment of the invention.
Fig. 7 is the schematic diagram of the el pixel circuit according to another embodiment of the present invention.
Fig. 8 is the schematic diagram of the compensating unit inside according to another embodiment of the present invention.
Fig. 9 is the sequential chart of the part signal of el pixel circuit shown in Fig. 8.
Figure 10 is the schematic diagram of the el pixel circuit according to one embodiment of the invention.
Figure 11 is the sequential chart of the part signal of el pixel circuit shown in Figure 10.
Figure 12 is the schematic diagram of the el pixel circuit according to another embodiment of the present invention.
Figure 13 is the schematic diagram of the el pixel circuit according to another embodiment of the present invention.
Figure 14 is the sequential chart of the part signal of el pixel circuit shown in Figure 13.
Wherein, Reference numeral:
100,200,300,500,600,700,800: el pixel circuit
102: driving transistors
104,220,720,1002,1302: switching transistor
106,316,517,617,816, C1, C2: electric capacity
110,230,730: Organic Light Emitting Diode
OVDD, OVSS, Vref: voltage source
SCAN: sweep signal
Vdata: data voltage
I
oled: pixel current
210,310,510,610,710,810: compensating unit
EM: control signal
S1: the first sweep signal
S2: the second sweep signal
S3: the three sweep signal
311,811,1003,1303: the first transistor
312,812,1004,1304: transistor seconds
313,813,1005,1305: third transistor
314,814,1006,1306: the four transistors
315,615,815,1007,1207,1307: the five transistors
A: node
V
a: the current potential of node A
T1 ~ T5: time
1000,1200,1300: el pixel circuit
1001,1301: light-emitting component
Embodiment
Fig. 2 is the schematic diagram of the el pixel circuit according to one embodiment of the invention.El pixel circuit 200 includes compensating unit 210, switching transistor 220 and Organic Light Emitting Diode 230.Wherein, Organic Light Emitting Diode 230 has anode tap and cathode terminal, and the cathode terminal of Organic Light Emitting Diode 230 is electrically connected to voltage source OVSS.Compensating unit 210 is electrically connected to another voltage source OVDD, and because of electrical connection reception control signal EM, the first sweep signal S1 and the second sweep signal S2, during the pulse activation of wherein the first sweep signal S1 and the second sweep signal S2 all during the pulse activation of control signal EM in, and during the pulse activation of the first sweep signal S1 during the pulse activation of the second sweep signal S2 before.Switching transistor 220 has first end, the second end and gate terminal, and the two ends of switching transistor 220 are electrically connected between the anode tap of compensating unit 210 and Organic Light Emitting Diode 230, and according to control signal EM actuating switch transistor 220.Above-mentioned voltage source OVSS and OVDD is all fixed voltage, and the accurate position in contrast to voltage source OVDD, the position of voltage source OVSS is accurate, and voltage source OVSS is such as-4.4 volts, and voltage source OVDD is such as+4.6 volts.
Specifically, please refer to Fig. 3, it is the schematic diagram of compensating unit inside.In figure 3, indicate person identical with the sign in Fig. 2 and be expressed as identical element, voltage source or signal.Compensating unit 310 shown in Fig. 3 includes the first transistor 311, transistor seconds 312 (following alleged transistor seconds is driving transistors), third transistor 313, the 4th transistor 314, the 5th transistor 315 and electric capacity 316, and wherein the first transistor all has first end, the second end and gate terminal to the 5th transistor 311 ~ 315.The first end of the first transistor 311 is electrically connected to voltage source OVDD, the gate terminal then reception control signal EM because of electrical connection of the first transistor 311.The first end of transistor seconds 312 is electrically connected to the second end of the first transistor 311, and the second end of transistor seconds 312 is electrically connected to the first end of switching transistor 220.The first end of third transistor 313 receives data voltage Vdata because of electrical connection, and the second end of third transistor 313 is electrically connected to the first end of transistor seconds 312, the gate terminal of third transistor 313 then receives the second sweep signal S2 because of electrical connection.The first end of the 4th transistor 314 is electrically connected to the second end of transistor seconds 312, and the second end of the 4th transistor 314 is electrically connected to the gate terminal of transistor seconds 312, the gate terminal of the 4th transistor 314 then receives the second sweep signal S2 because of electrical connection.First end and the gate terminal of the 5th transistor 315 are all electrically connected to voltage source OVDD, and the second end of the 4th transistor 314 is then electrically connected to the gate terminal of transistor seconds 312.One end of electric capacity 316 receives the first sweep signal S1 because of electrical connection, the other end of electric capacity 316 is then electrically connected to the gate terminal of transistor seconds 312.
In the present embodiment, the first transistor 311, transistor seconds 312, third transistor 313, the 4th transistor 314, the 5th transistor 315 can be all PMOS transistor with switching transistor 220.Below just for PMOS transistor, describe the sequential of the first sweep signal S1 in Fig. 3, the second sweep signal S2 and control signal EM.
Fig. 4 is the sequential chart of the part signal of el pixel circuit shown in Fig. 3.In the diagram, indicate person identical with the sign in Fig. 3 and be expressed as identical signal, and indicate the current potential that VA is the node A shown in Fig. 3.Can learn from Fig. 4, in during time T1 ~ T5, during the pulse activation of the first sweep signal S1 and the second sweep signal S2 all during the pulse activation of control signal EM in, and during the pulse activation of the first sweep signal S1 during the pulse activation of the second sweep signal S2 before.Wherein, in time T1 and time T5, being used for interval time of the rising edge of control signal EM and the rising edge of the first sweep signal S1 buffering first sweep signal S1 is pulled up to time needed for high levels by low level, then being used for interval time of the falling edge of control signal EM and the rising edge of the second sweep signal S2 buffering second sweep signal S2 is pulled up to time needed for high levels by low level, thus, during the pulse activation of the first sweep signal S1 and the second sweep signal S2 can be guaranteed all during the pulse activation of control signal EM within.
Although, in the present embodiment, the falling edge of the first sweep signal S1 and the falling edge of the second sweep signal S2 all have the relation overlapped each other, but in certain embodiments, the falling edge of the first sweep signal S1 and the falling edge of the second sweep signal S2 also can non-superposed relationship each other.That is, after the first sweep signal S1 is low level by high levels transition, it is low level state that the second sweep signal S2 just starts by high levels transition.Therefore, whether the overlapping of the falling edge of the first sweep signal S1 and the falling edge of the second sweep signal S2, during only wanting the pulse activation of the first sweep signal S1 and the second sweep signal S2 all during the pulse activation of control signal EM within, el pixel circuit normal operation can be made, all can realize the present invention.And above listed by the signal enumerated implement pattern, be only for example purposes, the present invention is not limited according to this.
The driving process of el pixel circuit 300 is described in detail below in conjunction with Fig. 3 and Fig. 4, and the driving process of el pixel circuit 300 of the present invention mainly includes operational phase, write and compensating operation stage and the light emission operation stage of resetting, in during dropping on time T2, time T3 and time T5 respectively.
Specifically, el pixel circuit 300 replacement operational phase T2 during in, control signal EM, the first sweep signal S1 and the second sweep signal S2 all present high levels state, make the 5th transistor 315 be conducting state, and the first transistor 311, transistor seconds 312, third transistor 313, the 4th transistor 314 and switching transistor 220 are all in closed condition.Now, voltage source OVDD is just provided to through the 5th transistor 315 of conducting the current potential V that electric capacity 316 makes node A
afor OVDD+|V
tH|.
Then in during write and compensating operation stage T3, first sweep signal S1 and the second sweep signal S2 all presents low level state, control signal EM then presents high levels state, make third transistor 313 and the 4th transistor 314 be all conducting state, and the first transistor 311, the 5th transistor 315 are all in closed condition with switching transistor 220.Now, because the current potential of node A can come high than the current potential of the first end of transistor seconds 312, therefore transistor seconds 312 also can be in closed condition.And the electric charge be stored in electric capacity 316 can be released, in time gradually then as the current potential V of node A originally
adrop to and compare Vdata-|V
tH| during also low current potential, transistor seconds 312 just can be switched on.
Now, be all conducting state at transistor seconds 312, third transistor 313 and the 4th transistor 314, and the first transistor 311, the 5th transistor 315 are when being all in closed condition with switching transistor 220, the value of data voltage Vdata is just provided to through the transistor seconds 312 of conducting, third transistor 313 and the 4th transistor 314 the current potential V that electric capacity 316 makes node A
amaintain Vdata-|V
tH| position accurate.
In finally during light emission operation stage T5, first sweep signal S1 and control signal EM all presents low level state, second sweep signal S2 then presents high levels state, make the first transistor 311, transistor seconds 312 be all conducting state with switching transistor 220, and third transistor 313, the 4th transistor 314 and the 5th transistor 315 are all in closed condition.Thus, transistor seconds 312 (i.e. driving transistors) just can according to the potential difference (PD) V on now its first end and its gate terminal
sgproduce pixel current I
oleddrive Organic Light Emitting Diode 230 shinny.
Hold above-mentioned, flow through the pixel current I of Organic Light Emitting Diode 230
oled=K* (V
sg-| V
tH|)
2.Now, the potential difference (PD) V in the first end of transistor seconds 312 and gate terminal
sgbe respectively the current potential Vdata-|V of voltage source OVDD and node A
tH|, therefore the pixel current flowing through Organic Light Emitting Diode 230 is I
oled=K*{ [OVDD-(Vdata-|V
tH|)]-| V
tH|
2=K* (OVDD – Vdata)
2.Can learn thus, in during light emission operation stage T5, flow through the pixel current I of Organic Light Emitting Diode 230
oledonly relevant with data voltage Vdata with voltage source OVDD, and with the critical voltage V of transistor seconds 312 (i.e. driving transistors)
tHcompletely irrelevant.Thus, the uneven problem of the Display panel that the processing procedure of Organic Light Emitting Diode causes the impact of the critical voltage of driving transistors can effectively be improved, thus organic light emitting diode display can be compensated critical voltage when display frame, and still can keep preferably display quality under long-time use.
In addition, in certain embodiments, the compensating unit of el pixel circuit inside of the present invention also can do a little improvement, respectively it is described with Fig. 5 and Fig. 6.Fig. 5 is the schematic diagram of another compensating unit according to el pixel circuit inside of the present invention.In Figure 5, indicate person identical with the sign in Fig. 3 and be expressed as identical object, voltage source or signal.The compensating unit 510 of the el pixel circuit 500 shown in Fig. 5 and the difference of the compensating unit 310 of the el pixel circuit 300 shown in Fig. 3, be that the compensating unit 510 of this el pixel circuit 500 inside also comprises electric capacity 517, between its second end being electrically connected at the 4th transistor 314 and gate terminal.
Fig. 6 is then the schematic diagram according to the compensating unit of an el pixel circuit inside more of the present invention.In figure 6, indicate person identical with the sign in Fig. 3 and be expressed as identical object, voltage source or signal.The compensating unit 610 of the el pixel circuit 600 shown in Fig. 6 and the difference of the compensating unit 310 of the el pixel circuit 300 shown in Fig. 3, be that the compensating unit 610 of this el pixel circuit 600 inside also comprises electric capacity 617, the first end of electric capacity 617 can be electrically connected to voltage source OVDD or voltage source V ref, and the second end of electric capacity 617 is then electrically connected to wherein one end of electric capacity 316.In addition, first end and the gate terminal of the 5th transistor the 615, five transistor 615 of compensating unit 610 inside all can be electrically connected to voltage source V ref, and the second end of the 5th transistor 615 is then electrically connected to the gate terminal of transistor seconds 312.In the present embodiment, voltage source OVSS, OVDD and Vref are all fixed voltage, and the accurate position in contrast to voltage source OVDD, the position of voltage source OVSS is accurate, and the position that the position of voltage source V ref standard is more than or equal to voltage source OVDD is accurate.Above-mentioned voltage source OVSS is such as-4.4 volts, and voltage source OVDD is such as+4.6 volts, and voltage source V ref is more than or equal to+4.6 volts.The driving process of these two kinds of el pixel circuits 500 and 600 above, those skilled in the art can push away it from the sequential content described by Fig. 4, is therefore no longer repeated.
Fig. 7 is the schematic diagram of the el pixel circuit according to another embodiment of the present invention.This el pixel circuit 700 comprises compensating unit 710, switching transistor 720 and Organic Light Emitting Diode 730.Wherein, Organic Light Emitting Diode 730 has anode tap and cathode terminal, and the anode tap of Organic Light Emitting Diode 730 is electrically connected to voltage source OVDD.Compensating unit 710 is electrically connected to another voltage source OVSS, and because of electrical connection reception control signal EM, the first sweep signal S1 and the second sweep signal S2, during the pulse activation of wherein the first sweep signal S1 and the second sweep signal S2 all during the pulse activation of control signal EM in, and during the pulse activation of the first sweep signal S1 during the pulse activation of the second sweep signal S2 before (describing in detail afterwards).Switching transistor 720 has first end, the second end and gate terminal, and the two ends of switching transistor 720 are electrically connected between the cathode terminal of compensating unit 710 and Organic Light Emitting Diode 730, and according to control signal EM actuating switch transistor 720.Above-mentioned voltage source OVDD and OVSS is all fixed voltage, and the accurate position in contrast to voltage source OVSS, the position of voltage source OVDD is accurate, and voltage source OVDD is such as+4.6 volts, and voltage source OVSS is such as-4.4 volts.
Specifically, please refer to Fig. 8, it is the schematic diagram of compensating unit inside.In fig. 8, indicate person identical with the sign in Fig. 7 and be expressed as identical object, voltage source or signal.Compensating unit 810 shown in Fig. 8 includes the first transistor 811, transistor seconds 812 (i.e. driving transistors), third transistor 813, the 4th transistor 814, the 5th transistor 815 and electric capacity 816, and wherein the first transistor all has first end, the second end and gate terminal to the 5th transistor 811 ~ 815.The first end of the first transistor 811 is electrically connected to the second voltage source OVSS, the gate terminal then reception control signal EM because of electrical connection of the first transistor 811.The first end of transistor seconds 812 is electrically connected to the second end of the first transistor 811, and the second end of transistor seconds 812 is electrically connected to the first end of switching transistor 720.The first end of third transistor 813 receives data voltage Vdata because of electrical connection, and the second end of third transistor 813 is electrically connected to the first end of transistor seconds 812, the gate terminal of third transistor 813 then receives the second sweep signal S2 because of electrical connection.The first end of the 4th transistor 814 is electrically connected to the second end of transistor seconds 812, and the second end of the 4th transistor 814 is electrically connected to the gate terminal of transistor seconds 812, the gate terminal of the 4th transistor 814 then receives the second sweep signal S2 because of electrical connection.First end and the gate terminal of the 5th transistor 815 are all electrically connected to voltage source OVSS, and the second end of the 5th transistor 815 is electrically connected to the gate terminal of transistor seconds 812.One end of electric capacity 816 receives the first sweep signal S1 because of electrical connection, the other end of electric capacity 816 is then electrically connected to the gate terminal of transistor seconds 812.
In the present embodiment, the first transistor 811, transistor seconds 812, third transistor 813, the 4th transistor 814, the 5th transistor 815 all adopt nmos pass transistor to realize with switching transistor 720.Below just for nmos pass transistor, describe the sequential of the first sweep signal S1 in Fig. 8, the second sweep signal S2 and control signal EM.
Fig. 9 is the sequential chart of the part signal of el pixel circuit shown in Fig. 8.In fig .9, indicate person identical with the sign in Fig. 8 and be expressed as identical signal, and indicate V
abe the current potential of the node A shown in Fig. 8.Can learn from Fig. 9, in during time T1 ~ T5, during the pulse activation of the first sweep signal S1 and the second sweep signal S2 all during the pulse activation of control signal EM in, and during the pulse activation of the first sweep signal S1 during the pulse activation of the second sweep signal S2 before.Wherein, in time T1 and time T5, be used to interval time of the falling edge of control signal EM and the falling edge of the first sweep signal S1 buffering first sweep signal S1 and reduce to time needed for low level by high levels, then be used to interval time of the rising edge of control signal EM and the falling edge of the second sweep signal S2 buffering second sweep signal S2 and reduce to time needed for low level by high levels, thus, during the pulse activation of the first sweep signal S1 and the second sweep signal S2 can be guaranteed all during the pulse activation of control signal EM within.
Although, in the present embodiment, the rising edge of the first sweep signal S1 and the rising edge of the second sweep signal S2 all have the relation overlapped each other, but in certain embodiments, the rising edge of the first sweep signal S1 and the rising edge of the second sweep signal S2 also can non-superposed relationship each other.That is, after the first sweep signal S1 is high levels by low level transition, it is high levels state that the second sweep signal S2 just starts by low level transition.Therefore, whether the overlapping of the rising edge of the first sweep signal S1 and the rising edge of the second sweep signal S2, during only wanting the pulse activation of the first sweep signal S1 and the second sweep signal S2 all during the pulse activation of control signal EM within, el pixel circuit normal operation can be made, all can realize the present invention.And above listed by the signal enumerated implement pattern, be only for example purposes, the present invention is not limited according to this.
Referring again to Fig. 9, this area has knows that the knowledgeable can from the sequential content described by the el pixel circuit 300 of previous embodiment usually, and the sequential of the first sweep signal S1 illustrated according to Fig. 9, the second sweep signal S2 and control signal EM pushes away to obtain the driving process of el pixel circuit 800 of Fig. 8, therefore just no longer repeated.
Figure 10 is the schematic diagram of the el pixel circuit according to one embodiment of the invention.This el pixel circuit 1000 mainly formed with light-emitting component 1001, switching transistor 1002, the first transistor 1003, transistor seconds 1004, third transistor 1005, the 4th transistor 1006, the 5th transistor 1007, electric capacity C1 and electric capacity C2.As shown in the figure, the cathode terminal of light-emitting component 1001 is electrically connected to voltage source OVSS.Second end of switching transistor 1002 is electrically connected to the anode tap of light-emitting component 1001, and the gate terminal of switching transistor 1002 is in order to reception control signal EM.The first end of the first transistor 1003 is electrically connected to voltage source OVDD, and the gate terminal of the first transistor 1003 is then in order to reception control signal EM.The first end of transistor seconds 1004 is electrically connected to the second end of the first transistor 1003, and the second end of transistor seconds 1004 is electrically connected to the first end of switching transistor 1002.The first end of third transistor 1005 is electrically connected to the second end of transistor seconds 1004, and the second end of third transistor 1005 is electrically connected to the gate terminal of transistor seconds 1004, and the gate terminal of third transistor 1005 is in order to receive the first sweep signal S1.The first end of the 4th transistor 1006 is in order to receive data voltage Vdata, and the second end of the 4th transistor 1006 is electrically connected to the gate terminal of transistor seconds 1004, and the gate terminal of the 4th transistor 1006 is then in order to receive the 3rd sweep signal S3.The first end of the 5th transistor 1007 is electrically connected to voltage source OVDD, and the second end of the 5th transistor 1007 is electrically connected to the second end of transistor seconds 1004, and the gate terminal of the 5th transistor 1007 is then in order to receive the first sweep signal S1.Electric capacity C1 is electrically connected between the gate terminal of transistor seconds 1004 and the first end of transistor seconds 1004.Electric capacity C2 is electrically connected between the first end of transistor seconds 1004 and the second sweep signal S2.Above-mentioned voltage source OVDD and OVSS is all fixed voltage, and the accurate position in contrast to voltage source OVSS, the position of voltage source OVDD is accurate, and voltage source OVDD is such as+4.6 volts, and voltage source OVSS is such as-4.4 volts.In addition, the light-emitting component 1001 in this embodiment realizes with Organic Light Emitting Diode.
In the present embodiment, switching transistor 1002, the first transistor 1003, transistor seconds 1004, third transistor 1005, the 4th transistor 1006 and the 5th transistor 1007 all adopt PMOS transistor to realize.Below just for PMOS transistor, describe the sequential of the first sweep signal S1 in Figure 10, the second sweep signal S2, the 3rd sweep signal S3 and control signal EM.
Figure 11 is the sequential chart of the part signal of el pixel circuit shown in Figure 10.As shown in the figure, be expressed as the replacement of el pixel circuit at time T1 ~ T4 during, between the amortization period, between data address period and light emission period.First sweep signal S1 during resetting (i.e. time T1) and between the amortization period (i.e. time T2) be positioned at first standard, the first sweep signal S1 (i.e. time T4) between data address period (i.e. time T3) and light emission period is positioned at second standard.Second sweep signal S2 (i.e. time T1) during resetting is positioned at first standard, and the second sweep signal S2 is accurate to second by first accurate transition during (i.e. time T2) initial between the amortization period.3rd sweep signal S3 during resetting between (i.e. time T1), amortization period between (i.e. time T2) and light emission period (i.e. time T4) be positioned at second standard, the 3rd sweep signal S3 is positioned at first standard in data address period (i.e. time T3).Control signal EM is positioned at second standard time (i.e. time T2) and data address period (i.e. time T3) between (i.e. time T1), amortization period during resetting, and control signal EM is positioned at first standard time (i.e. time T4) between light emission period.In this embodiment, first described standard is logic low level state, and described second criterion is the accurate state of logic high.
Specifically, when el pixel circuit 1000 is during resetting time (i.e. time T1), first sweep signal S1 and the second sweep signal S2 all presents logic low level state, and the 3rd sweep signal S3 and control signal EM all presents the accurate state of logic high, make switching transistor 1002, the first transistor 1003, transistor seconds 1004 and the 4th transistor 1006 all be in closed condition, and third transistor 1005 and the 5th transistor 1007 are all in opening.Now, voltage source OVDD is just provided to the third transistor 1005 of conducting the current potential about slightly DVDD that electric capacity C1 makes node A through the 5th transistor 1007 of conducting.
Then, when el pixel circuit 1000 is between the amortization period time (i.e. time T2), first sweep signal S1 presents logic low level state, and the second sweep signal S2, the 3rd sweep signal S3 and control signal EM all present the accurate state of logic high, make switching transistor 1002, the first transistor 1003 and the 4th transistor 1006 all be in closed condition, and transistor seconds 1004, third transistor 1005 and the 5th transistor 1007 are all in opening.Now, the current potential about slightly DVDD of node A, and the current potential of the first end of transistor seconds 1004 about slightly DVDD+|V
tH|, therefore when the current potential of node A comes low compared to the current potential of the first end of transistor seconds 1004, transistor seconds 1004 is in opening.When el pixel circuit 1000 is when data address period (i.e. time T3), first sweep signal S1, the second sweep signal S2 and control signal EM all present the accurate state of logic high, 3rd sweep signal S3 then presents logic low level state, make switching transistor 1002, the first transistor 1003, third transistor 1005 and the 5th transistor 1007 all be in closed condition, and transistor seconds 1004 and the 4th transistor 1006 are all in opening.Now, the data voltage Vdata that the first end of the current potential of node A about slightly the 4th transistor 1006 receives, the current potential then rough DVDD+|V of the first end of transistor seconds 1004
tH|+α (Vdata-DVDD).Wherein, α is the ratio between two electric capacity C1 and C2, is
Finally, when el pixel circuit 1000 is between light emission period time (i.e. time T4), first sweep signal S1, the second sweep signal S2 and the 3rd sweep signal S3 all present the accurate state of logic high, control signal EM then presents logic low level state, make switching transistor 1002, the first transistor 1003 and transistor seconds 1004 all be in opening, and third transistor 1005, the 4th transistor 1006 and the 5th transistor 1007 are all in closed condition.Now, the current potential of the current potential about slightly OVDD of the first end of transistor seconds 1004, node A then about slightly Vdata-|V
tH|+α (DVDD-Vdata).So, transistor seconds 1004 just can produce pixel current I according to the potential difference (PD) on its first end and its gate terminal
oleddrive light-emitting component 1001 shinny.
Hold above-mentioned, flow through the pixel current I of light-emitting component 1001
oled=1/2*K* (V
sg-| V
tH|)
2.Now, the potential difference (PD) V in the first end of transistor seconds 1004 and gate terminal
sgbe respectively the current potential Vdata-|V of voltage source OVDD and node A
tH|+α (DVDD-Vdata), therefore the pixel current flowing through light-emitting component 1001 is I
oled=1/2*K*{OVDD-[Vdata-|V
tH|+α (DVDD-Vdata)]-| V
tH|
2=1/2*K* [(1-α) * (OVDD – Vdata)]
2.Can learn thus, flow through the pixel current I of light-emitting component 1001
oledonly relevant with data voltage Vdata with voltage source OVDD, and with the critical voltage V of transistor seconds 1004 (i.e. driving transistors)
tHirrelevant.Thus, the uneven problem of the Display panel that the processing procedure of described light-emitting component causes the impact of the critical voltage of driving transistors can effectively be improved, thus the electroluminescence display pixel of this embodiment can be compensated critical voltage when display frame, and still can keep preferably display quality under long-time use.
In addition, in certain embodiments, above-mentioned electroluminescence display pixel also can make a little improvement, with Figure 12, it is described.Figure 12 is the schematic diagram of the el pixel circuit according to another embodiment of the present invention.In fig. 12, indicate person identical with the sign in Figure 10 and be expressed as identical element, voltage source or signal.The difference of the electroluminescence display pixel 1200 shown in Figure 12 and the electroluminescence display pixel 1000 shown in Figure 10, be that the first end of the 5th transistor 1207 in electroluminescence display pixel 1200 is electrically connected to voltage source OVDD, the second end of the 5th transistor 1207 is then electrically connected to the first end of third transistor 1005.As for the detailed driving process of this kind of electroluminescence display pixel 1200, those of ordinary skill in the art can push away it from the sequential content described by Figure 11, therefore repeats no more.
Figure 13 is the schematic diagram of the el pixel circuit according to another embodiment of the present invention.El pixel circuit 1300 shown in Figure 13 and the difference of the electroluminescence display pixel 1000 shown in Figure 10, be that el pixel circuit 1300 mainly formed with light-emitting component 1301, switching transistor 1302, the first transistor 1303, transistor seconds 1304, third transistor 1305, the 4th transistor 1306 and the 5th transistor 1307.Wherein, these transistors all adopt nmos pass transistor to realize.As shown in the figure, the anode tap of light-emitting component 1301 is electrically connected to voltage source OVDD.The first end of switching transistor 1302 is electrically connected to the cathode terminal of light-emitting component 1301, and the gate terminal of switching transistor 1302 is then in order to reception control signal EM.Second end of the first transistor 1303 is electrically connected to voltage source OVSS, and the gate terminal of the first transistor 1303 is then in order to reception control signal EM.The first end of transistor seconds 1304 is electrically connected to the second end of switching transistor 1302, and the second end of transistor seconds 1304 is then electrically connected to the first end of the first transistor 1303.The first end of third transistor 1305 is electrically connected to the second end of transistor seconds 1304, second end of third transistor 1305 is electrically connected to the gate terminal of transistor seconds 1304, and the gate terminal of third transistor 1305 is then in order to receive the first sweep signal S1.The first end of the 4th transistor 1306 is in order to receive data voltage Vdata, and the second end of the 4th transistor 1306 is electrically connected to the gate terminal of transistor seconds 1304, and the gate terminal of the 4th transistor 1306 is then in order to receive the 3rd sweep signal S3.The first end of the 5th transistor 1307 is electrically connected to voltage source OVSS, and the second end of the 5th transistor 1307 is electrically connected to the second end of transistor seconds 1004, and the gate terminal of the 5th transistor 1307 is then in order to receive the first sweep signal S1.Electric capacity C1 is electrically connected between the gate terminal of transistor seconds 1304 and the first end of transistor seconds 1304.Electric capacity C2 is electrically connected between the first end of transistor seconds 1304 and the second sweep signal S2.Above-mentioned voltage source OVDD and OVSS is all fixed voltage, and the accurate position in contrast to voltage source OVSS, the position of voltage source OVDD is accurate, and voltage source OVDD is such as+4.6 volts, and voltage source OVSS is such as-4.4 volts.In addition, the light-emitting component 1301 in this embodiment realizes with Organic Light Emitting Diode.
Figure 14 is the sequential chart of the part signal of el pixel circuit shown in Figure 13.As shown in the figure, be expressed as the replacement of el pixel circuit at time T1 ~ T4 during, between the amortization period, between data address period and light emission period.First sweep signal S1 during resetting (i.e. time T1) and between the amortization period (i.e. time T2) be positioned at first standard, the first sweep signal S1 (i.e. time T4) between data address period (i.e. time T3) and light emission period is positioned at second standard.Second sweep signal S2 (i.e. time T1) during resetting is positioned at first standard, and the second sweep signal S2 is accurate to second by first accurate transition during (i.e. time T2) initial between the amortization period.3rd sweep signal S3 during resetting between (i.e. time T1), amortization period between (i.e. time T2) and light emission period (i.e. time T4) be positioned at second standard, the 3rd sweep signal S3 is positioned at first standard in data address period (i.e. time T3).Control signal EM is positioned at second standard time (i.e. time T2) and data address period (i.e. time T3) between (i.e. time T1), amortization period during resetting, and control signal EM is positioned at first standard time (i.e. time T4) between light emission period.In this embodiment, first described standard is the accurate state of logic high, and described second criterion is logic low level state.As for the detailed driving process of this kind of electroluminescence display pixel 1300, those skilled in the art can push away it from the sequential content described by Figure 11, therefore repeats no more.
In sum, the present invention solves the major way of foregoing problems, be by designing el pixel circuit structure, the size flowing through Organic Light Emitting Diode or the pixel current of light-emitting component can be made to be relevant to voltage source and data voltage, and completely irrelevant with the critical voltage of driving transistors.Therefore, the el pixel circuit that the embodiment of the present invention proposes effectively can improve the uneven problem of Display panel, to provide high-quality display frame, and then reaches object of the present invention.
Although the present invention with preferred embodiment openly as above; but it is also not used to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when doing a little change and amendment, therefore protection scope of the present invention is when being as the criterion depending on accompanying claims protection domain person of defining.
Claims (10)
1. an el pixel circuit, is characterized in that, comprising:
One Organic Light Emitting Diode, has an anode tap and a cathode terminal, and this cathode terminal of this Organic Light Emitting Diode is electrically connected to one first voltage source;
One compensating unit, be electrically connected to one second voltage source, and in order to receive a control signal, one first sweep signal and one second sweep signal, during the pulse activation of this first sweep signal and this second sweep signal neither during the pulse activation of this control signal in, and during the pulse activation of this first sweep signal during the pulse activation of this second sweep signal before; And
One switching transistor, this switching transistor has a first end, one second end and a gate terminal, two ends of this switching transistor are electrically connected between this anode tap of this compensating unit and this Organic Light Emitting Diode, and according to this this switching transistor of control signal conducting, wherein this first voltage source and this second voltage source are all fixed voltage, and the accurate position in contrast to this second voltage source, the position of this first voltage source is accurate;
Wherein, this compensating unit includes:
One the first transistor, this first transistor has a first end, one second end and a gate terminal, and this first end of this first transistor is electrically connected to this second voltage source, and this gate terminal of this first transistor is then in order to receive this control signal;
One transistor seconds, this transistor seconds has a first end, one second end and a gate terminal, this first end of this transistor seconds is electrically connected to this second end of this first transistor, and this second end of this transistor seconds is electrically connected to this first end of this switching transistor;
One third transistor, this third transistor has a first end, one second end and a gate terminal, this first end of this third transistor is in order to receive a data voltage, this second end of this third transistor is electrically connected to this first end of this transistor seconds, and this gate terminal of this third transistor is then in order to receive this second sweep signal;
One the 4th transistor, 4th transistor has a first end, one second end and a gate terminal, this first end of 4th transistor is electrically connected to this second end of this transistor seconds, this second end of 4th transistor is electrically connected to this gate terminal of this transistor seconds, and this gate terminal of the 4th transistor is then in order to receive this second sweep signal;
One the 5th transistor, 5th transistor has a first end, one second end and a gate terminal, this first end of 5th transistor and this gate terminal are all electrically connected to this second voltage source, and this second end of the 5th transistor is electrically connected to this gate terminal of this transistor seconds; And
One first electric capacity, wherein one end of this first electric capacity is in order to receive this first sweep signal, and the other end is then electrically connected to this gate terminal of this transistor seconds.
2. el pixel circuit as claimed in claim 1, it is characterized in that, this first transistor, this transistor seconds, this third transistor, the 4th transistor, the 5th this switching transistor of transistor AND gate are all identical kenel.
3. el pixel circuit as claimed in claim 1, it is characterized in that, this compensating unit also includes one second electric capacity, and this second electric capacity is electrically connected between this second end and this gate terminal of the 4th transistor.
4. el pixel circuit as claimed in claim 1, it is characterized in that, in during a first stage, this control signal, this first sweep signal and this second sweep signal have one first standard, in during a subordinate phase, it is accurate that this first sweep signal and this second sweep signal have a second, this control signal then has this first standard, in during a phase III, it is accurate that this first sweep signal and this second sweep signal have this second, this control signal is then this first standard, this first accurate polarity is in contrast to the polarity of this second standard.
5. an el pixel circuit, is characterized in that, comprising:
One Organic Light Emitting Diode, has an anode tap and a cathode terminal, and this cathode terminal of this Organic Light Emitting Diode is electrically connected to one first voltage source;
One switching transistor, this switching transistor has a first end, one second end and a gate terminal, this second end of this switching transistor is electrically connected to this anode tap of this Organic Light Emitting Diode, this gate terminal of this switching transistor then in order to receive a control signal, and according to this this switching transistor of control signal conducting;
One the first transistor, this first transistor has a first end, one second end and a gate terminal, and wherein this first end of this first transistor is electrically connected to one second voltage source, and this gate terminal of this first transistor is then in order to receive this control signal;
One transistor seconds, this transistor seconds has a first end, one second end and a gate terminal, wherein this first end of this transistor seconds is electrically connected to this second end of this first transistor, and this second end of this transistor seconds is electrically connected to this first end of this switching transistor;
One third transistor, this third transistor has a first end, one second end and a gate terminal, wherein this first end of this third transistor is in order to receive a data voltage, this second end of this third transistor is electrically connected to this first end of this transistor seconds, and this gate terminal of this third transistor is then in order to receive one second sweep signal;
One the 4th transistor, 4th transistor has a first end, one second end and a gate terminal, wherein this first end of the 4th transistor is electrically connected to this second end of this transistor seconds, this second end of 4th transistor is electrically connected to this gate terminal of this transistor seconds, and this gate terminal of the 4th transistor is then in order to receive this second sweep signal;
One the 5th transistor, 5th transistor has a first end, one second end and a gate terminal, this first end of 5th transistor and this gate terminal of the 5th transistor are all electrically connected to this second voltage source, and this second end of the 5th transistor is electrically connected to this gate terminal of this transistor seconds; And
One first electric capacity, wherein one end of this first electric capacity is in order to receive one first sweep signal, and the other end of this first electric capacity is then electrically connected to this gate terminal of this transistor seconds.
6. el pixel circuit as claimed in claim 5, it is characterized in that, also include one second electric capacity, this second electric capacity is electrically connected between this second end and this gate terminal of the 4th transistor.
7. an el pixel circuit, is characterized in that, comprising:
One light-emitting component, has an anode tap and a cathode terminal, and this cathode terminal of this light-emitting component is electrically connected to one first voltage source;
One switching transistor, this switching transistor has a first end, one second end and a gate terminal, and this second end of this switching transistor is electrically connected to this anode tap of this light-emitting component, and this gate terminal of this switching transistor is then in order to receive a control signal;
One the first transistor, this first transistor has a first end, one second end and a gate terminal, and this first end of this first transistor is electrically connected to one second voltage source, and this gate terminal of this first transistor is then in order to receive this control signal;
One transistor seconds, this transistor seconds has a first end, one second end and a gate terminal, this first end of this transistor seconds is electrically connected to this second end of this first transistor, and this second end of this transistor seconds is then electrically connected to this first end of this switching transistor;
One third transistor, this third transistor has a first end, one second end and a gate terminal, this first end of this third transistor is electrically connected to this second end of this transistor seconds, this second end of this third transistor is electrically connected to this gate terminal of this transistor seconds, and this gate terminal of this third transistor is then in order to receive one first sweep signal;
One the 4th transistor, 4th transistor has a first end, one second end and a gate terminal, this first end of 4th transistor is in order to receive a data voltage, this second end of 4th transistor is electrically connected to this gate terminal of this transistor seconds, and this gate terminal of the 4th transistor is then in order to receive one the 3rd sweep signal;
One the 5th transistor, 5th transistor has a first end, one second end and a gate terminal, this first end of 5th transistor is electrically connected to this second voltage source, this second end of 5th transistor is electrically connected to this second end of this transistor seconds, and this gate terminal of the 5th transistor is then in order to receive this first sweep signal;
One first electric capacity, this first electric capacity is electrically connected between this gate terminal of this transistor seconds and this first end of this transistor seconds; And
One second electric capacity, this second electric capacity is electrically connected between this first end of this transistor seconds and one second sweep signal.
8. el pixel circuit as claimed in claim 7, it is characterized in that, this first transistor, this transistor seconds, this third transistor, the 4th transistor, the 5th this switching transistor of transistor AND gate are all isomrophous crystal pipe.
9. el pixel circuit as claimed in claim 7, it is characterized in that, this first voltage source and this second voltage source are all fixed voltage, and the accurate position in contrast to this second voltage source, the position of this first voltage source is accurate.
10. el pixel circuit as claimed in claim 7, it is characterized in that, during separately comprising a replacement, between one amortization period, one data address period, and one between light emission period, wherein this first sweep signal is positioned at one first standard during this replacement and between this amortization period, and it is accurate that this first sweep signal is positioned at a second between this data address period and this light emission period;
This second sweep signal is positioned at this first standard during this replacement, accurate to this second by this first accurate transition during initial between this amortization period of this second sweep signal;
It is accurate that 3rd sweep signal is positioned at this second during this replacement, between this amortization period and between this light emission period, and the 3rd sweep signal is positioned at this first standard in this data address period; And
This control signal during this replacement, between this amortization period and this data address periods time to be positioned at this second accurate, be positioned at this first standard when this control signal is between this light emission period.
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| TW102125567 | 2013-07-17 | ||
| TW102125567A TWI492206B (en) | 2012-11-21 | 2013-07-17 | Electroluminescence display pixel circuit |
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| TWI514352B (en) * | 2014-05-20 | 2015-12-21 | Au Optronics Corp | Pixel driving circuit for organic light emitting diode display and operating method thereof |
| TWI515712B (en) * | 2014-05-28 | 2016-01-01 | 友達光電股份有限公司 | Pixel driving circuit |
| TWI539422B (en) | 2014-09-15 | 2016-06-21 | 友達光電股份有限公司 | Pixel architechture and driving method thereof |
| US10431142B2 (en) * | 2016-11-14 | 2019-10-01 | Int Tech Co., Ltd. | Pixel circuit and electroluminescent display comprising the pixel circuit |
| CN115019729B (en) * | 2022-08-04 | 2022-11-25 | 惠科股份有限公司 | Pixel driving circuit, display panel and control method thereof |
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