CN103488605A - Bus architecture for multiprocessor parallel communication - Google Patents
Bus architecture for multiprocessor parallel communication Download PDFInfo
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- CN103488605A CN103488605A CN201310438349.9A CN201310438349A CN103488605A CN 103488605 A CN103488605 A CN 103488605A CN 201310438349 A CN201310438349 A CN 201310438349A CN 103488605 A CN103488605 A CN 103488605A
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Abstract
The invention relates to a bus architecture for multiprocessor parallel communication. The bus architecture for the multiprocessor parallel communication comprises a communication bus communicated with central processing unit (CPU) plugins, wherein the communication bus comprises M serial channels, each CPU plugin is provided with at least M communication interfaces, and the communication interfaces of the CPU plugins are connected with the serial channels in a one-to-one correspondence mode. The bus architecture adopts a total-exchange serial bus which is substantially of a multiple-transmitting-receiving-node serial bus structure and used for multiprocessor data exchange. Therefore, the communication problem of an arbitrary number of slot position processors is solved, meanwhile the communication efficiency of the processors is improved, and multi-task and multiple-CPU parallel processing application with high real-timeliness requirement is met. The bus architecture for the multiprocessor parallel communication has good continuity and forward compatibility technically, subsequent investment in research and development can be saved, only CPU and backboards are locally required to be changed, other types of IO plugins are not required to be changed, and therefore the investment benefit can be maximized.
Description
Technical field
The present invention relates to a kind of bus architecture of parallel multiprocessor communication.
Background technology
Controlling protecting platform is the nucleus equipment of HVDC Converter Stations secondary side, is the nerve center of direct-current power transmission control protection system.In high voltage direct current transmission project, control protecting platform and be applied to many occasions such as station control, utmost point control, the control of valve group, alternating current-direct current protection.Summing up its common feature, is all the parallel processing application of multiprocessor, in a cabinet according to the complexity of application, configure some CPU, each CPU combines with corresponding peripheral I/O plug-in unit, finally forms a plurality of processing set with specific function.But in traditional design, in a cabinet, all CPU and peripheral plug-in units all are inserted on (sharing) parallel bus back board, like this, in cabinet, any one CPU need to be used bus resource when (as accessed its attached peripheral plug-in unit or accessing other cpu data), will take to exclusiveness core bus, communication between CPU not only needs the shared drive board, and the bus collision situation is arranged, and other CPU card task associated with bus access will be affected.
Summary of the invention
The bus architecture that the purpose of this invention is to provide a kind of parallel multiprocessor communication, to solve the Communication between each CPU in existing multiprocessors parallel processing application.
For achieving the above object, the bus architecture technical scheme of parallel multiprocessor communication of the present invention is as follows:
Comprise and the communication bus of CPU card communication, communication bus comprises M bar serial-port, and each CPU card is provided with at least M communication interface, and each communication interface and each serial-port of each CPU card connect one to one, and M is more than or equal to 2 natural number.
One of them communication interface of described each CPU card is transmission interface, and other communication interfaces are receiving interface; The transmission interface of each CPU card is corresponding one by one with each serial-port.
Described CPU card arranges the priority level of each receiving cable by communication interface.
The bus architecture of parallel multiprocessor communication of the present invention, adopt full duplex exchange universal serial bus, this bus essence is many transmitting-receiving nodes serial bus structure, for exchanges data between multiprocessor, so both solved the problem of mutual communication between any groove bit processor, also improved the communication efficiency between processor, the more much higher task of requirement of real time, many CPU parallel processing application simultaneously; Technical have preferably a continuity and compatible forward, can save follow-up investment in research and development, only needs local change CPU and backboard, and other various types of IO plug-in units, without change, can make returns of investment maximize like this.
The accompanying drawing explanation
Fig. 1 is many transmitting-receiving nodes serial bus technology principle schematic;
Fig. 2 is the structural representation of embodiment mono-;
Fig. 3 is the structural representation of embodiment bis-.
Embodiment
One, embodiment mono-
Universal serial bus: along with the raising of parallel bus speed, the problem of line-to-line crosstalk is just outstanding all the more.In recent years, follow the development of high speed serial communication technology, by the highest 10M of early stage RS485, till now LVDS approach 2G, serial communication speed has had very large lifting, serial communication bus is also given birth to because of gesture.
The universal serial bus of the bus architecture of this parallel multiprocessor communication adopts many transmitting-receiving nodes serial bus technology, can realize receiving 1 more, and flank speed can reach 500Mbps.In this structure, a plurality of transceivers can be connected on the same bus, as shown in Figure 1, can control reiving/transmitting state by controlling transmit-receive position, therefore allow the bi-directional half-duplex communication.
The bus architecture of parallel multiprocessor communication, communication bus comprises M bar serial-port, and each CPU card is provided with at least M communication interface, and each communication interface and each serial-port of each CPU card connect one to one, and M is more than or equal to 2 natural number.One of them communication interface of each CPU card is transmission interface, and other communication interfaces are receiving interface; The transmission interface of each CPU card is corresponding one by one with each serial-port, and M, N are the natural number that is more than or equal to 2.Corresponding communication bus refers to that each CPU card monopolizes a communication bus and send information, and the connection that receiving cable is corresponding is connected to and will receives reception information on the communication bus that CPU card monopolizes.
As shown in Figure 2,4 CPU are arranged, and M=4, N=3, on whole 21 groove backboards, it is serial communication bus that 21 serial-ports are arranged.The CPU of each groove position can be connected to the sendaisle of oneself on corresponding serial-port.As the CPU of the 1st groove position is connected to the 1st serial-port by sendaisle, the CPU of the 17th groove position is connected to the 17th serial-port by sendaisle.For receiving cable, the CPU of each groove position can receive other serial-port except self slot number.As the CPU of the first groove position can receive 2-21 bar serial-port, the CPU of the 17th groove position can receive 1-16 bar and 18-21 bar serial-port.Because the CPU of each groove position monopolizes a sendaisle, so belong to " full duplex " communication modes for the many transmitting-receiving nodes universal serial bus on this backboard.So more improved the real-time of data.This is a kind of full exchange connection mode of simplification, and the CPU on any groove position can send data in real time, is not subject to the impact of bus arbitration, directly data is sent on purpose CPU.
For CPU card, the transceiver of 21 universal serial bus is arranged on each CPU, according to groove position information, the transceiver that this CPU arranges respective number is sending mode.According to receiving needs, the transceiver that other respective number is set is receiving mode in addition.As 1 groove CPU wants simultaneously and 3 grooves, 7 grooves, 13 groove CPU communications, 3 groove CPU also will with No. 1, No. 7, No. 13 CPU communications.So for the CPU of 1 groove position.No. 1 transceiver that the CPU of No. 1 groove position is set is sending mode; It is receiving mode that 3,7, No. 13 transceivers are set simultaneously.In like manner, to 3 groove CPU, it is sending mode that No. 3 transceivers are set, and No. 1, No. 7, No. 13 transceivers are receiving mode (receiving the information of the CPU of 1 groove, 7 grooves and 13 grooves).In like manner 7 groove CPU and 13 groove CPU also have similar setting.
Issue of priority about CPU inside: go up 1 groove CPU shown in Fig. 2, receive the data of 3,7,13 groove bit CPUs simultaneously.Under default situations, the data of 3,7, the 13 grooves level that has that All factors being equal, preference will be give to, for 1 groove CPU, be exactly the first-in first-out principle.If there is special requirement also priority can be set, if 1 groove CPU is subject to the cpu data of 3,7 groove positions simultaneously, and 7 groove priority are the highest, and the data of 7 groove CPU will preferentially be transmitted so.
Two, embodiment bis-
As shown in Figure 3, in order further to alleviate bus contention, at the bus architecture of the parallel multiprocessor communication shown in Fig. 2, arrange on the basis of many universal serial bus, also be provided with parallel bus, this parallel bus, for the parallel N cross-talk bus arranged, is connected with at least one CPU card on every cross-talk bus.
By tradition, shared parallel bus carries out segmentation (being divided into 3 sections), in each section, is all the parallel bus back board structure of a set of complete function, forms the multibus framework of sectional type from the angle of all-in-onecase.
In the application of HVDC (High Voltage Direct Current) transmission system, the situation that is less than or equal to 3 CPU in cabinet is the most common.If so a high speed parallel bus is divided into to 3 sections buses arranged side by side, by meeting most application needs, can certainly increase the spare bus, during in order to multiprocessor more, use.On physics, former parallel bus is segmented into to a plurality of primary and secondary lines, every cross-talk bus is all identical with former parallel bus aspect transmission data, principle, be that each section in the N section is all the parallel bus structure of a set of complete function, form the multibus framework of sectional type from the angle of all-in-onecase.
Many parallel buss (more available resources are provided) are provided, and the single common bus competition by a cabinet scope, be converted into the bus contention in segmentation.Because the CPU quantity in segmentation reduces, the load condition of segmentation internal bus improves; And minute intersegmental separate, be independent of each other, thereby on the whole, be compared to traditional single parallel bus structure, the sectional type multibus significantly weakens the competition bottleneck of bus resource.
The configuration optimization that the sectional type multiple bus architecture is direct current transportation application function in a cabinet provides more reasonably and has selected.As: the communication task with field layer equipment, operation monitoring layer equipment can be processed to set (usually by a processor card, two field bus communication plug-in units, two Ethernet plug-in units compositions) and be configured in a bus sectionalization.This application communication data volume is larger, and processes by a CPU is unified.Can, so that the processing of communication task can not be subject to because of bus contention the impact of other CPU, the task in other CPU not impacted so simultaneously yet.
After bus sectionalization, the situation of many CPU competition bus is significantly alleviated, in the situation that be less than or equal to 3 CPU, eliminated the bus contention situation, and on the core bus terminal, designed a kind of full exchange universal serial bus, well solved the Communication between a plurality of CPU.
The bus architecture of this parallel multiprocessor communication has following advantage:
1) although VXS, VPX technology have solved the competition bottleneck of parallel backboard relatively, improved the throughput of many CPU access, realize that cost is very high, be not suitable for the such batch commercial Application of similar DC transmission engineering.
2) well solved the throughput bottleneck between the many CPU access of platform under the parallel core bus structure of standard.Both solve bus conflict, solved again the rapid communication problem between many CPU.The more much higher task of requirement of real time, many CPU parallel processing application.
3) technical have preferably a continuity and compatible forward, can save follow-up investment in research and development, only needs local change CPU and backboard, and other various types of IO plug-in units are without change.Can make like this returns of investment maximize.
4) reduced the shared drive board, also to reducing costs contribution to some extent.
It should be noted last that: above embodiment is the non-limiting technical scheme of the present invention in order to explanation only, although with reference to above-described embodiment, the present invention is had been described in detail, those of ordinary skill in the art is to be understood that; Still can modify or be equal to replacement the present invention, and not break away from any modification or partial replacement of the spirit and scope of the present invention, it all should be encompassed in the middle of claim scope of the present invention.
Claims (3)
1. the bus architecture of parallel multiprocessor communication, it is characterized in that: comprise the communication bus with the CPU card communication, communication bus comprises M bar serial-port, each CPU card is provided with at least M communication interface, each communication interface and each serial-port of each CPU card connect one to one, and M is more than or equal to 2 natural number.
2. the bus architecture of parallel multiprocessor communication according to claim 1, it is characterized in that: one of them communication interface of described each CPU card is transmission interface, other communication interfaces are receiving interface; The transmission interface of each CPU card is corresponding one by one with each serial-port.
3. the bus architecture of parallel multiprocessor communication according to claim 1 and 2, it is characterized in that: described CPU card arranges the priority level of each receiving cable by communication interface.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104572514A (en) * | 2015-01-20 | 2015-04-29 | 浪潮电子信息产业股份有限公司 | Globally shared I/O (input/output) server design method |
| CN108614528A (en) * | 2016-12-13 | 2018-10-02 | 中核控制系统工程有限公司 | A kind of safety level multibus collaboration working method |
| CN111865551A (en) * | 2020-07-13 | 2020-10-30 | 国电南瑞科技股份有限公司 | Device and method for coordinated management of multistage system based on fast bus |
| CN112732348A (en) * | 2020-12-30 | 2021-04-30 | 浙江大华技术股份有限公司 | Service processing method and device of multi-node all-in-one machine |
| CN115756824A (en) * | 2022-10-21 | 2023-03-07 | 超聚变数字技术有限公司 | Out-of-band query/configuration method for processor information in server and server |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104572514A (en) * | 2015-01-20 | 2015-04-29 | 浪潮电子信息产业股份有限公司 | Globally shared I/O (input/output) server design method |
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| CN111865551A (en) * | 2020-07-13 | 2020-10-30 | 国电南瑞科技股份有限公司 | Device and method for coordinated management of multistage system based on fast bus |
| CN111865551B (en) * | 2020-07-13 | 2022-11-11 | 国电南瑞科技股份有限公司 | Device and method for coordinated management of multistage system based on fast bus |
| CN112732348A (en) * | 2020-12-30 | 2021-04-30 | 浙江大华技术股份有限公司 | Service processing method and device of multi-node all-in-one machine |
| CN115756824A (en) * | 2022-10-21 | 2023-03-07 | 超聚变数字技术有限公司 | Out-of-band query/configuration method for processor information in server and server |
| CN115756824B (en) * | 2022-10-21 | 2023-11-03 | 超聚变数字技术有限公司 | Out-of-band query/configuration method of processor information in server and server |
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