CN103475344B - A kind of phase demodulating, frequency doubling logic circuit with the anti-mechanism of makeing mistakes - Google Patents
A kind of phase demodulating, frequency doubling logic circuit with the anti-mechanism of makeing mistakes Download PDFInfo
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- CN103475344B CN103475344B CN201310444979.7A CN201310444979A CN103475344B CN 103475344 B CN103475344 B CN 103475344B CN 201310444979 A CN201310444979 A CN 201310444979A CN 103475344 B CN103475344 B CN 103475344B
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Abstract
The invention discloses a kind of phase demodulating, frequency doubling logic circuit with the anti-mechanism of makeing mistakes, including phase demodulating, frequency doubling module, phase discrimination signal filtration module and frequency-doubled signal conditioning module, phase demodulating, frequency doubling module includes five d type flip flops, three XOR gates, a not gate；Phase discrimination signal filtration module includes three d type flip flops, three NAND gate, an XOR gate, and the input of this module receives initial phase discrimination signal, clock signal and reset signal respectively, exports phase discrimination signal；Frequency-doubled signal conditioning module includes six d type flip flops, and the input of this module receives initial frequency-doubled signal, clock signal and reset signal respectively, exports frequency-doubled signal.The present invention inputs as phase discrimination signal clock after reverse for initial frequency-doubled signal, effectively solves d type flip flop erroneous trigger problem；Phase demodulating, frequency doubling module basis combines filtration module and conditioning module, the problem of incorrect output when efficiently solving signal burr, time delay and the not actuated circuit caused after accurate signal passes through phase demodulating, frequency doubling module.
Description
Technical field
The present invention relates to the phase demodulating, frequency doubling logic electricity in a kind of direct current generator feedback system field based on data acquisition process
Road.
Background technology
In the feedback control system detection of direct current generator, often by photoelectric encoder detection direct current generator rotating speed and
Direction.When motor rotates, grating disc rotates with motor simultaneously, photoelectric encoder detection output pulse signal, is processed by calculating
Pulse signal just can obtain rotating speed and the direction of motor.Precision is the highest, and acquisition number of pulses per second is the most.Photoelectric encoder can be answered
For the feedback control of multiple motor, such as brshless DC motor (BLDC), switched reluctance machines (SRD), AC induction motor
(ACIM) etc..Typical incremental optical-electricity encoder is generally by light source (transmitter module), code-disc, grating (detection module) and conversion
Circuit forms, and provides A phase, B phase and the output of C phase (origin pulse) three tunnel.By the logic circuit output to photoelectric encoder
Pulse is decoded, and can obtain the movable information of motor, including rotating speed and direction.Wherein, the phase relation between A phase and B phase
Can uniquely determine the direction of motion of motor.If A advanced B phase, then the direction of motion of motor is forward.If the advanced A of B phase
Phase, then the direction of motion of motor is reverse.C phase is origin pulse, and motor every revolution produces a pulse, makes as benchmark
With.
Photoelectric encoder there will be some sound pollutions very the most unavoidably as a kind of high-precision detecting element, output signal
To time delay, this situation has had a strong impact on the accuracy of step-by-step counting, thus affects the control accuracy of whole control system.
Therefore in detection design process, often add signal filtering and phase demodulating, frequency doubling circuit is eliminated the effects of the act, improve essence simultaneously
Degree.But have ignored basic phase demodulating, frequency doubling logic and time identical, reach special circumstances and the essence of rising edge in clock signal with A, B
Accurate A, B phase easily produces signal burr, time delay and the output of not actuated circuit error by basic phase demodulating, frequency doubling circuit
Problem.And, use hardware circuit often to produce new interference factor, and it is the strongest to take circuit board space, motility.
Therefore, it is necessary to design the modified model phase demodulating, frequency doubling logic electricity of a kind of anti-mechanism of makeing mistakes of the band that can accurately export
Road.
Summary of the invention
The technical problem to be solved is, not enough for prior art, it is provided that a kind of mirror with the anti-mechanism of makeing mistakes
Phase frequency multiplication logic circuit, solves the accurate signal ignored of available circuit and can produce noise and delay, not through basic phase demodulation module
The problem of incorrect output during start-up circuit.
For solving above-mentioned technical problem, the technical solution adopted in the present invention is: a kind of phase demodulation times with the anti-mechanism of makeing mistakes
Frequently logic circuit, including phase demodulating, frequency doubling module, described phase demodulating, frequency doubling module includes five d type flip flops, not gate, three XOR gates,
The input input external signal of the first d type flip flop and the second d type flip flop, wherein four d flip-flop and the 5th d type flip flop time
Clock input termination external timing signal, the enable input of five d type flip flops all connects outside enable signal；First d type flip flop is defeated
Going out end to be connected with 3d flip-flop input, 3d flip-flop outfan and one input of the second XOR gate connect；Described
Another input of second XOR gate and the second d type flip flop outfan connect；First d type flip flop, the second d type flip flop and the 3rd D
The input end of clock equal NAND gate outfan of trigger connects；Described external signal inputs two inputs of the first XOR gate,
The input of described first XOR gate outfan and an input of the 3rd XOR gate, four d flip-flop connects；Described 3rd
Another input of XOR gate and the 5th d type flip flop outfan connect；Described 5th d type flip flop input and the 4th D trigger
Device outfan connects；
Described phase demodulating, frequency doubling module connects phase discrimination signal filtration module and frequency-doubled signal conditioning module；Described frequency-doubled signal
Conditioning module includes 3～8 d type flip flops being sequentially connected with, described non-gate output terminal, the 3rd XOR gate outfan and described frequency multiplication
First d type flip flop input of Signal-regulated kinase connects, all d type flip flops in described frequency-doubled signal conditioning module time
Clock input is all connected with external timing signal, the enable input of all d type flip flops in described frequency-doubled signal conditioning module
All enable signal with outside to be connected；
Described phase discrimination signal filtration module includes three d type flip flops, three NAND gate and the 4th XOR gate, described second different
Or gate output terminal is connected with first d type flip flop input of described phase discrimination signal filtration module, described phase discrimination signal filtering mould
Three d type flip flop input end of clock of block are all connected with external timing signal, and three D of described phase discrimination signal filtration module trigger
Device enables input and is all connected with outside enable signal；3rd d type flip flop outfan of described phase discrimination signal filtration module with
Second NAND gate one input connects, and described another input of second NAND gate is with described 4th XOR gate outfan even
Connecing, described two inputs of 4th XOR gate, two inputs of the first NAND gate are in parallel respectively accesses the filter of described phase discrimination signal
Between two d type flip flops that mode block is adjacent；Described first NAND gate outfan, the second NAND gate outfan with the respectively the 3rd with
Two inputs of not gate connect.
Described frequency-doubled signal conditioning module includes six d type flip flops.
Compared with prior art, the had the beneficial effect that present invention of the present invention has the anti-mechanism of makeing mistakes of d type flip flop,
Through sending into non-behind the door as the input end of clock of d type flip flop using initial phase discrimination signal, can effectively prevent d type flip flop clock from believing
Number with D input A, B phase signals produce conflict, prevent d type flip flop latch signal from makeing mistakes；The present invention has phase discrimination signal filtering merit
Can, eliminate the noise in initial phase discrimination signal and correction through three d type flip flops, an XOR gate and three NAND gate effects
Its time delay.Signal sends into second d type flip flop after first d type flip flop, and second d type flip flop output signal is sent into
3rd d type flip flop, meanwhile, first d type flip flop output signal is simultaneously fed into XOR gate with second d type flip flop output signal
With first NAND gate, the 3rd d type flip flop output signal and XOR gate output signal send into second NAND gate, first with
Not gate output signal and second NAND gate output signal send into the 3rd NAND gate, obtain final phase discrimination signal.I.e. signal is at D
The effect of trigger delay action and XOR gate, NAND gate is lower to be eliminated the noise in initial phase discrimination signal and revises delay, effectively
Solve the problem that the accurate signal that current techniques ignores can produce noise and delay through basic phase demodulation module；The present invention has
Frequency-doubled signal conditioning functions, filters the inaccurate signal in initial frequency-doubled signal through six d type flip flop effects.Signal passes through
First d type flip flop sends into second d type flip flop, and the output signal of second d type flip flop sends into the 3rd d type flip flop, and the 3rd
The output signal of individual d type flip flop sends into the 4th d type flip flop, and the output signal of the 4th d type flip flop is sent into the 5th D and triggered
Device, the output signal of the 5th d type flip flop is sent into the 6th d type flip flop, is obtained final frequency-doubled signal.I.e. signal is at d type flip flop
Eliminate incorrect output and conditioning pulse signal when reset signal is under delay action, efficiently solve what current techniques was ignored
Precisely signal can produce delay and the problem of not actuated circuit error output through basic times of frequency module；The present invention is by phase demodulating, frequency doubling
Combining with filtering modulate circuit, system accuracy is high, and circuit is simple and reliable, can effectively solve basic phase demodulating, frequency doubling logic circuit
Reach, in clock signal, the d type flip flop that the special circumstances of rising edge cause time identical with A, B and trigger the problem made mistakes and precisely
A, B phase by basic phase demodulating, frequency doubling circuit easily produce signal burr, time delay and not actuated circuit error output ask
Topic.This logic circuit can be downloaded to programmable chip, and such as CPLD or FPGA etc., on-line debugging is convenient, and dependable performance uses valency
It is worth high.
Accompanying drawing explanation
Fig. 1 is present configuration block diagram；
Fig. 2 is one embodiment of the invention phase demodulating, frequency doubling module principle figure；
Fig. 3 is one embodiment of the invention frequency-doubled signal conditioning module schematic diagram；
Fig. 4 is one embodiment of the invention phase discrimination signal filtration module schematic diagram；
Fig. 5 is one embodiment of the invention phase demodulating, frequency doubling modular simulation waveform diagram；
Fig. 6 is one embodiment of the invention phase discrimination signal filtration module simulation waveform schematic diagram；
Fig. 7 is one embodiment of the invention frequency-doubled signal conditioning module simulation waveform schematic diagram；
Detailed description of the invention
As it is shown in figure 1, one embodiment of the invention includes phase demodulating, frequency doubling module, described phase demodulating, frequency doubling module connects has phase demodulation to believe
Number filtration module and frequency-doubled signal conditioning module.
Phase demodulating, frequency doubling module has used five d type flip flops, three XOR gates, a not gate.Phase demodulation part has used three D
Trigger, an XOR gate and a not gate, frequency multiplication part has used two d type flip flops and two XOR gates.Phase demodulation part work
It is that signal sends into XOR gate computing after d type flip flop postpones, and obtains initial phase discrimination signal, d type flip flop clock signal as principle
For initial frequency-doubled signal signal after reverse.Frequency multiplication part operation principle is, signal is after XOR gate computing, and point two-way is respectively
Sending into XOR gate and two d type flip flops postpone, d type flip flop sends into XOR gate and for the first time through the letter of XOR gate computing after postponing
Number carry out computing, obtain initial frequency-doubled signal.
Phase discrimination signal filtration module has used three d type flip flops, three NAND gate, an XOR gate.Signal is through three D
During trigger, postponing one by one, the two paths of signals after postponing carries out XOR and NAND operation respectively, then is touched by the 3rd D
Send out device output postpone signal and XOR after signal carry out NAND operation, the signal after twice NAND operation is carried out with
Inverse, obtains final phase discrimination signal.Noise and time delay issue in initial phase discrimination signal can effectively be solved.
Frequency-doubled signal conditioning module has used six d type flip flops.Signal postpones one by one through six d type flip flops, finally gives quadruple
Signal.These three circuit is combined in programming device, a kind of modified model phase demodulating, frequency doubling logic with the anti-mechanism of makeing mistakes
Circuit.
As shown in figures 1-4, the present invention is mainly nursed one's health by phase demodulating, frequency doubling module, phase discrimination signal filtration module and frequency-doubled signal
Module forms, and wherein, phase demodulating, frequency doubling module receives A, B two paths of signals needing phase demodulating, frequency doubling, is output as initial phase discrimination signal
Dir1 and initial frequency-doubled signal pulse1.Phase discrimination signal filtration module receives initial phase discrimination signal dir1, exports phase discrimination signal
dir.Frequency-doubled signal conditioning module receives initial frequency-doubled signal pulse1, exports quadruple signal pulse.
As in figure 2 it is shown, phase demodulating, frequency doubling module is mainly by five d type flip flops 1,3,4,5,9, three XOR gates 2,6,8, one
Not gate 7 forms.Wherein, the outfan of the first d type flip flop 1 and the D input of 3d flip-flop 4 are connected, 3d flip-flop 4
One input of outfan and the second XOR gate 6 be connected, the outfan of the first XOR gate 2 and one of the 3rd XOR gate 8 defeated
Enter end, the input of four d flip-flop 5 is connected, and the outfan of four d flip-flop 5 and the input of the 5th d type flip flop 9 are connected,
The outfan of the 5th trigger 9 and an input of the 3rd XOR gate 8 are connected, the outfan of the 3rd XOR gate 8 and first non-
The input of door 7 is connected, and the outfan of the second d type flip flop 3 and an input of the second XOR gate 6 are connected, the first not gate 7
Outfan input end of clock with first d type flip flop the 1, second d type flip flop 3 respectively is connected, and the input of the first XOR gate 2 is respectively
Be connected with A, B two paths of signals, 3d flip-flop 4, four d flip-flop the 5, the 5th d type flip flop 9 input end of clock all with clk time
Clock signal is connected.The enable input of all electronic components is all connected with reset signal.
As shown in Figure 4, phase discrimination signal filtration module mainly by three d type flip flops 16,17,18, three NAND gate 20,21,
22, an XOR gate composition 19.Wherein, the outfan of the tenth 2-D trigger 16 and the D input of the tenth 3d flip-flop 17,
One input of four XOR gates 19, the first NAND gate 20 an input be connected, the outfan of the tenth 3d flip-flop 17 with
The D input of the tenth four d flip-flop 18, an input of the 4th XOR gate 19, an input phase of the first NAND gate 20
Even, the outfan of the tenth four d flip-flop 18 and an input of the second NAND gate 21 are connected, the outfan of the 4th XOR gate 19
It is connected with an input of the second NAND gate 21, the outfan of the first NAND gate 20 and an input of the 3rd NAND gate 22
Being connected, the outfan of the second NAND gate 21 and an input of the 3rd NAND gate 22 are connected, the input of the tenth 2-D trigger 16
End is connected with initial phase discrimination signal, and the input end of clock of all electronic components is connected with clk signal, the enable of all electronic components
Input is connected with reset signal.
As it is shown on figure 3, frequency-doubled signal conditioning module is mainly made up of six d type flip flops 10,11,12,13,14,15.Its
In, the outfan of the 6th d type flip flop 10 and the D input of the 8th d type flip flop 12 are connected, the outfan of the 8th d type flip flop 12 with
The D input of the tenth d type flip flop 14 is connected, and the outfan of the tenth d type flip flop 14 and the D input of the 7th d type flip flop 11 are connected,
The outfan of the 7th d type flip flop and the D input of the 9th d type flip flop 13 are connected, the outfan and the 11st of the 9th d type flip flop 13
The D input of d type flip flop 15 is connected, and the input end of clock of all electronic components is connected with clk signal, making of all electronic components
Can be connected with reset signal by input.
The work process of the present invention is as follows:
In conjunction with Fig. 1～Fig. 7, first d type flip flop the 1, second d type flip flop 3 of phase demodulating, frequency doubling module and the first XOR gate 2
Input receives respectively from extraneous A, B phase signals, and the D that the output signal of the first d type flip flop 1 sends into 3d flip-flop 4 is defeated
Entering end, the output signal of 3d flip-flop 4 sends into an input of the second XOR gate 6, the output signal of the first XOR gate 2
Sending into an input of the 3rd XOR gate 8, the D input of four d flip-flop 5, the output signal of four d flip-flop 5 is sent into
The D input of the 5th d type flip flop 9, an input of output signal feeding the 3rd XOR gate 8 of the 5th trigger 9, the 3rd is different
Or the output signal of door 8 sends into the input of the first not gate 7, the output of the second d type flip flop 3 sends into one of the second XOR gate 6
Input, the input signal of the first not gate 7 is initial frequency-doubled signal and is respectively fed to first d type flip flop the 1, second d type flip flop 3
Input end of clock, the output signal of the second XOR gate 6 is initial phase discrimination signal.3d flip-flop 4, four d flip-flop the 5, the 5th
The input end of clock of d type flip flop 9 is all connected with clk clock signal.The enable input of all electronic components all with reset signal
It is connected.
The input of the tenth 2-D trigger 16 in phase discrimination signal filtration module receives initial phase discrimination signal, and the 12nd D touches
Send out the output signal of device 16 be respectively fed to the D input of the tenth 3d flip-flop 17, an input of the 4th XOR gate 19, the
One input of one NAND gate 20, the output signal of the tenth 3d flip-flop 17 send into the tenth four d flip-flop 18 D input,
One input of the 4th XOR gate 19, an input of the first NAND gate 20, the output signal of the tenth four d flip-flop 18 is sent
Entering an input of the second NAND gate 21, the output signal of the 4th XOR gate 19 sends into an input of the second NAND gate 21
End, the output signal of the first NAND gate 20 sends into an input of the 3rd NAND gate 22, the output signal of the second NAND gate 21
Sending into an input of the 3rd NAND gate 22, the output signal of the 3rd NAND gate 22 is phase discrimination signal.All electronic components
Input end of clock is connected with clk signal, and the enable input of all electronic components is connected with reset signal.
The input of the 6th d type flip flop 10 in frequency-doubled signal conditioning module receives initial frequency-doubled signal, the 6th d type flip flop
The output signal of 10 sends into the D input of the 8th d type flip flop 12, and the output signal of the 8th d type flip flop 12 sends into the tenth d type flip flop
The D input of 14, the D input of output signal feeding the 7th d type flip flop 11 of the tenth d type flip flop 14, the 7th d type flip flop 11
Outfan and the D input of the 9th d type flip flop 13, the output signal of the 9th d type flip flop 13 sends into the D of the 11st d type flip flop 15
Input, the output signal of the 11st d type flip flop 15 is quadruple signal.The input end of clock of all electronic components is believed with clk
Number be connected, the enable input of all electronic components is connected with reset signal.
Clock pulse frequency fclkShould be greater than A, B phase signals frequency fA, B8 times, but can not be equal to 16 times.Optimal clock arteries and veins
Rush frequency fclkFor in A, B phase signals frequency fA, B32 times, i.e. fclk=32 × fA, B。
Fig. 5～Fig. 7 is for show for phase demodulating, frequency doubling module, phase discrimination signal filtration module and frequency-doubled signal conditioning module simulation waveform
It is intended to, it can be seen that precisely A, B phase signals signal after basic phase demodulating, frequency doubling module has burr, the time prolongs
The problem of mistake output during slow and not actuated circuit, is simultaneously introduced a kind of anti-mechanism of makeing mistakes, prevents circuit clock signal from touching through D
Produce collision problem when sending out device, be presented as the clock utilizing initial frequency-doubled signal as phase discriminator.Module and tune after filtering
Reason module, obtains accurate phase discrimination signal and frequency-doubled signal.
The present invention obtains initial phase discrimination signal and initial frequency multiplication by five d type flip flops, three XOR gates and a not gate
Signal, through phase discrimination signal filtration module and frequency-doubled signal conditioning module, solves the signal burr that phase demodulating, frequency doubling process causes
And time delay issue.By using initial phase discrimination signal reversely as the clock signal of d type flip flop, be prevented effectively from because of clock signal
With the collision problem of A, B phase signals, simultaneously by the filtering modulate circuit after introducing phase demodulating, frequency doubling, efficiently solve current techniques
Mistake output when the accurate signal ignored can produce burr, time delay and not actuated circuit by basic phase discriminator module
Problem.Present system precision is high, and circuit is simple and reliable, can be downloaded to programmable chip, such as CPLD or FPGA etc., adjusts online
Examination is convenient, great use value.
Claims (1)
1. a phase demodulating, frequency doubling logic circuit for the anti-mechanism of makeing mistakes of band, including phase demodulating, frequency doubling module, described phase demodulating, frequency doubling module bag
Include five d type flip flops, not gate, three XOR gates, the A road signal of the input input phase demodulating, frequency doubling of the first d type flip flop, the 2nd D
The input end of clock of B road signal wherein four d flip-flop and the 5th d type flip flop of the input input phase demodulating, frequency doubling of trigger connects
External timing signal, the enable input of five d type flip flops all connects outside enable signal；First d type flip flop outfan and the 3rd D
Trigger input connects, and 3d flip-flop outfan and one input of the second XOR gate connect；Described second XOR gate is another
One input and the second d type flip flop outfan connect；It is characterized in that, the first d type flip flop, the second d type flip flop and the 3rd D touch
The input end of clock equal NAND gate outfan sending out device connects；A, B two paths of signals of described phase demodulating, frequency doubling inputs the first XOR gate
Two inputs, the input of described first XOR gate outfan and an input of the 3rd XOR gate, four d flip-flop connects
Connect；Another input of described 3rd XOR gate and the 5th d type flip flop outfan connect；Described 5th d type flip flop input
It is connected with four d flip-flop outfan；The output signal of described 3rd XOR gate sends into the input of described not gate；Initial frequency multiplication
Signal pulse1 sends into the input of described not gate；
Described phase demodulating, frequency doubling module connects phase discrimination signal filtration module and frequency-doubled signal conditioning module；Phase demodulating, frequency doubling module exports
For initial phase discrimination signal dir1 and initial frequency-doubled signal pulse1；Phase discrimination signal filtration module receives initial phase discrimination signal dir1,
Frequency-doubled signal conditioning module receives initial frequency-doubled signal pulse1；Phase discrimination signal filtration module output phase discrimination signal dir, frequency multiplication is believed
Number conditioning module output quadruple signal pulse；
Described frequency-doubled signal conditioning module includes that 6 d type flip flops being sequentially connected with, the outfan of the 6th d type flip flop and the 8th D touch
The D input sending out device is connected, and the outfan of the 8th d type flip flop and the D input of the tenth d type flip flop are connected, the tenth d type flip flop
The D input of outfan and the 7th d type flip flop is connected, the outfan of the 7th d type flip flop and the D input phase of the 9th d type flip flop
Even, the outfan of the 9th d type flip flop and the D input of the 11st d type flip flop are connected；Described second XOR gate outfan is with described
Tenth 2-D trigger input of phase discrimination signal filtration module connects, all d type flip flops in described frequency-doubled signal conditioning module
Input end of clock be all connected with external timing signal, the enable of all d type flip flops in described frequency-doubled signal conditioning module is defeated
Enter end to be all connected with outside enable signal；
Described phase discrimination signal filtration module includes three d type flip flops, three NAND gate and the 4th XOR gate, the tenth 2-D trigger
Outfan and the tenth 3d flip-flop D input connect；The outfan of the tenth 3d flip-flop and the D of the tenth four d flip-flop
Input connects；Three d type flip flop input end of clock of described phase discrimination signal filtration module are all connected with external timing signal, institute
Three the d type flip flops enable inputs stating phase discrimination signal filtration module are all connected with outside enable signal；Described phase discrimination signal is filtered
Tenth four d flip-flop outfan of mode block and one input of the second NAND gate connect, and another is defeated for described second NAND gate
Entering end to be connected with described 4th XOR gate outfan, an input of described 4th XOR gate accesses the tenth 2-D trigger
Between the D input of outfan and the tenth 3d flip-flop, another input of described 4th XOR gate accesses the 13rd D and touches
Send out between outfan and the D input of the tenth four d flip-flop of device；One input of the first NAND gate accesses the 12nd D and touches
Send out between outfan and the D input of the tenth 3d flip-flop of device, another input of described first NAND gate accesses the tenth
Between outfan and the D input of the tenth four d flip-flop of 3d flip-flop；Described first NAND gate outfan, the second NAND gate
Outfan is connected with two inputs of the 3rd NAND gate respectively；
Phase demodulating, frequency doubling module, phase discrimination signal filtration module, frequency-doubled signal conditioning module external timing signal clock pulses frequency
RateShould be greater than phase demodulating, frequency doubling modules A, B phase signals frequency8 times, but can not be equal to 16 times.
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| CN201310444979.7A CN103475344B (en) | 2013-09-26 | 2013-09-26 | A kind of phase demodulating, frequency doubling logic circuit with the anti-mechanism of makeing mistakes |
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| CN103475344B true CN103475344B (en) | 2017-01-04 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101534109A (en) * | 2009-03-30 | 2009-09-16 | 浙江大学 | Orthogonal signal frequency-multiplication phase-demodulation logic circuit with filter function |
| CN101789784A (en) * | 2009-12-15 | 2010-07-28 | 北京时代民芯科技有限公司 | Configurable phase discriminator for time-delay locking ring |
| CN201898500U (en) * | 2010-11-10 | 2011-07-13 | 天津光电通信技术有限公司 | Phase demodulating, frequency doubling and counting device |
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| US7027505B2 (en) * | 2001-05-04 | 2006-04-11 | Al-Eidan Abdullah A | System and method for bandwidth compression of frequency and phase modulated signals and suppression of the upper and lower sidebands from the transmission medium |
| DE102006052873B4 (en) * | 2006-11-09 | 2013-07-11 | Siemens Aktiengesellschaft | Filter circuitry |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101534109A (en) * | 2009-03-30 | 2009-09-16 | 浙江大学 | Orthogonal signal frequency-multiplication phase-demodulation logic circuit with filter function |
| CN101789784A (en) * | 2009-12-15 | 2010-07-28 | 北京时代民芯科技有限公司 | Configurable phase discriminator for time-delay locking ring |
| CN201898500U (en) * | 2010-11-10 | 2011-07-13 | 天津光电通信技术有限公司 | Phase demodulating, frequency doubling and counting device |
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