CN103426866B - The design rule test circuit at fence interval - Google Patents
The design rule test circuit at fence interval Download PDFInfo
- Publication number
- CN103426866B CN103426866B CN201210155011.8A CN201210155011A CN103426866B CN 103426866 B CN103426866 B CN 103426866B CN 201210155011 A CN201210155011 A CN 201210155011A CN 103426866 B CN103426866 B CN 103426866B
- Authority
- CN
- China
- Prior art keywords
- conductive layer
- hole
- fence
- mosfet
- interval
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention provides the design rule test circuit at a kind of fence interval, including: conductive layer；Being located at multiple through holes of described conductive layer, the plurality of through hole is distributed in file on described conductive layer, and the fence interval of each through hole and described conductive layer is each unequal；Grid electrically connects with described conductive layer, drain electrically connect with power input, MOSFET that source electrode electrically connects with power output end；The multiple conductor layers electrically connected with the plurality of through hole respectively, the plurality of conductor layer electrically connects with multiple control ends respectively.These circuit multiple can carry out series connection by the source electrode of wherein MOSFET, drain electrode and form bigger test circuit.This circuit is by measuring the saturation current I of MOSFETdsat, and then test out the position skew that will make due to the error of manufacturing process conductive layer and through hole in actual manufacture process and produce the optimal fence interval of open circuit.The design rule test circuit at the fence interval of the present invention decreases the use of weld pad, saves domain space, and simplifies detection process.
Description
Technical field
The present invention relates to semiconductor fabrication, particularly to setting that the fence in a kind of layout design is spaced
The design rule test circuit at meter regular testing method and fence interval.
Background technology
In the domain (layout) of semiconductor technology designs, a geometric figure is (such as contact hole contact
Or through hole via) external boundary is in another figure (such as polysilicon layer poly or metal level metal)
The length on border is called enclosure, referred to herein as fence interval.Fig. 1 is the first graph layer and
The schematic diagram of Fence structure that two graph layers are formed, be wherein in the first graph layer A(such as contact hole or
Through hole) external boundary and second graph layer B(such as polysilicon layer or metal level) inner boundary between
The length of horizontal line C is fence interval (enclosure).
In the design rule (Design Rule) of layout design, for contact hole (contact) outside
Boundary is to polysilicon layer (poly) inner boundary, contact hole external boundary to metal level (metal) inner boundary, logical
Hole (via) external boundary is to metal level inner boundary etc., and the precision at fence interval is the most crucial and basic
Design parameter, the size at fence interval directly influences the quality of performance of made integrated circuit.
As in figure 2 it is shown, be under 45nm process node existing a kind of contact hole external boundary to polysilicon layer
The test structural representation at the fence interval of inner boundary.Wherein it is respectively directed to contact hole external boundary to polysilicon
The different size of fence interval of layer inner boundary, in the embodiment shown in Fig. 2, design altogether on domain 3
12 matrixes 1, the internal structure of each matrix 1 is the most identical, but the size at fence therein interval is each
Differ, from left to right the fence in each matrix 1 interval be respectively 0nm, 10nm, 15nm, 20nm,
25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, between each matrix 1
Interval connects outside weld pad (pad) 2, and the matrix 1 of fence interval 0nm and fence interval 60nm
Side is also all connected with weld pad 2, and so, the two ends of each matrix 1 are all connected with weld pad 2, so have 13
Individual weld pad 2.Fig. 3 is the enlarged drawing of the matrix 1 of fence interval 10nm, the polycrystalline of matrix 1 in Fig. 2
Silicon layer (dashed region in Fig. 2, Fig. 3) 11 is connected to the weld pad 2 of side beyond matrix, matrix 1
In each matrix unit in contact hole be all connected to the weld pad of opposite side beyond matrix by wire 12
2.Fig. 4 is the internal structure enlarged drawing of a matrix unit in matrix shown in Fig. 3, wherein contact hole
Fence between A1 and polysilicon layer 11 is spaced apart 10nm.Because contact hole A1 and polysilicon layer 11
Between the difference at fence interval can cause the difference of leakage current, weld pad 2 the most just can be utilized to measure and to lead
The leakage current of line-contact hole-polysilicon layer, by the comparison to leakage current, selects between optimal fence
Every, the fence interval as corresponding to the matrix that leakage current is minimum.
In prior art, need to various fences interval (as contact hole external boundary to polysilicon layer inner boundary,
Contact hole external boundary is to metal level inner boundary, through hole external boundary to metal level inner boundary etc.) repeatedly set
Meter is with explication.The most just need to use a large amount of weld pad (as used 13 weld pads in Fig. 2), and
These weld pads can not be reused, and carries out the design that through hole is spaced to metal level fence the most again and is also required to class
Like the layout architecture in Fig. 2, but but because the restriction of weld pad needs to use another BT(batch testing) weld pad.
Summary of the invention
In view of this, the present invention provides the design rule test circuit that a kind of fence is spaced, to reduce weld pad
Use, save domain space, and simplify detection process.
The technical scheme is that and be achieved in that:
A kind of design rule test circuit at fence interval, including:
One conductive layer；
Being located at multiple through holes of described conductive layer, the plurality of through hole is distributed in file on described conductive layer,
And the fence interval of each through hole and described conductive layer is each unequal；
Grid electrically connects with described conductive layer, drain electrically connect with power input, source electrode exports with power supply
The MOSFET of end electrical connection；
The multiple conductor layers electrically connected with the plurality of through hole respectively, the plurality of conductor layer is respectively with multiple
Control end electrical connection.
Further, described conductive layer is polysilicon layer or the metal level being applied to semiconductor device.
Further, described through hole is 12, and described conductor layer is 12.
Further, each through hole and described conductive layer fence interval be respectively 0nm, 10nm, 15nm,
20nm、25nm、30nm、35nm、40nm、45nm、50nm、55nm、60nm。
A kind of design rule test circuit at fence interval, including:
Multiple conductive layers in horizontally-arranged distribution；
Being located at multiple through holes of the plurality of conductive layer, the plurality of through hole is array distribution, described array
In be positioned at all through holes of same file and be located at same conductive layer, described array is positioned at same horizontally-arranged institute
Have through hole to be respectively arranged on different conductive layers, be positioned at each through hole being located at same conductive layer of same file with
The fence interval of this same conductive layer is each unequal, is positioned at the same horizontally-arranged different conductive layers that is respectively arranged on
The fence interval of each through hole and its residing conductive layer is the most equal；
The multiple MOSFETs equal with the plurality of conductive layer quantity, the grid of each MOSFET with
Each conductive layer electrically connects one to one, and the plurality of MOSFET consists of source electrode, drain series
MOSFET series circuit, is in drain electrode and the power supply of the MOSFET of MOSFET series circuit one end
Input electrically connects, and the source electrode of the MOSFET being in the MOSFET series circuit other end is defeated with power supply
Go out end electrical connection；
The multiple conductor layers equal with the horizontally-arranged quantity of through hole, are positioned at same horizontally-arranged all through holes all with same
One conductor layer electrical connection, all through holes being positioned at same file electrically connect with different conductor layer respectively, and
The plurality of conductor layer electrically connects with multiple control ends respectively.
Further, described conductive layer is polysilicon layer or the metal level being applied to semiconductor device.
Further, described conductive layer is 5 ~ 1000, and described MOSFET is 5 ~ 1000, described logical
The file in hole is 5 ~ 1000 row.
Further, the horizontally-arranged of described through hole is 12 rows, and described conductor layer is 12.
Further, every exhausting hole and conductive layer fence interval be respectively 0nm, 10nm, 15nm, 20nm,
25nm、30nm、35nm、40nm、45nm、50nm、55nm、60nm。
Further, described MOSFET is N-type MOSFET or p-type MOSFET.
From such scheme it can be seen that the design rule at the fence interval of the present invention tests circuit, with conduction
The Fence structure that layer is formed with through hole as the gate switch circuit of MOSFET, measure conductive layer and
The MOSFET saturation current I corresponding to fence interval of through holedsat, and then obtain fence interval and
MOSFET saturation current IdsatCorresponding relation, according to saturation current IdsatSelected optimal the enclosing of change
Hurdle gap size is as the fence spacing parameter in layout design, and this optimal fence interval will not be due to system
Make the error of technique and make conductive layer and the through hole position in actual manufacture process offset and produce open circuit,
Compared with existing measuring technology, decrease the use of weld pad, save domain space, and simplify and detected
Journey.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of Fence structure；
Fig. 2 be in prior art contact hole external boundary to polysilicon layer inner boundary fence be spaced test knot
Structure schematic diagram；
Fig. 3 is the enlarged drawing of the matrix of fence interval 10nm in Fig. 2；
Fig. 4 is the internal structure enlarged drawing of a matrix unit in matrix shown in Fig. 3；
Fig. 5 is the design rule test circuit theory diagrams at the fence interval of the present invention；
Fig. 6 is the design rule test circuit first embodiment schematic diagram at the fence interval of the present invention；
Fig. 7 is design rule test circuit the second embodiment schematic diagram at the fence interval of the present invention.
Detailed description of the invention
For making the purpose of the present invention, technical scheme and advantage clearer, develop simultaneously referring to the drawings
Embodiment, is described in further detail the present invention.
In implementation below, unification represents the contact hole in art technology with title " through hole "
And through hole (via) etc. (contact), should " through hole " title not in order to the restriction to through hole (via),
Those skilled in the art can promote its representative contact hole (contact) known according to this " through hole " title
With through hole (via) etc..
In implementation below, title " conductive layer " can be applied to semiconductor device polysilicon layer,
Metal levels etc. are for the functional layer of conduction.
Each of " through hole " being stacked up and down in the semiconductor device of designed production and circuit " is led
Electric layer " and (for conduction functional layer) between electrical connection, well known in the art.
The thought of the present invention is:
Research finds, as it is shown in figure 5, for the Fence structure that conductive layer 4 and through hole 5 are formed,
The grid of conductive layer 4 with a MOSFET 6 is electrically connected, by through hole 5 by conductor layer 7 and a control
End K processed electrically connects, and the drain electrode of MOSFET 6 and source electrode export with power input F1 and power supply respectively
After end F2 electrical connection, when accessing input pole (such as V at power input F1dd), at power output end
F2 accesses output stage (such as GND), and is controlling end K Access Control pole (such as VggAfter), MOSFET
6 will turn on.Saturation current I when MOSFET 6 turns ondsatSize and conductive layer 4 and through hole 5
The fence interval of the Fence structure formed also exists contact: in semiconductor fabrication, owing to existing
The error of manufacturing process, when fence interval is the least, it is possible to make conductive layer 4 and through hole 5 in reality
Position in manufacture process occurs skew that open circuit occurs so that controlling pole tension (stream) cannot be applied to
The grid of MOSFET 6 and make transistor to turn on, and then cannot be formed saturated in MOSFET 6
Electric current Idsat, so that the electric current change between power input F1 and power output end F2 is the least.Base
In this thought, the invention provides the design rule test circuit at a kind of fence interval.
As shown in Figure 6, the first embodiment of the design rule test circuit being spaced for the fence of the present invention is shown
It is intended to.This circuit includes: a conductive layer 4；It is located at multiple through holes of this conductive layer 4, as shown in Figure 6
First through hole the 51, second through hole 52 ..., m through hole 5m(m be the positive integer more than 1),
The plurality of through hole is distributed in file on this conductive layer 4, and the fence interval of each through hole and conductive layer 4
Each unequal, in Fig. 6, the first through hole 51 to m through hole 5m on conductive layer 4 from top to bottom
It is distributed in file, is spaced from the fence of the first through hole 51 to m through hole 5m and conductive layer 4 and gradually increases
Greatly；One MOSFET 6, the grid of MOSFET 6 electrically connects with conductive layer 4, drains and power supply input
End F1 electrical connection, source electrode electrically connect with power output end F2；Multiple conductor layers, respectively with multiple through holes
Electrical connection, in Fig. 6, conductor layer No.1 71 electrically connects with the first through hole 51, the second conductor layer 72
Electrically connect with the second through hole 52 ..., m conductor layer 7m and m through hole 5m electrical connection, many
Individual conductor layer electrically connects with multiple control ends the most respectively, and in Fig. 6, conductor layer No.1 71 and first controls
End K1 electrical connection, the second conductor layer 72 with second control end K2 electrically connect ..., m conductor layer
7m and m controls end Km electrical connection.
The design rule utilizing the embodiment circuit shown in Fig. 6 to carry out fence interval is tested by the following method
Carry out.Power input F1 accesses input pole (such as Vdd), access output stage at power output end F2
(such as GND)；The first control end K1 Access Control pole corresponding with the first through hole 51 is (such as Vgg),
It is vacant that other control ends, record be spaced with the fence of the first through hole 51 and conductive layer 4 corresponding now
The saturation current I of MOSFET 6dsat；The second control end K2 corresponding with the second through hole 52 accesses control
Pole processed is (such as Vgg), it is vacant that other control end, between the fence of record and the second through hole 52 and conductive layer 4
Saturation current I every corresponding MOSFET 6 nowdsat；……；Relative with m through hole 5m
The m answered controls end Km Access Control pole (such as Vgg), it is vacant that other control end, record and m
The fence of through hole 5m and conductive layer 4 is spaced the saturation current I of corresponding MOSFET 6 nowdsat；
According to all fences interval recorded and corresponding saturation current IdsatRelation, select optimal
Saturation current IdsatCorresponding fence interval is spaced as the fence of design rule.Fence interval and with
The saturation current I of correspondencedsatRelation, can be represented by a coordinate system, such as the transverse axis in a coordinate system
(x-axis) upper mark saturation current Idsat, at the longitudinal axis (y-axis) the upper mark fence interval of this coordinate system,
By the fence interval recorded and corresponding saturation current IdsatLabelling in the coordinate system, just can obtain
To fence interval and saturation current IdsatCurve relation figure, and according to this graph of a relation select be suitable for fence
Interval.
Corresponding with the prior art shown in Fig. 2, in the present embodiment, m desirable 12, i.e. electricity shown in Fig. 6
Lu Zhong, total: 12 through holes, respectively first through hole the 51, second through hole 52 ..., the 12nd
Through hole 512；12 conductor layers, respectively conductor layer No.1 the 71, second conductor layer 72 ..., the tenth
Two conductor layers 712；12 control end, and respectively first controls end K1 electrical connection, the second control end
K2 ..., the 12nd control end K12；From the first through hole 51 to the 12nd through hole 512, with conductive layer
4 fence interval be respectively 0nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm,
45nm、50nm、55nm、60nm；MOSFET 6 can use N-type MOSFET, power input
The voltage of the input pole that F1 accesses is 2.5V, power output end F2 ground connection；Each controls end and connects respectively
The voltage controlling pole entered is 2.5V.Using above-mentioned parameter, utilization can test the saturated electricity of MOSFET
Stream IdsatSaturation current test instrunment just can obtain each fence above-mentioned interval corresponding to saturation current
Idsat, and then can be according to these saturation currents IdsatSelect optimal fence interval.MOSFET also may be used
To use p-type MOSFET, adjust according to the turn-on condition of p-type MOSFET control to terminate into control
Pole tension processed so that p-type MOSFET turns on, it is possible to carry out saturation current IdsatMeasurement.
Embodiment illustrated in fig. 6 use a MOSFET one conductive layer 4 and through hole therein are enclosed
Hurdle structure measures, and includes substantial amounts of semiconductor device in integrated circuits, utilizes shown in Fig. 6
Only include the circuit of a conductive layer 4 and the Fence structure of through hole therein, owing to sampling is very few and not enough
To carry out the test of fence spaced design rule, it is therefore desirable to other embodiments make saturation current Idsat
Can survey.
As it is shown in fig. 7, be the second enforcement illustration of the design rule test circuit at the fence interval of the present invention
It is intended to.Compared with Fig. 6, embodiment illustrated in fig. 7 is the cascade of Fig. 6, and this circuit concrete structure is such as
Under.
This circuit includes: the multiple conductive layers in horizontally-arranged distribution, the first conductive layer 41 as shown in Figure 7,
Second conductive layer 42 ..., the n-th conductive layer 4n；It is located at multiple through holes of the plurality of conductive layer, such as figure
In 7, multiple through holes are located at the first conductive layer 41 to the n-th conductive layer 4n, and multiple through holes are array distribution,
The all through holes being positioned at same file in this array are located at same conductive layer, such as the first of the first conductive layer 41
Through hole the 51, second through hole 52 ..., m through hole 5m are positioned at same file, the second conductive layer 42
First through hole the 51, second through hole 52 ..., m through hole 5m be positioned at same file ...,
First through hole 51, second through hole 52 ... of the n-th conductive layer 4n, m through hole 5m are positioned at same
File, is positioned at same horizontally-arranged all through holes and is respectively arranged on different conductive layers, in Fig. 7 in this array
All first through holes 51 are positioned at same horizontally-arranged and are respectively arranged at the first conductive layer 41 to the n-th conductive layer 4n,
All second through holes 52 are positioned at same horizontally-arranged and are respectively arranged at the first conductive layer 41 to the n-th conductive layer
4n ..., all m through hole 5m be positioned at same horizontally-arranged and be respectively arranged at the first conductive layer 41 to
N-th conductive layer 4n, is positioned at each through hole being located at same conductive layer and this same conductive layer of same file
Fence interval each unequal, in Fig. 7, be positioned at each through hole of the first conductive layer 41 and first lead with this
Electric layer 41 fence interval each unequal and from the first through hole 51 to m through hole 5m and the first conductive layer
The fence interval of 41 is gradually increased, and is positioned at each through hole and this second conductive layer 42 of the second conductive layer 42
Fence interval each unequal and from the first through hole 51 to m through hole 5m and this second conductive layer 42
Fence interval is gradually increased ..., it is positioned at each through hole and this n-th conductive layer of the n-th conductive layer 4n
The fence interval of 4n is each unequal and from the first through hole 51 to m through hole 5m and this n-th conductive layer 4n
Fence interval be gradually increased, be positioned at the same horizontally-arranged each through hole being respectively arranged on different conductive layers and its
The fence interval of residing conductive layer is the most equal, in Fig. 7, is positioned at same the first horizontally-arranged through hole 51
It is respectively arranged at the first conductive layer 41 to the n-th conductive layer 4n, and the first conductive layer 41 to the n-th conductive layer
First through hole 51 of each conductive layer of 4n and the fence interval of this conductive layer are the most equal, are positioned at same horizontal stroke
Second through hole 52 of row is respectively arranged at the first conductive layer 41 to the n-th conductive layer 4n, and the first conductive layer
Second through hole 52 of each conductive layer of 41 to the n-th conductive layer 4n and the fence interval of this conductive layer are homogeneous
Deng ..., it is positioned at same horizontally-arranged m through hole 5m and is respectively arranged at the first conductive layer 41 to the n-th
Conductive layer 4n, and the m through hole 5m of each conductive layer of the first conductive layer 41 to the n-th conductive layer 4n
And the fence interval of this conductive layer is the most equal；The multiple MOSFETs equal with the plurality of conductive layer quantity,
The grid of each MOSFET electrically connects one to one with each conductive layer, such as a MOSFET 61 in Fig. 7
Being electrically connected by grid and the first conductive layer 41, the 2nd MOSFET 62 is by grid and the second conductive layer
42 electrical connections ..., the n-th MOSFET 6n is electrically connected by grid and the n-th conductive layer 4n, and these are many
Individual MOSFET is by source electrode, drain series composition MOSFET series circuit, the i.e. the oneth MOSFET 61
Source electrode and the 2nd MOSFET 62 drain electrode connect, the source electrode and the 3rd of the 2nd MOSFET 62
MOSFET(Fig. 7 is not shown) drain electrode connect ..., (n-1)th MOSFET(Fig. 7 is not shown)
Source electrode and the n-th MOSFET 6n drain electrode connect, be in MOSFET series circuit one end
The drain electrode of MOSFET electrically connects with power input, is in the MOSFET series circuit other end
The source electrode of MOSFET electrically connects with power output end, as being in MOSFET series circuit one in Fig. 7
The drain electrode of the oneth MOSFET 61 of end electrically connects with power input F1, is in MOSFET series connection
The source electrode of the n-th MOSFET 6n of the circuit other end electrically connects with power output end F2；Horizontal stroke with through hole
Multiple conductor layers that row amount is equal, each conductor layer electrically connects with each horizontally-arranged all through holes respectively,
I.e. it is positioned at same horizontally-arranged all through holes all to electrically connect with same conductor layer, is positioned at all of same file
Through hole electrically connects with different conductor layer respectively, and the plurality of conductor layer electrically connects with multiple control ends respectively,
Such as m conductor layer in Fig. 7, wherein conductor layer No.1 71 respectively be in same horizontally-arranged upper and be positioned at not
Electrically connect with all first through holes 51 of conductive layer, the second conductor layer 72 respectively be in same horizontally-arranged on
And all second through holes 52 being positioned at different conductive layers electrically connect ..., m conductor layer 7m is respectively
Electrically connect with being in all m through hole 5m that are same horizontally-arranged upper and that be positioned at different conductive layers, the first wire
Layer 71 electrically connects with the first control end K1, the second conductor layer 72 electrically connects with the second control end K2 ...,
M conductor layer 7m and m controls end Km electrical connection.
Compared with the circuit of Fig. 6, the circuit of Fig. 7 is the extension of circuit shown in Fig. 6, is shown in Fig. 6
The cascade of circuit, wherein any one unit in Fig. 7, as the i-th MOSFET, the i-th conductive layer,
And i-th first through hole 51 of conductive layer be the integer of 1 to n to m through hole 5m(i) form
Circuit structure unit is circuit structure shown in Fig. 6.I.e. in circuit shown in Fig. 7, multiple conductive layers to
Expressing the meaning is at least 1 conductive layer, then as a special case, if wherein only having 1 conductive layer (i.e.
N=1), time, its structure is consistent with Fig. 6.
In structure shown in Fig. 7, power input F1 is accessed input pole (such as Vdd), export at power supply
End F2 accesses output stage (such as GND), not shown with jth through hole 5j(Fig. 7) corresponding jth
Controlling end Kj(Fig. 7 not shown) (j is the integer of 1 to m) Access Control pole is (such as Vgg) time,
It is not shown by jth conductor layer 7j(Fig. 7 that this jth controls end Kj) electrically connect with each jth through hole 5j
All MOSFET can be made simultaneously to all turn on, thus can measure this jth control end Kj and be connected
The jth through hole 5j connect and the power input F1 corresponding to fence interval of conductive layer is to power output end
The saturation current I of the MOSFET series circuit of F2dsat。
Compared with embodiment illustrated in fig. 6, Fig. 7 have employed the series system of multiple Fig. 6 structure, adds
Multiple conductive layers and the Fence structure of through hole therein, and then add a large amount of sampling so that fence is spaced
The test of design rule is more accurate, such as:
When the circuit utilizing Fig. 6 carries out the test of fence spaced design rule, due to the error of manufacturing process,
Just this kind of situation it is likely to occur: in jth1The jth that through hole is corresponding1After controlling end Access Control extremely, can measure
The saturation current I of MOSFET 6dsat, and in jth1Through hole is to jth corresponding to m through hole1Control end
The saturation current I of MOSFET 6 all can be measured after controlling end Access Control extremely to mdsat, and in jth1-1
The jth that through hole is corresponding1-1 controls end even than jth1The through hole pair of Fence structure less corresponding to-1 through hole
After the control end Access Control extremely answered, all can not measure the saturation current I of MOSFET 6dsat, the most permissible
Select jth1The design rule parameter that fence gap size corresponding to through hole is spaced as fence.But because of
For in circuit structure shown in Fig. 6, only carry out MOSFET 6 grid by a Fence structure and control pole
Access, just exist sample very few (only by a Fence structure) and cause test inaccurate problem.
And for circuit shown in Fig. 7, the most all of MOSFET grid is all connected just with control pole
Can guarantee that the series circuit that MOSFET is formed turns on and produces saturation current Idsat.Accordingly, because system
Make the error of technique, be just likely to occur this kind of situation: i-th1Jth on conductive layer1Through hole is in actual system
Position during making occurs skew that open circuit occurs so that i-th1Conductive layer corresponding i-th1MOSFET
It is unsatisfactory for turn-on condition, but jth on other conductive layers1Through hole does not occur open circuit to make other
MOSFET meets turn-on condition, due to i-th1MOSFET is unsatisfactory for turn-on condition and makes to own
The series circuit of MOSFET composition cannot turn on, thus can't detect what all MOSFET were formed
The saturation current I of series circuitdsat, this just illustrates jth1Fence gap size corresponding to through hole is not suitable for
Design rule parameter as fence interval.Only occur in this jth on all of conductive layer1Through hole is corresponding
Fence interval ensure under the error of manufacturing process, it is possible to make all MOSFET all can Access Control
Pole and then the series circuit that MOSFET is formed turn on and produce saturation current Idsat, guarantee
This jth1The fence gap size that through hole is corresponding can be as the design rule parameter at fence interval.
Therefore the embodiment of Fig. 7 with Fig. 6 is compared, and the test for fence spaced design rule is more accurate.
For circuit shown in Fig. 7, during actual application, the quantity of n can be arranged as required to be 5 ~ 1000,
Corresponding conductive layer quantity is 5 ~ 1000, and MOSFET is 5 ~ 1000, the through hole in array distribution
File is 5 ~ 1000 row.The quantity of n is difficult to very few and affects the sampling of Fence structure.Below with Fig. 2 institute
The prior art shown is corresponding, introduces and uses circuit shown in Fig. 7 to carry out saturation current IdsatMeasurement and select
Select an embodiment at optimal fence interval.
In the present embodiment, m desirable 12, i.e. in circuit shown in Fig. 7, in the array that through hole is formed,
The horizontally-arranged of through hole is 12 rows altogether, and in the first conductive layer 41 to the n-th conductive layer 4n, each conductive layer all has
12 through holes, respectively first through hole the 51, second through hole 52 ..., the 12nd through hole 512(Fig. 7
Not shown)；Conductor layer is 12, respectively conductor layer No.1 the 71, second conductor layer 72 ...,
12nd conductor layer 712(Fig. 7 is not shown)；12 control end, and respectively first controls end K1 electricity
Connect, second control end K2 ..., the 12nd control end K12(Fig. 7 not shown)；Lead to from first
Horizontally-arranged to the 12nd through hole 512 of hole 51 horizontally-arranged, the fence interval point of every exhausting hole and each conductive layer
Not Wei 0nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm,
55nm、60nm；N takes 500, then MOSFET is 500, and conductive layer is 500, all MOSFET
All using N-type MOSFET, the voltage of the input pole that power input F1 accesses is 2.5V, at power supply
Outfan F2 ground connection；Each control voltage controlling pole that end is respectively connected to be 2.5V(simultaneously other
Control the most vacant).Using above-mentioned parameter, utilization can test saturation current IdsatSaturation current tester
Device just can obtain the series circuit being made up of 500 MOSFET corresponding to each fence above-mentioned interval
Saturation current Idsat, and then can be according to these saturation currents IdsatSelect optimal fence interval.This
A little MOSFET can also use p-type MOSFET, adjusts according to the turn-on condition of p-type MOSFET
Control terminate into control pole tension so that p-type MOSFET turn on, it is possible to carry out saturation current Idsat
Measurement.
Compared with prior art shown in Fig. 2, the above-mentioned test circuit of the present invention, with conductive layer and through hole institute
The Fence structure formed, as the gate switch circuit of MOSFET, measures the fence of conductive layer and through hole
MOSFET saturation current I corresponding to intervaldsat, and then obtain fence interval and the saturated electricity of MOSFET
Stream IdsatCorresponding relation, according to saturation current IdsatThe selected optimal fence gap size conduct of change
Fence spacing parameter in layout design, this optimal fence interval will not be due to the error of manufacturing process
The position skew in actual manufacture process of conductive layer and through hole is made to produce open circuit, with existing test skill
Art is compared, and the circuit of the present invention need not arrange weld pad between each different Fence structure, thus subtracts
Lack the use of weld pad, saved domain space, and simplify detection process.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all at this
Within the spirit of invention and principle, any modification, equivalent substitution and improvement etc. done, should be included in
Within the scope of protection of the invention.
Claims (10)
1. the design rule test circuit at a fence interval, it is characterised in that including:
One conductive layer；
Being located at multiple through holes of described conductive layer, the plurality of through hole is distributed in file on described conductive layer,
And the fence interval of each through hole and described conductive layer is each unequal；
Grid electrically connects with described conductive layer, drain electrically connect with power input, source electrode exports with power supply
The MOSFET of end electrical connection；
The multiple conductor layers electrically connected with the plurality of through hole respectively, the plurality of conductor layer is respectively with multiple
Control end electrical connection；
Wherein, described fence is spaced apart the horizontal line being between the external boundary of through hole and the inner boundary of conductive layer
Length.
The design rule test circuit at fence the most according to claim 1 interval, it is characterised in that:
Described conductive layer is polysilicon layer or the metal level being applied to semiconductor device.
The design rule test circuit at fence the most according to claim 1 interval, it is characterised in that:
Described through hole is 12, and described conductor layer is 12.
The design rule test circuit at fence the most according to claim 3 interval, it is characterised in that:
Each through hole and described conductive layer fence interval be respectively 0nm, 10nm, 15nm, 20nm, 25nm,
30nm、35nm、40nm、45nm、50nm、55nm、60nm。
5. the design rule test circuit at a fence interval, it is characterised in that including:
Multiple conductive layers in horizontally-arranged distribution；
Being located at multiple through holes of the plurality of conductive layer, the plurality of through hole is array distribution, described array
In be positioned at all through holes of same file and be located at same conductive layer, described array is positioned at same horizontally-arranged institute
Have through hole to be respectively arranged on different conductive layers, be positioned at each through hole being located at same conductive layer of same file with
The fence interval of this same conductive layer is each unequal, is positioned at the same horizontally-arranged different conductive layers that is respectively arranged on
The fence interval of each through hole and its residing conductive layer is the most equal；
The multiple MOSFETs equal with the plurality of conductive layer quantity, the grid of each MOSFET with
Each conductive layer electrically connects one to one, and the plurality of MOSFET consists of source electrode, drain series
MOSFET series circuit, is in drain electrode and the power supply of the MOSFET of MOSFET series circuit one end
Input electrically connects, and the source electrode of the MOSFET being in the MOSFET series circuit other end is defeated with power supply
Go out end electrical connection；
The multiple conductor layers equal with the horizontally-arranged quantity of through hole, are positioned at same horizontally-arranged all through holes all with same
One conductor layer electrical connection, all through holes being positioned at same file electrically connect with different conductor layer respectively, and
The plurality of conductor layer electrically connects with multiple control ends respectively；
Wherein, described fence is spaced apart the horizontal line being between the external boundary of through hole and the inner boundary of conductive layer
Length.
The design rule test circuit at fence the most according to claim 5 interval, it is characterised in that:
Described conductive layer is polysilicon layer or the metal level being applied to semiconductor device.
The design rule test circuit at fence the most according to claim 5 interval, it is characterised in that:
Described conductive layer is 5～1000, and described MOSFET is 5～1000, and the file of described through hole is
5～1000 row.
The design rule test circuit at fence the most according to claim 5 interval, it is characterised in that:
The horizontally-arranged of described through hole is 12 rows, and described conductor layer is 12.
The design rule test circuit at fence the most according to claim 8 interval, it is characterised in that:
The fence interval respectively 0nm of every exhausting hole and conductive layer, 10nm, 15nm, 20nm, 25nm, 30nm,
35nm、40nm、45nm、50nm、55nm、60nm。
The design rule test circuit at fence the most according to claim 5 interval, it is characterised in that:
Described MOSFET is N-type MOSFET or p-type MOSFET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210155011.8A CN103426866B (en) | 2012-05-17 | 2012-05-17 | The design rule test circuit at fence interval |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210155011.8A CN103426866B (en) | 2012-05-17 | 2012-05-17 | The design rule test circuit at fence interval |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103426866A CN103426866A (en) | 2013-12-04 |
| CN103426866B true CN103426866B (en) | 2016-08-31 |
Family
ID=49651389
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210155011.8A Active CN103426866B (en) | 2012-05-17 | 2012-05-17 | The design rule test circuit at fence interval |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103426866B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104931759B (en) * | 2014-03-21 | 2018-07-06 | 中芯国际集成电路制造(上海)有限公司 | A kind of test circuit and test method of standard block leakage current |
| CN105206545B (en) * | 2015-08-21 | 2017-12-22 | 杭州广立微电子有限公司 | A kind of high density integrated circuit test chip of alternative configuration connection and preparation method thereof |
| CN105743451B (en) * | 2016-02-03 | 2018-11-06 | 宜确半导体（苏州）有限公司 | A kind of radio-frequency power amplifier domain and radio-frequency power amplifier |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6536023B1 (en) * | 2000-07-03 | 2003-03-18 | Cadence Design Systems, Inc. | Method and system for hierarchical metal-end, enclosure and exposure checking |
| US7380227B1 (en) * | 2005-10-28 | 2008-05-27 | Sun Microsystems, Inc. | Automated correction of asymmetric enclosure rule violations in a design layout |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6804808B2 (en) * | 2002-09-30 | 2004-10-12 | Sun Microsystems, Inc. | Redundant via rule check in a multi-wide object class design layout |
| US7007258B2 (en) * | 2003-06-13 | 2006-02-28 | Sun Microsystems, Inc. | Method, apparatus, and computer program product for generation of a via array within a fill area of a design layout |
| US7519929B2 (en) * | 2006-06-23 | 2009-04-14 | Sun Microsystems, Inc. | Method and computer program product for interlayer connection of arbitrarily complex shapes under asymmetric via enclosure rules |
-
2012
- 2012-05-17 CN CN201210155011.8A patent/CN103426866B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6536023B1 (en) * | 2000-07-03 | 2003-03-18 | Cadence Design Systems, Inc. | Method and system for hierarchical metal-end, enclosure and exposure checking |
| US7380227B1 (en) * | 2005-10-28 | 2008-05-27 | Sun Microsystems, Inc. | Automated correction of asymmetric enclosure rule violations in a design layout |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103426866A (en) | 2013-12-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102522386B (en) | Gate-oxidizing-layer interface-trap density-testing structure and testing method | |
| JP4512125B2 (en) | Semiconductor package group for detecting stress distribution and method for detecting stress distribution of semiconductor package using the same | |
| US9018968B2 (en) | Method for testing density and location of gate dielectric layer trap of semiconductor device | |
| CN103941172B (en) | Semiconductor test apparatus and method of testing | |
| CN105223420B (en) | For measuring the TFT of contact resistance and the measuring method of contact resistance | |
| CN104218027B (en) | Semiconductor test structure and test method thereof | |
| US11205748B2 (en) | 3-contact vertical hall sensor elements connected in a ring and related devices, systems, and methods | |
| CN102157411B (en) | MOSFET element electrology characteristic variation measuring method | |
| CN103426866B (en) | The design rule test circuit at fence interval | |
| US10366987B2 (en) | Methods and apparatus for compensation and current spreading correction in shared drain multi-channel load switch | |
| CN104658940A (en) | Structure for measuring electrical properties of FinFET (fin field-effect transistor) | |
| US20140354325A1 (en) | Semiconductor layout structure and testing method thereof | |
| CN103941171A (en) | Semiconductor test structure and test method | |
| US10816589B2 (en) | Structure and method for testing semiconductor device | |
| CN102339814B (en) | Method and structure for testing metal-oxide-semiconductor field-effect transistor (MOSFET) | |
| CN104101823B (en) | Semi-conductor test structure and method of testing | |
| CN103837809A (en) | IC layout for testing MOSFET matching and test method | |
| US20080197351A1 (en) | Testkey design pattern for gate oxide | |
| CN102769008B (en) | A kind of device surveyed Kelvin test loop increasing unit testing module | |
| Pan et al. | Using NMOS transistors as switches for accuracy and area-efficiency in large-scale addressable test array | |
| CN114509657A (en) | Test unit for improving WAT test precision and test method thereof | |
| US20150070039A1 (en) | Apparatus of measuring semiconductor device | |
| CN112687560A (en) | Device for monitoring temperature of semiconductor element | |
| CN110146800B (en) | Method for measuring gate current and turn-off characteristics of IGCT device | |
| CN208368499U (en) | Semi-conductor test structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |