CN103390609B - Semiconductor device and forming method thereof - Google Patents
Semiconductor device and forming method thereof Download PDFInfo
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- CN103390609B CN103390609B CN201310315000.6A CN201310315000A CN103390609B CN 103390609 B CN103390609 B CN 103390609B CN 201310315000 A CN201310315000 A CN 201310315000A CN 103390609 B CN103390609 B CN 103390609B
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Abstract
A kind of semiconductor device and forming method thereof, this device includes: substrate；It is positioned at the transistor of substrate, including: grid, source electrode and drain electrode；The first interlayer dielectric layer being positioned on substrate and transistor；It is positioned at the first and second conductive plungers of the first interlayer dielectric layer；The first and second interconnection lines being positioned on the first interlayer dielectric layer, first, second interconnection line electrically connects with first, second conductive plunger respectively；It is positioned at the second interlayer dielectric layer on the first interlayer dielectric layer, the first and second interconnection lines；It is positioned at the 3rd conductive plunger of the first and second interlayer dielectric layers；The 3rd interconnection line being positioned on the second interlayer dielectric layer and electrically connect with the 3rd conductive plunger；In first, second, and third conductive plunger, one electrically connect with source electrode, one with drain electrode electrically connect, another electrically connects with grid.This device reduces the parasitic capacitance between the interconnection line being connected with transistor, improves the performance of device.
Description
Technical field
The invention belongs to technical field of semiconductors, particularly relate to a kind of semiconductor device and forming method thereof.
Background technology
Shown in Fig. 1 and Fig. 2, existing rf circuitry includes: substrate 1；It is positioned at the transistor of substrate 1, including: grid
Pole 2, source electrode 3 and drain electrode 4；The first interlayer dielectric layer 5 being positioned on substrate 1 and transistor；It is positioned at the first interlayer dielectric layer 5
First conductive plunger 7A, the second conductive plunger 7B and the 3rd conductive plunger 7C, the first conductive plunger 7A electrically connects with grid 2, the
Two conductive plunger 7B electrically connect with source electrode 3, and the 3rd conductive plunger 7C electrically connects with drain electrode 4；It is positioned on the first interlayer dielectric layer 5
First interconnection line 6A, the second interconnection line 6B and the 3rd interconnection line 6C, three is positioned at same layer, the first interconnection line 6A and first conduction
Connector 7A electrically connects, the second interconnection line 6B and the second conductive plunger 7B electrical connection, the 3rd interconnection line 6C and the 3rd conductive plunger 7C
Electrical connection；It is positioned at the second layer on the first interconnection line 6A, the second interconnection line 6B, the 3rd interconnection line 6C and the first interlayer dielectric layer 5
Between dielectric layer 8.
During radio circuit work, radiofrequency signal can send via other interconnection lines (not shown) above the second interconnection line 6B
To the second interconnection line 6B, received by the 3rd interconnection line 6C again, or, radiofrequency signal can be via other above the 3rd interconnection line 6C
Interconnection line (not shown) sends to the 3rd interconnection line 6C, is received by the second interconnection line 6B.
But, find in actual applications, this radio circuit exist serious radio frequency signal leakage phenomenon, reduces and penetrate
The performance of frequency circuit.
Summary of the invention
The problem to be solved in the present invention is: there is serious radio frequency signal leakage phenomenon in radio circuit, reduces radio frequency
The performance of circuit.
For solving the problems referred to above, the invention provides a kind of semiconductor device, including:
Substrate；
It is positioned at the transistor of substrate, including: grid, source electrode and drain electrode；
The first interlayer dielectric layer being positioned on described substrate and transistor；
It is positioned at the first conductive plunger and second conductive plunger of described first interlayer dielectric layer；
It is positioned at the first interconnection line on described first interlayer dielectric layer and the second interconnection line, described first interconnection line and first
Conductive plunger electrically connects, described second interconnection line and the electrical connection of the second conductive plunger；
It is positioned at the second interlayer dielectric layer on described first interlayer dielectric layer, the first interconnection line and the second interconnection line；
It is positioned at the 3rd conductive plunger of described first interlayer dielectric layer and the second interlayer dielectric layer；
Being positioned at the 3rd interconnection line on described second interlayer dielectric layer, described 3rd interconnection line and the 3rd conductive plunger are electrically connected
Connect；
In described first conductive plunger, the second conductive plunger and the 3rd conductive plunger, one electrically connect with described source electrode, one
Individual and described drain electrode electrically connects, another electrically connects with described grid.
Optionally, described semiconductor device is radio-frequency (RF) switch.
Optionally, also include: be positioned at the 4th conductive plunger and the 5th conductive plunger of described second interlayer dielectric layer, institute
State the 4th conductive plunger and the electrical connection of the first interconnection line, described 5th conductive plunger and the electrical connection of the second interconnection line；
It is positioned at the 4th interconnection line on described second interlayer dielectric layer and the 5th interconnection line, described 4th interconnection line and the 4th
Conductive plunger electrically connects, described 5th interconnection line and the electrical connection of the 5th conductive plunger.
It addition, present invention also offers the forming method of a kind of semiconductor device, including:
Substrate is provided；
Forming the transistor being positioned at described substrate, described transistor includes: grid, source electrode and drain electrode；
Described substrate and transistor are formed the first interlayer dielectric layer；
The first conductive plunger and the second conductive plunger is formed in described first interlayer dielectric layer；
Described first interlayer dielectric layer is formed the first interconnection line and the second interconnection line, described first interconnection line and first
Conductive plunger electrically connects, described second interconnection line and the electrical connection of the second conductive plunger；
Described first interconnection line, the second interconnection line and the first interlayer dielectric layer form the second interlayer dielectric layer；
The 3rd conductive plunger is formed in described first interlayer dielectric layer and the second interlayer dielectric layer；
Forming the 3rd interconnection line on described second interlayer dielectric layer, described 3rd interconnection line and the 3rd conductive plunger are electrically connected
Connect；
In described first conductive plunger, the second conductive plunger and the 3rd conductive plunger, one electrically connect with described source electrode, one
Individual and described drain electrode electrically connects, another electrically connects with described grid.
Optionally, before forming described 3rd interconnection line, also include: in described second interlayer dielectric layer, form the 4th lead
Electric plug and the 5th conductive plunger, described 4th conductive plunger and the electrical connection of the first interconnection line, described 5th conductive plunger and the
Two interconnection line electrical connections；
Formed while described 3rd interconnection line, on described second interlayer dielectric layer, also forming the 4th interconnection line and the
Five interconnection lines, described 4th interconnection line and the electrical connection of the 4th conductive plunger, described 5th interconnection line and the 5th conductive plunger are electrically connected
Connect.
Optionally, the forming method of described 3rd conductive plunger, the 4th conductive plunger and the 5th conductive plunger includes:
Described second interlayer dielectric layer is carried out the first etching, to form the first hole exposing described first interconnection line, and
Expose the second hole of described second interconnection line；
Described second interlayer dielectric layer and the first interlayer dielectric layer are carried out the second etching, to form the 3rd hole；
Filler metal in described first hole, the second hole and the 3rd hole, the first hole being filled with metal is that the 4th conduction is inserted
Plug, the second hole being filled with metal is the 5th conductive plunger, and the 3rd hole being filled with metal is the 3rd conductive plunger.
Optionally, before forming the second interlayer dielectric layer, described first interconnection line and the second interconnection line form etching
Barrier layer；
The forming method of described 3rd conductive plunger, the 4th conductive plunger and the 5th conductive plunger includes:
Described second interlayer dielectric layer forms graphical photoresist layer；
Perform etching for mask with described graphical photoresist layer, expose described the to be formed in the second interlayer dielectric layer
First hole of one interconnection line and expose the second hole of described second interconnection line, is situated between at the second interlayer dielectric layer and the first interlayer simultaneously
The 3rd hole is formed in matter layer；
After removing described graphical photoresist layer, filler metal in described first hole, the second hole and the 3rd hole, fill
The first hole having metal is the 4th conductive plunger, and the second hole being filled with metal is the 5th conductive plunger, is filled with the of metal
Three holes are the 3rd conductive plunger.
Optionally, the material of described etching barrier layer is TiN.
Optionally, the thickness of described first interlayer dielectric layer is 0.5 to 1 micron, the thickness of described second interlayer dielectric layer
It is 0.5 to 1.5 micron.
Compared with prior art, technical scheme has the advantage that
In the semiconductor device, the first interconnection line and the second interconnection line at same layer, the 3rd interconnection line and the first interconnection line,
Second interconnection line is not at same layer: electrically connect with grid at the first interconnection line, the second interconnection line electrically connects with source electrode, the 3rd interconnection
When line electrically connect with drain electrode, the distance increase between the second interconnection line and the 3rd interconnection line, therefore, the second interconnection line and the 3rd mutual
Parasitic capacitance between line reduces, and device performance is had an impact by the parasitic capacitance between the second interconnection line and the 3rd interconnection line
Time, reducing the impact on performance of semiconductor device of the parasitic capacitance between the two, this semiconductor device can be radio circuit,
The leakage of radiofrequency signal can be reduced accordingly；The first interconnection line with drain electrode electrically connect, the second interconnection line electrically connects with source electrode,
When 3rd interconnection line electrically connects with grid, distance between the first interconnection line and the 3rd interconnection line increases, the second interconnection line and the
Distance between three interconnection lines increases, and therefore, the parasitic capacitance between the first interconnection line and the 3rd interconnection line reduces, the second interconnection
Parasitic capacitance between line and the 3rd interconnection line reduces, and the parasitic capacitance between the first interconnection line and the 3rd interconnection line is to device
Performance has an impact, or when device performance is had an impact by the parasitic capacitance between the second interconnection line and the 3rd interconnection line, reduces two
The impact on performance of semiconductor device of the parasitic capacitance between person.
Accompanying drawing explanation
Fig. 1 is the top view of existing a kind of semiconductor device；
Fig. 2 is the profile in AA direction along Fig. 1；
Fig. 3 is the top view of semiconductor device in embodiments of the invention one；
Fig. 4 is the profile in BB direction along Fig. 3；
Fig. 5 is the top view of semiconductor device in embodiments of the invention two；
Fig. 6 is the profile in CC direction along Fig. 5.
Detailed description of the invention
Cause the reason that there is serious radio frequency signal leakage phenomenon in radio circuit as follows:
Amass as it is shown in figure 1, have certain right opposite between the second interconnection line 6B and the 3rd interconnection line 6C, therefore, second
Parasitic capacitance C can be formed between interconnection line 6B and the 3rd interconnection line 6C, cause radiofrequency signal to leak from parasitic capacitance C, and this is proper
It it is just undesirable phenomenon during radio-frequency apparatus uses.When parasitic capacitance C is the biggest, the leakage of radiofrequency signal is the most serious.
In other semiconductor device, if the parasitic capacitance between the first interconnection line and the second interconnection line is to device performance
Have an impact, then if the parasitic capacitance between the first interconnection line and the second interconnection line is big, also can reduce the performance of device.
Equally, if device performance is had an impact by the parasitic capacitance between the first interconnection line and the 3rd interconnection line, then the
If parasitic capacitance between one interconnection line and the 3rd interconnection line is big, also can reduce the performance of device.
In order to solve the problems referred to above, the invention provides a kind of semiconductor device, semiconductor device includes being positioned at same layer
The first interconnection line, the second interconnection line, but the 3rd interconnection line and the first interconnection line, the second interconnection line are positioned at different layers, and first is mutual
In line, the second interconnection line, the 3rd interconnection line, one electrically connects with the source electrode of transistor, and another is electrically connected with the drain electrode of transistor
Connecing, the 3rd electrically connects with the grid of transistor.By increasing between the 3rd interconnection line and the first interconnection line, the second interconnection line
Distance, reduces the parasitic capacitance between the 3rd interconnection line and the first interconnection line, the second interconnection line with this, should such that it is able to reduce
The parasitic capacitance impact on device performance.
In order to the technical term making the present invention is clearer, it is unlikely to affect protection scope of the present invention, in the present invention
The technical term used does defined below: the first interconnection line, the second interconnection line, the 3rd interconnection line refer to the ground floor above transistor
Interconnection line, say, that be the interconnection line electrically connected with transistor by the conductive plunger being directly connected with transistor, and this is mutual
Line contacts with this conductive plunger.
Understandable, below in conjunction with the accompanying drawings to the present invention for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
Specific embodiment be described in detail.
Embodiment one
Parasitic capacitance pair in the semiconductor device of embodiment one, between two interconnection lines electrically connected with source electrode, drain electrode
Performance of semiconductor device impact is bigger.Second interconnection line electrically connects with source electrode, and the 3rd interconnection line electrically connects with drain electrode, and second is mutual
Distance between line and the 3rd interconnection line increases, and accordingly, parasitic capacitance between the two reduces.
As shown in Figure 3 and Figure 4, semiconductor device 100 includes: substrate 110；It is positioned at the transistor of substrate 110, this transistor
Including: the grid 121 being positioned on substrate 110, the source electrode 122 being positioned at substrate 110 and drain electrode 123；It is positioned at substrate 110 and crystal
The first interlayer dielectric layer 130 on pipe；The first conductive plunger 151 and the second conduction that are positioned at the first interlayer dielectric layer 130 are inserted
Plug 152, the first conductive plunger 151 electrically connects with grid 121, and the second conductive plunger 152 electrically connects with source electrode 122；It is positioned at first
The first interconnection line 141 and the second interconnection line 142 on interlayer dielectric layer 130, the first interconnection line 141 and the first conductive plunger 151
Electrical connection, the second interconnection line 142 electrically connects with the second conductive plunger 152；It is positioned at first interlayer dielectric layer the 130, first interconnection line
141 and second the second interlayer dielectric layers 160 on interconnection line 142；It is positioned at the first interlayer dielectric layer 130 and the second interlayer dielectric layer
The 3rd conductive plunger 153 in 160, the 3rd conductive plunger 153 electrically connects with drain electrode 123；It is positioned on the second interlayer dielectric layer 160
The 3rd interconnection line 143, the 3rd interconnection line 143 electrically connects with the 3rd conductive plunger 153.
Amass as it is shown on figure 3, the second interconnection line 142 and the 3rd interconnection line 143 have certain right opposite.Described right opposite amasss
Refer to: when the 3rd interconnection line 143 is reduced to the position being positioned at same level with the second interconnection line 142, the most just
To area.
In the present embodiment, owing to the second interconnection line 142 and the 3rd interconnection line 143 are positioned at different layers, therefore, the second interconnection line
142 and the 3rd distances between interconnection line 143 increase, parasitic capacitance C1 between the second interconnection line 142 and the 3rd interconnection line 143
Reduce, reduce the impact on performance of semiconductor device of parasitic capacitance C1 between the two.
Such as, when semiconductor device 100 is applied in radio circuit, radiofrequency signal can be via on the second interconnection line 142
Other layer of interconnection line (not shown) of side sends to the second interconnection line 142, is received by the 3rd interconnection line 143, or, radio frequency is believed
Number can send to the 3rd interconnection line 143, mutual by second again via other floor interconnection lines (not shown) above the 3rd interconnection line 143
Line 142 receives, owing to parasitic capacitance C1 between the second interconnection line 142 and the 3rd interconnection line 143 reduces, therefore from parasitism
Electric capacity C1 leakage radiofrequency signal decrease, and this exactly radio-frequency apparatus use in wish occur.
In the present embodiment, with continued reference to shown in Fig. 3 and Fig. 4, have between the first interconnection line 141 and the 3rd interconnection line 143
Certain right opposite is had to amass.Described right opposite is long-pending to be referred to: be reduced to the 3rd interconnection line 143 be positioned at same with the first interconnection line 141
During the position of one horizontal plane, right opposite between the two amasss.Therefore, can shape between the first interconnection line 141 and the 3rd interconnection line 143
Become parasitic capacitance C2.
In the present embodiment, owing to the first interconnection line 141 and the 3rd interconnection line 143 are positioned at different layers, therefore, the first interconnection line
141 and the 3rd distances between interconnection line 143 increase, parasitic capacitance C2 between the first interconnection line 141 and the 3rd interconnection line 143
Reduce, if device performance is also had an impact by parasitic capacitance C2, then reduce parasitic capacitance C2, it is possible to preferably raising is partly led
The performance of body device.
Therefore, when, in semiconductor device, the parasitic capacitance between two interconnection lines electrically connected with grid, drain electrode is half-and-half led
When the impact of body device performance is bigger, it is also possible to take the technical scheme of embodiment one to reach to improve performance of semiconductor device
Purpose.
In the present embodiment, semiconductor device 100 is radio-frequency (RF) switch.
In the present embodiment, substrate 110 is silicon-on-insulator substrate (SOI).In other embodiments, substrate 110 also may be used
Think that other are suitable for use as the material of substrate.
In the present embodiment, described transistor is mos field effect transistor (MOSFET), grid 121
Being positioned at above substrate 110, source electrode 122 and drain electrode 123 are positioned at substrate 110.But it should be noted that, described transistor should be not only
Being confined to mos field effect transistor, it can also be other kinds of transistor.
In the present embodiment, the material of the first interlayer dielectric layer 130 and the second interlayer dielectric layer 160 is silicon oxide.
In the present embodiment, the material of first interconnection line the 141, second interconnection line 142 and the 3rd interconnection line 143 is aluminum.
In the present embodiment, semiconductor device 100 also includes: the 4th conduction being positioned at the second interlayer dielectric layer 160 is inserted
Filling in and the 5th conductive plunger (not shown), described 4th conductive plunger and the first interconnection line 141 electrically connect, and described 5th conduction is inserted
Plug electrically connects with the second interconnection line 142；It is positioned at the 4th interconnection line on the second interlayer dielectric layer 160 and the 5th interconnection line (is not schemed
Show), described 4th interconnection line and the electrical connection of the 4th conductive plunger, described 5th interconnection line and the electrical connection of the 5th conductive plunger.
Below in conjunction with Fig. 3 and Fig. 4, the forming method of the semiconductor device in embodiment one is described.
First, it is provided that substrate 110, forming the transistor on substrate 110, described transistor includes: grid 121, source electrode 122
With drain electrode 123.
The concrete forming method of transistor is referred to the forming method of existing transistor, does not repeats them here.
Then, substrate 110 and transistor form the first interlayer dielectric layer 130.
In the present embodiment, the material of the first interlayer dielectric layer 130 is silicon oxide, and chemical gaseous phase can be used to deposit
(CVD) method formed from level to level on substrate 110 and transistor between dielectric layer, then carry out cmp (CMP) place
Reason, to form the first interlayer dielectric layer 130 of surface planarisation.In a particular embodiment, the thickness of the first interlayer dielectric layer 130
It it is 0.5 to 1 micron (including end points).
Then, forming the first conductive plunger 151 and the second conductive plunger 152 in the first interlayer dielectric layer 130, first leads
Electric plug 151 electrically connects with grid 121, and the second conductive plunger 152 electrically connects with source electrode 122.
The forming method of the first conductive plunger 151 and the second conductive plunger 152 is referred to the formation of existing conductive plunger
Method, does not repeats them here.
Then, the first interlayer dielectric layer 130 is formed the first interconnection line 141 and the second interconnection line 142, the first interconnection line
141 electrically connect with the first conductive plunger 151, and the second interconnection line 142 electrically connects with the second conductive plunger 152.
The forming method of the first interconnection line 141 and the second interconnection line 142 is referred to the forming method of existing interconnection line,
This repeats no more.
Then, first interconnection line the 141, second interconnection line 142 and the first interlayer dielectric layer 130 are formed the second interlayer to be situated between
Matter layer 160.
In the present embodiment, the material of the second interlayer dielectric layer 160 is silicon oxide, can use the side that chemical gaseous phase deposits
Method formed from level to level on first interconnection line the 141, second interconnection line 142 and the first interlayer dielectric layer 130 between dielectric layer, then enter
Row cmp processes, to form the second interlayer dielectric layer 160 of surface planarisation.In a particular embodiment, the second layer
Between the thickness of dielectric layer 160 be 0.5 to 1.5 micron (including end points).
Then, formation the 3rd conductive plunger 153 in the first interlayer dielectric layer 130 and the second interlayer dielectric layer 160, the 3rd
Conductive plunger 153 electrically connects with drain electrode 123.Then, forming the 3rd interconnection line 143 on the second interlayer dielectric layer 160, the 3rd is mutual
Line 143 electrically connects with the 3rd conductive plunger 153.
The forming method of the 3rd interconnection line 143 is referred to the forming method of existing interconnection line, does not repeats them here.
In the present embodiment, before forming the 3rd interconnection line 143, also include: formed in the second interlayer dielectric layer 160
4th conductive plunger and the 5th conductive plunger (not shown), described 4th conductive plunger and the first interconnection line 141 electrically connect, described
5th conductive plunger and the second interconnection line 142 electrically connect；While forming the 3rd interconnection line 143, also form the 4th interconnection line
With the 5th interconnection line (not shown), the 3rd interconnection line the 143, the 4th interconnection line and the 5th interconnection line be positioned at same layer, the 4th interconnection
Line 144 electrically connects with the 4th conductive plunger, the 5th interconnection line and the electrical connection of the 5th conductive plunger.
In one embodiment, the 3rd conductive plunger the 153, the 4th conductive plunger and the forming method bag of the 5th conductive plunger
Include: the second interlayer dielectric layer 160 is carried out the first etching, to form the first hole exposing the first interconnection line 141, and expose second
Second hole of interconnection line 142；Second interlayer dielectric layer 160 and the first interlayer dielectric layer 130 are carried out the second etching, to form
Three holes；Filler metal in described first hole, the second hole and the 3rd hole, the first hole being filled with metal is the 4th conductive plunger,
The second hole being filled with metal is the 5th conductive plunger, and the 3rd hole being filled with metal is the 3rd conductive plunger 153, described metal
It can be the tungsten layer on bonding coat Ti/TiN and bonding coat.Described first etch step can be in the advance of the second etch step
OK, it is also possible to carry out after the second etch step.
In another embodiment, the 3rd conductive plunger the 153, the 4th conductive plunger and the 5th conductive plunger synchronize to be formed.
In this case, formed before the second interlayer dielectric layer 160, need on the first interconnection line 141 and the second interconnection line 142 shape
Becoming etching barrier layer (not shown), the method forming etching barrier layer includes: form interconnection line on the first interlayer dielectric layer 130
Metal level, and it is positioned at the etching barrier layer on interconnection line metal level；Described etching barrier layer and interconnection line metal level are carved
Erosion, to form the first interconnection line 141 and the second interconnection line 142, and is positioned on the first interconnection line 141 and the second interconnection line 142
Etching barrier layer.
In this case, the 3rd conductive plunger the 153, the 4th conductive plunger and the method bag of the 5th conductive plunger is formed
Include: on the second interlayer dielectric layer 160, form graphical photoresist layer；Carve with described graphical photoresist layer for mask
Erosion, exposes the first hole of the first interconnection line 141 to be formed in the first interlayer dielectric layer 130 and exposes the second interconnection line 142
Second hole, forms the 3rd hole in the second interlayer dielectric layer 160 and the first interlayer dielectric layer 130 simultaneously；Remove described graphically
After photoresist layer, filler metal in described first hole, the second hole and the 3rd hole, being filled with the first hole of metal is the 4th to lead
Electric plug, the second hole being filled with metal is the 5th conductive plunger, and the 3rd hole being filled with metal is the 3rd conductive plunger 153.
In etching process, the etching barrier layer on the first interconnection line 141 and the second interconnection line 142 can be protected first mutual
Line 141 and the second interconnection line 142 are not etched, can according to the depth difference between the 3rd hole and the first hole (or second hole),
And the quarter between interlayer dielectric layer (including the second interlayer dielectric layer 160 and the first interlayer dielectric layer 130) and etching barrier layer
Erosion selects ratio, determines the thickness of etching barrier layer, so that the first interconnection line 141 and the second interconnection line 142 will not be etched.?
In specific embodiment, the material of described etching barrier layer is TiN.
So that perform etching to form the described 3rd to the second interlayer dielectric layer 160 and the first interlayer dielectric layer 130
The technique in hole, and the easier realization of technique of filler metal, need to make described 3rd hole have less depth-to-width ratio, therefore, and should
The thickness sum making the second interlayer dielectric layer 160 and the first interlayer dielectric layer 130 is smaller.In the present embodiment,
The thickness of one interlayer dielectric layer 130 is 0.5 to 1 micron, and the thickness of the second interlayer dielectric layer 160 is 0.5 to 1.5 micron, permissible
Reach this purpose.
Embodiment two
Parasitic capacitance pair in the semiconductor device of embodiment two, between two interconnection lines electrically connected with grid, drain electrode
Performance of semiconductor device impact is bigger.First interconnection line electrically connects with drain electrode, and the 3rd interconnection line electrically connects with grid, and first is mutual
Distance between line and the 3rd interconnection line increases, and accordingly, parasitic capacitance between the two reduces.
Difference between the present embodiment and embodiment one is: as shown in Figure 6, the 3rd conductive plunger 153 and grid 121 electricity
Connecting, the first conductive plunger 151 electrically connects with drain electrode 123, and the second conductive plunger 152 electrically connects with source electrode 122；As it is shown in figure 5,
3rd interconnection line 143 and the first interconnection line 141 have the first certain right opposite and amass, the 3rd interconnection line 143 and the second interconnection line
142 have the second certain right opposite amasss, and described first right opposite is long-pending to be referred to: be reduced to mutual with first by the 3rd interconnection line 143
When line 141 is positioned at the position of same level, right opposite between the two amasss；Described second right opposite is long-pending to be referred to: by the 3rd
When interconnection line 143 is reduced to the position being positioned at same level with the second interconnection line 142, right opposite between the two amasss.
Therefore, parasitic capacitance C2 can be formed between the first interconnection line 141 and the 3rd interconnection line 143, the second interconnection line 142 He
Parasitic capacitance C1 can be formed between 3rd interconnection line 143.
In embodiment two, as shown in Figure 5 and Figure 6, owing to the second interconnection line 142 and the 3rd interconnection line 143 are positioned at different layers,
Therefore, the distance between the second interconnection line 142 and the 3rd interconnection line 143 increases, the second interconnection line 142 and the 3rd interconnection line 143
Between parasitic capacitance C1 reduce, if device performance is also had an impact by parasitic capacitance C1, then reduce parasitic capacitance C1, so that it may
Preferably to improve the performance of semiconductor device.
Therefore, when, in semiconductor device, the parasitic capacitance between two interconnection lines electrically connected with grid, source electrode is half-and-half led
When the impact of body device performance is bigger, it is also possible to take the technical scheme of embodiment two to reach to improve performance of semiconductor device
Purpose.
Those skilled in the art can be according to the structure difference of semiconductor device between embodiment two and embodiment one, to reality
Execute the method for forming semiconductor devices in example one and make corresponding adjustment, to obtain the formation side of semiconductor device in embodiment two
Method, does not repeats them here.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art, without departing from this
In the spirit and scope of invention, all can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Limit in the range of standard.
Claims (9)
1. a semiconductor device, it is characterised in that including:
Substrate；
It is positioned at the transistor of described substrate, including: grid, source electrode and drain electrode；
The first interlayer dielectric layer being positioned on described substrate and transistor；
It is positioned at the first conductive plunger and second conductive plunger of described first interlayer dielectric layer；
It is positioned at the first interconnection line on described first interlayer dielectric layer and the second interconnection line, described first interconnection line and the first conduction
Connector electrically connects, and described second interconnection line and the electrical connection of the second conductive plunger, described first interconnection line and the second interconnection line are positioned at
Same layer；
It is positioned at the second interlayer dielectric layer on described first interlayer dielectric layer, the first interconnection line and the second interconnection line；
It is positioned at the 3rd conductive plunger of described first interlayer dielectric layer and the second interlayer dielectric layer；
It is positioned at the 3rd interconnection line on described second interlayer dielectric layer, described 3rd interconnection line and the electrical connection of the 3rd conductive plunger；
In described first conductive plunger, the second conductive plunger and the 3rd conductive plunger, one electrically connect with described source electrode, one with
Described drain electrode electrically connects, another electrically connects with described grid.
2. semiconductor device as claimed in claim 1, it is characterised in that described semiconductor device is radio-frequency (RF) switch.
3. semiconductor device as claimed in claim 1, it is characterised in that also include: be positioned at described second interlayer dielectric layer
The 4th conductive plunger and the 5th conductive plunger, described 4th conductive plunger and the first interconnection line electrical connection, described 5th conduction
Connector and the electrical connection of the second interconnection line；
It is positioned at the 4th interconnection line on described second interlayer dielectric layer and the 5th interconnection line, described 4th interconnection line and the 4th conduction
Connector electrically connects, described 5th interconnection line and the electrical connection of the 5th conductive plunger.
4. the forming method of a semiconductor device, it is characterised in that including:
Substrate is provided；
Forming the transistor being positioned at described substrate, described transistor includes: grid, source electrode and drain electrode；
Described substrate and transistor are formed the first interlayer dielectric layer；
The first conductive plunger and the second conductive plunger is formed in described first interlayer dielectric layer；
Described first interlayer dielectric layer is formed the first interconnection line and the second interconnection line, described first interconnection line and the first conduction
Connector electrically connects, and described second interconnection line and the electrical connection of the second conductive plunger, described first interconnection line and the second interconnection line are positioned at
Same layer；
Described first interconnection line, the second interconnection line and the first interlayer dielectric layer form the second interlayer dielectric layer；
The 3rd conductive plunger is formed in described first interlayer dielectric layer and the second interlayer dielectric layer；
Described second interlayer dielectric layer is formed the 3rd interconnection line, described 3rd interconnection line and the electrical connection of the 3rd conductive plunger；
In described first conductive plunger, the second conductive plunger and the 3rd conductive plunger, one electrically connect with described source electrode, one with
Described drain electrode electrically connects, another electrically connects with described grid.
5. forming method as claimed in claim 4, it is characterised in that before forming described 3rd interconnection line,
Also include: in described second interlayer dielectric layer, form the 4th conductive plunger and the 5th conductive plunger, described 4th conduction
Connector and the electrical connection of the first interconnection line, described 5th conductive plunger and the electrical connection of the second interconnection line；
Formed while described 3rd interconnection line, on described second interlayer dielectric layer, also forming the 4th interconnection line and the 5th mutual
Line, described 4th interconnection line and the electrical connection of the 4th conductive plunger, described 5th interconnection line and the electrical connection of the 5th conductive plunger.
6. forming method as claimed in claim 5, it is characterised in that described 3rd conductive plunger, the 4th conductive plunger and the
The forming method of five conductive plungers includes:
Described second interlayer dielectric layer is carried out the first etching, to form the first hole exposing described first interconnection line, and exposes
Second hole of described second interconnection line；
Described second interlayer dielectric layer and the first interlayer dielectric layer are carried out the second etching, to form the 3rd hole；
Filler metal in described first hole, the second hole and the 3rd hole, the first hole being filled with metal is the 4th conductive plunger, fills out
The second hole being filled with metal is the 5th conductive plunger, and the 3rd hole being filled with metal is the 3rd conductive plunger.
7. forming method as claimed in claim 5, it is characterised in that before forming the second interlayer dielectric layer,
Described first interconnection line and the second interconnection line are formed etching barrier layer；
The forming method of described 3rd conductive plunger, the 4th conductive plunger and the 5th conductive plunger includes:
Described second interlayer dielectric layer forms graphical photoresist layer；
Perform etching with described graphical photoresist layer for mask, with formed in the second interlayer dielectric layer expose described first mutual
First hole of line and expose the second hole of described second interconnection line, simultaneously at the second interlayer dielectric layer and the first interlayer dielectric layer
Interior formation the 3rd hole；
After removing described graphical photoresist layer, filler metal in described first hole, the second hole and the 3rd hole, it is filled with gold
The first hole belonged to is the 4th conductive plunger, and the second hole being filled with metal is the 5th conductive plunger, is filled with the 3rd hole of metal
It it is the 3rd conductive plunger.
8. forming method as claimed in claim 7, it is characterised in that the material of described etching barrier layer is TiN.
9. forming method as claimed in claim 4, it is characterised in that the thickness of described first interlayer dielectric layer is 0.5 to 1 micro-
Rice, the thickness of described second interlayer dielectric layer is 0.5 to 1.5 micron.
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| CN101872745A (en) * | 2009-04-24 | 2010-10-27 | 海力士半导体有限公司 | Semiconductor memory device and method for manufacturing the same |
| CN102903698A (en) * | 2012-10-25 | 2013-01-30 | 上海宏力半导体制造有限公司 | Semiconductor device and integrated circuit |
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| CN101246873A (en) * | 2007-02-13 | 2008-08-20 | 台湾积体电路制造股份有限公司 | Integrated circuit structure |
| CN101872745A (en) * | 2009-04-24 | 2010-10-27 | 海力士半导体有限公司 | Semiconductor memory device and method for manufacturing the same |
| CN102903698A (en) * | 2012-10-25 | 2013-01-30 | 上海宏力半导体制造有限公司 | Semiconductor device and integrated circuit |
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