CN103376764B - The power management logic unit of many logical blocks power management integrated circuit - Google Patents

Abstract

A kind of many logical blocks power management integrated circuit (MTPMIC) comprise a processor, fault secure circuit, the first terminal, one drive the driver of described the first terminal, one second terminal and export a digital detection signal, show whether to detect the testing circuit of predetermined condition on the second terminal.Processor can make fault secure circuit to pass through one of multi signal function comprising digital detection signal at Down Drive afterwards to fault secure circuit programming.Its function is programmed by processor.In one embodiment, as testing circuit detects predetermined condition on the second terminal, so fault secure circuit closes all high-side driver of MTPMIC and all low-end drivers by independent, and does not need to come any input of self processor.

Description

The power management logic unit of many logical blocks power management integrated circuit

Technical field

Content of the present invention relates to general power management integrated circuit technical field.

Background technology

There is a variety of microcontroller integrated circuit that can be used for power transfer and Energy control application at present.Existing microcontroller generally includes the processor of a tape input/lead-out terminal, possesses simple input/output function, or has an analog-digital converter (ADC) and/or a digital analog converter (DAC).Such microcontroller to be used in general power control system, generally need certain power supply to provide voltage, thus can use power under the control of the micro-controller or change.Microcontroller self circuit also must pass through DC-voltage supply.Be generally the voltage required for other modules of DC voltage and system that microcontroller powers different.Therefore a part for the normally total microprocessor controls system design task of the design of power supply or power pack.Power supply is not only total system and powers simultaneously for microcontroller circuit is powered yet.

If microcontroller can autonomous operation, so have the slip-stick artist of microcontroller programming background usually can design and build the ball bearing made using of powering for this microcontroller, but these slip-stick artists often lack the experience for the more complicated Switching Power Supply of overall microprocessor controls system power supply design.Meanwhile, they do not know how to design the analog power interface circuit being coupled required by microcontroller and monitoring or control system yet.In addition, the microcontroller of the most applicable application how is selected also to be a difficult problem.Alternative specific microcontroller used in system or microcontroller series may be limited.If have selected a specific microcontroller series, need again afterwards to modify to systemic-function, the so initial microcontroller series selected just may cannot meet the system needs after upgrading.If must change the microcontroller of system centre position, so, the time and money of flower on selected microcontroller just may have been wasted.Therefore, simultaneously also for other reasons, be never part nothing the matter concerning design and development whole system a common slip-stick artist under many circumstances.The demand reducing microcontroller power switch system design difficulty has also just been arisen at the historic moment.

Summary of the invention

A kind of many logical blocks power management integrated circuit (MTPMIC) comprise multiple power management integrated circuit and power management IC (PMIC) logical block.In one example, these power management IC logical blocks comprise a MCU/ADC logical block, a driver management logical block, a power management logic unit, and a signal management logical block.When multiple power management IC logical block is together as MTPMIC a part of, which constitute a STD bus.Each logical block has resolving circuit and a configuration register.Configuration information in logical block configuration register determines the resolving circuit of how configuration logic unit.Processor in MCU/ADC logical block is coupled with STD bus.This processor can be inscribed via on the configuration register of STD bus in logical block required arbitrarily, and is configured by this method the resolving circuit in multiple logical block and reconfigures.

Power management logic unit comprises the configurable pulse width modulator that a group is called configurable switch power supply pulse width modulator (CSPSPWM).Except CSPSPWM, power management logic unit also comprises a HV Terminal VHM, an internal voltage regulator of powering for CSPSPWM, a driver output terminals DRM, driver output signal is sent to the coupled driver circuit of driver output terminals DRM from CSPSPWM Received signal strength by one, a power supply terminal VP that can be coupled with the error amplifier of CSPSPWM, a configuration register, and other assemblies.The configuration information be stored in configuration register determines the configuration of CSPSPWM.Power management logic unit can be configured by different way together with a small amount of external module (beyond MTPMIC), thus the one realized in multiple switching power circuit, such as: buck converter, high pressure drop pressure type transducer, direction flyback converter, and boost converter.

A novel part of the present invention is, the terminal of power management logic unit and external circuit (beyond MTPMIC integrated circuit) are coupled, thus allow power management logic unit and external circuit can together with operate as Switching Power Supply.The total system comprising MTPMIC is not powered in an initial condition.Afterwards, the voltage from outside is applied on MTPMIC by HV Terminal VHM.This application example, may relate to coupling one connect without the DC voltage of harmonizing or by one since high pressure spot is linked to the switch activated resistance of HV Terminal VHM.Then, the internal voltage regulator of CSPSPWM obtains the voltage from this external power source, and provides operate power for the remainder circuit of CSPSPWM.Power once internal voltage regulator is CSPSPWM, CSPSPWM just starts working as Switching Power Supply together with drive circuit and external module.

In switch process, CSPSPWM imposes pulse under clean boot pattern the main switch of Switching Power Supply.Under clean boot pattern, main switch is subjected to duration impulse, and this pulse possesses fixing low switching frequency and Fixed Time Interval.When Switching Power Supply is run under this safe mode, the supply voltage VP on terminal VP rises.In the meantime, CSPSPWM decides current sense method according to the configuration of integrated circuit external circuit and the method for operation.Supply voltage VP on terminal VP is the output supply voltage of Switching Power Supply.In the secure mode after short time work, the supply voltage VP on terminal VP can reach enough high, thus CSPSPWM can be worked in the normal operating mode.In the normal operating mode, main external switch carrys out switch (higher than start-up mode) with higher inversion frequency, and have adjusted pulse width.

Supply voltage VP is that linear voltage regulator circuit in power management logic unit is powered afterwards, produces VCORE voltage.This VCORE voltage is supplied to the processor in MCU/ADC logical block by the wire of STD bus.Therefore, processor obtains power and starts to perform instruction.In one embodiment, performing instruction allows processor inscribe via in the configuration register of STD bus in power management logic unit.When power supply is high pressure, after VP voltage rise is more than VHM voltage, supply voltage VP also can be used to supplementary VHM voltage by external diode.

In power-conversion application, driver in driver management logical block is coupled to control external power source circuit, input circuit simultaneously as the differential amplifier in signal management logical block and signal event generator is coupled, and detects and monitor the operation of external power source circuit.Processor receives the information of the relevant external power source circuit operation from signal management logical block, information is processed, and the driver of tackling mutually in actuator tube reason logical block controls, thus in control loop, outside power circuit is suitably controlled.Switching Power Supply is not only MTPMIC power itself (CSPSPWM of power management logic unit is a part wherein), and it is also for the external power source circuit obtaining controlling is powered simultaneously.In one example, CSPSPWM change-over switch power supply (CSPSPWM and driver are wherein a part), Switching Power Supply provides at least as many with MTPMIC autophage electric power for the external power source circuit controlled by MTPMIC thus.In one example, external power source circuit at least obtains one watt of power.

In one example, driver management logical block comprises a high-side driver output circuit.High-side driver output circuit has a level shifting circuit and a driver.If high-end lead-out terminal will reach high voltage, so the voltage on high-end lead-out terminal and second terminal just matches by driver, if high-end input terminal will realize low-voltage, so the voltage on high-end lead-out terminal and the 3rd terminal just matches by driver.In another example, signal management logical block comprises a differential amplifier circuit, here first input of coupled differential amplifier circuit is to receive first signal from first terminal, and second input of coupled differential amplifier circuit is to receive second signal from second terminal simultaneously.An analog signal output of differential amplifier can be supplied to the input lead of the analog to digital converter (ADC) in MCU/ADC logical block thus allow ADC can by analog signal figure.In another example, the drive circuit of driving CSPSPWM driver output terminals DRM works under caning be passed through and being configured in pulse pull-down pattern.Whether, in another example, CSPSPWM comprises a current sensing circuit, be coupled with deciding current-sense terminal CSM under the configuration of high-side current sensing or the configuration of low-side current sensing.In another example, CSPSPWM has an error amplifier and a digital to analog converter (DAC), wherein error amplifier control in first operational mode an error node on voltage, and DAC controls the voltage in the second operational mode on an error node.In the second operational mode, the processor in MCU/ADC logic power, by via STD bus, writes a multi-bit digital value, and is transported in the input of DAC numeral, thus the voltage of departure signal amplifier output node.

A novel part of the present invention is; the power management integrated circuit of logical block more than (MTPMIC) comprises a processor, a fault secure circuit, a first terminal, one second terminal and testing circuit, and this circuit exports a digital detection signal and shows whether predetermined condition detected on the second terminal.Driver is controlled by processor, and processor in the drive, after performing processor executable program, can determine to open or close external transistor by control and drive system thus a suitable control signal is sent on the first terminal.Processor can also be programmed to fault secure circuit, makes the multi signal value function of fault secure circuit, comprises digital detection signal, can stop driver afterwards.This function is programmed by processor.In one embodiment, if testing circuit detects predetermined condition on the second terminal, so fault secure circuit can promptly stop all high-side driver of MTPMIC and all low-end drivers voluntarily automatically, and without the need to carrying out the input of self processor.

Foregoing is summary of the invention, namely detailed content is simplified as required, concludes and abridges; Therefore content of the present invention use for illustrative purposes only.Other methods, structure and details refer to following detailed description.Scope of the present invention should not determined by foregoing invention content.Invention definition is see claims.

Accompanying drawing explanation

Appended drawing, wherein correlated digital illustrates associated component, in order to illustrate invention.

Fig. 1 relates to the schematic diagram of the system 1 of many logical blocks power management integrated circuit (MTPMIC) 2;

The simplification concept map of Tu2Shi MTPMIC2 total arrangement, illustrates in MTPMIC design process, how PMIC logical block to be inserted simply from MTPMIC and extracts;

Fig. 3 is the reduced graph of the MTPMIC2 be coupled with integrated antenna package by wire bond;

Fig. 4 A, 4B, 4C constitute the schematic diagram that large figure Fig. 4, Fig. 4 are MTPMIC2 together with 4D;

It is the schematic diagram applied about the brushless motor controller of Fig. 4 MTPMIC2 that Fig. 5 A, 5B, 5C constitute large figure Fig. 5, Fig. 5 together with 5D;

It is the schematic diagram applied about the LED driver of Fig. 4 MTPMIC2 that Fig. 6 A, 6B, 6C constitute large figure Fig. 6, Fig. 6 together with 6D;

Fig. 7 is the schematic diagram of system 500, and wherein power management logic unit and external module constitute high pressure drop pressure converter power supply;

Fig. 8 is the schematic diagram of system 600, and wherein power management logic unit and external module constitute direction flyback converter power supply;

Fig. 9 is the schematic diagram of system 700, and wherein driver management logical block is coupled to control multiple LED string;

Figure 10 is the schematic diagram of system 800, and wherein external circuit manages logical block with the driver of MTPMIC2 and is coupled, and constitutes a H bridge inverter;

Figure 11 is the schematic diagram of system 900, and wherein the driver of external circuit and MTPMIC2 manages logical block and is coupled, and constitutes a wireless charger;

The table of Figure 12 illustrates the configuration bit in the configuration register 27 and 28 of MCU/ADC logical block;

The table of Figure 13 illustrates the configuration bit in the configuration register 29 of driver management logical block;

The table of Figure 14 illustrates the configuration bit of configuration register 30 in power management logic unit;

The table of Figure 15 illustrates the configuration bit in the configuration register 31 of signal management logical block;

Figure 16 is the wiring diagram of CSM mode detection module 130;

Figure 17 is the process flow diagram of the method 1000 provided from Point of Innovation of the present invention;

Figure 18 is another embodiment schematic diagram of the driver management logical block of many logical blocks power management integrated circuit (MTPMIC), in order to illustrate that the function how fault secure circuit determines according to processor makes driver forbid;

Figure 19 is the detailed structure view of failure processor;

Figure 20 is the operation schematic diagram of function selector circuit;

Figure 21 is the process flow diagram of the method 2000 provided according to Point of Innovation of the present invention.

Embodiment

Fig. 1 relates to the schematic diagram of the system 1 of many logical blocks power management integrated circuit (MTPMIC) 2.Information 5, debugged program 6 and development kit software 7 that server 3 stores program coding 4, uses MTPMIC2 to design as reference.Server 3 can store a large amount of reference design adopting MTPMIC2, and here each reference design and corresponding program coding have all been done by the power supply company producing MTPMIC2 and runtime server 3 and verified thoroughly.

Computing machine 8 is matched by network 9 and server 3.The website that user uses computing machine 8 to enter to be supported by server 3 is also loaded with the information of closing MTPMIC2 and reference design up and down from website.Use this information, user can assemble reference design or other user's particular electrical circuit based on reference design.In the presented embodiments, user assembled circuit 10 i.e. reference design.Circuit 10 comprises the external hardware circuit 11 of MTPMIC2 and respective amount.MTPMIC2 and other circuit 11 are all as figure is arranged on printed circuit board (pcb) 12.It is two-way communication between circuit 10 and subscriber computer 8.In the illustrated embodiment, circuit 10 participates in the two-way communication of the dongle using SPI or I2C agreement by a dongle 13 from USB to the SPI/I2C .MTPMIC2 that to be coupled with the USB port 14 of subscriber computer 8, and computing machine 8 participates in the two-way communication of the dongle using usb protocol.The function of USB to SPI/I2C dongle 13 just looks like be a bus protocol translating equipment.

User also uses computing machine 8 to download in computing machine 8 by program coding 4 by network 9, then enters MTPMIC2 by USB-TO-SPI/I2C dongle 13.In one embodiment, coding 4 is the special codings in the program internal memory of the MCU/ADC logical block downloaded in MTPMIC.MCU/ADC logical block comprises the processor that can read internal memory.Processor performs the program coding 4 downloaded, thus control MTPMIC2 and circuit 11, allow them normally work together.

In addition, server 3 stores development kit program 7.User downloads and installs development kit program 7 in computing machine 8.User has also downloaded debugged program 6 in MTPMIC2.The development kit program 7 that computing machine 8 works provides graphic user interface, thus user can be monitored circuit operation.Debugged program 6 is performed by the processor in MTPMIC2, allow the circuit in MTPMIC2 carry out the specific node in monitoring circuit 10 and the data report that circuit is run to the kit program 7 worked on computing machine 8.By this framework, user can stop alternately as required and activate the specific part in circuit 10.By using development kit, user can allow the electric current in kit writing circuit on specific node and voltage data show on screen 15 and record data.Program coding 4 can the hardware of driver circuit 10 in the secure mode, and in this mode, even if the hardware of circuit 10 is equipped with problem, the assembly of circuit also can not cause and self damage.Once the failture evacuation of circuit 10, MTPMIC2 can reload other codings thus make MTPMIC2 when just can running without the need to when Additional debug program.

The simplification concept map of Tu2Shi MTPMIC2 total arrangement.MTPMIC2 is the rectangle integrated circuit (IC) chip in integrated antenna package 16.On its four edges of integrated antenna package 16, there is row's terminal on every limit.A terminal reference of encapsulation top is numbered 17.MTPMIC2 self comprises multiple power management integrated circuit (PMIC) logical block part.These PMIC parts comprise MCU/ADC logical block 18, driver management logical block 19, power management logic unit 20, and a signal management logical block 21.MCU/ADC logical block 18 comprises a MCU(micro controller unit) submodule 22 and analog to digital converter (ADC) submodule 23.

Rightmost one arrange each PMIC logical block have one can conduct digital signals, simulating signal and power signal conductor bus distribute.Bus assignment 24A is the bus assignment of driver management logical block 19.Bus assignment 24B is the bus assignment of power management logic unit 20.Bus assignment 24C is the bus assignment of signal management logical block 21.Bus assignment in each logical block is placed as shown in the figure, if therefore each row in logical block all correctly arrange, so the bus assignment of neighboring logic cell will line up a team, composition STD bus 24.In such as illustrated example, standardized bus 24 vertically extends along the left side edge of driver the management left margin of logical block, the left margin of power management logic unit and signal management logical block.The MCU/ADC18 in left side and STD bus 24 are by configuration register 27 and 28 interfaces in the standard fashion.Each PMIC logical block of right side file also has such configuration register and STD bus to be coupled.Configuration register 29 is configuration registers of driver management logical block 19.Configuration register 30 is configuration registers of power management logic unit 20.Configuration register 31 is configuration registers of signal management logical block 21.

Each individual bit in each such configuration register all may comprise a volatile cells and a non-volatile cell, or as can read in register in ordinary processor, only may simply comprise a volatile cells.If configuration bit has a non-volatile cell, so when MTPMIC2 electric power starting, data content in non-volatile cell can be automatically transferred in volatile cells, and then the data of volatile cells export other circuit be used in configuration logic unit.Single configuration bit in these configuration registers all can be read and write via STD bus.

Processor 32 administrative standard bus 24 in MCU/ADC18.By bus interface 42, processor 32 is inscribed in any configuration register of any logical block by STD bus.Understand other information of logical block framework, STD bus and associated configuration register thereof, refer to: 1) US patent number 7,788,608, MicrobumpFunctionAssignmentInABuckConverter, date saved on October 29th, 2007, author: Huynhetal., 2) US patent number 7,581,198, MethodandSystemfortheModularDesignandLayoutofIntegratedC ircuits, date saved on October 7th, 2006, author Huynhetal; 3) U.S. Provisional Application 60/850,359, Single-PolyEEPROMStructureForBit-WiseWrite/Overwrite, date saved on October 7th, 2006; 4) US patent number 7,869,275, MemoryStructureCapableofBit-WiseWriteorOverwrite, date saved on July 31st, 2007, author Grantetal.; And 5) US patent number 7,904,864, InterconnectLayerofaModularlyDesignedAnalogIntegratedCir cuit, date saved on October 29th, 2007, author Huynhetal; 6) U.S. Patent Application Serial Number 11/452,713, SystemforaScaleableandProgrammablePowerManagementIntegra tedCircuit, date saved on June 13rd, 2006, author Huynh; And 7) U.S.Provisional Serial 60/691,721, SystemforaScaleableandProgrammablePowerManagementIntegra tedCircuit, date saved on June 16th, 2005, the complete name that author Huynh(encloses these patent documents is herein for reference).

Except STD bus, MTPMIC2 also comprises a processor local bus 34.Multiple circuit in MCU submodule 22 and ADC submodule 23 is coupled with this processor local bus 34.Processor 32 reads these different circuit by processor local bus 34, and simultaneous processor 32 also inscribes these different circuit by processor local bus 34.

There is the PMIC logical block of number of different types by STD bus 24 interface each other.When designing integrated circuit, the logical block layout of the PMIC logical block of the given PMIC of the right file can be removed, and another logical block layout of the another kind of PMIC logical block that replaces.A PMIC logical block layout comprises the local message of all integrated circuit layers of logical block, comprises all upper layer metallization layers.PMIC logical block in the file of the right can inject very easily when designing and extract from integrated circuit, thus allows final MTPMIC integrated circuit have required PMIC logical block and required function.Arrow 35 represents that in this design process, insert driver manages logical block 19.Use the same method and can to plug the PMIC logical block in the file of right side when designing integrated circuit, same, the PMIC logical block in the file of left side also can plug when designing integrated circuit.On the left of this, the embodiment of file logical block comprises with the logical block of communication bus interface circuit and the logical block with additional processor internal memory.Such as, a communication bus interface circuit PMIC logical block has the USB(USB (universal serial bus) be coupled with processor local bus 34) logical block of controller.

Fig. 3 is the reduced graph of MTPMIC2.Each terminal of PMIC logical block is coupled by the respective terminal of corresponding bonding wire with encapsulation 16.Fig. 3 is reduced graph.In actual package, each terminal is a part for lead frame.Lead frame has a finger assembly to extend inward into integrated circuit from terminal.Bonding wire is as shown in Figure 3 so long and relatively short, and is not welded on the peripheral actual terminal of encapsulation, but is welded in the corresponding finger-like end of terminal.In figure 3,36 the bonding wire be coupled with the terminal (also can be used as backing plate) 84 of MTPMIC2 by package terminal 17 is referred to.

Fig. 4 A, 4B, 4C and 4D are assembled together and constitute the large figure of Fig. 4.How figure main presentation main on the right side of following Fig. 3 4A, 4B, 4C and 4D are assembled together.STD bus 24 comprises data bus DIN [0-7], clock stroboscopic wire (displaying), general-purpose digital signal wire (displaying), other special digital wires (displaying), generic analog signal wire AB [0-4], specialized simulation wire (displaying), fault wire fault [0-1], global clock wire (displaying), ground connection and reference voltage wire (displaying) and other wires.Processor local bus 34 comprises an address bus LOCALBUSADR, a data bus LOCALBUSDATA, and control signal wire LOCALBUSCTRL.Due to the space constraint of drawing, show only the part wire of STD bus 24 and the part wire of processor local bus 34.

mCU/ADC logical block

Fig. 4 A is the reduced graph of MCU/ADC logical block 18.MCU/ADC logical block 18 comprises other modules multiple in processor 32 and figure.In diagram specific embodiment, the vertical extension of STD bus 24 not through MCU/ADC logical block 18, and just along the right edge of logical block 18 along outer vertical extension.Preparation register 27 refers to Fig. 3 with 28() and these of other circuit and STD bus 24 are vertical extends bus conductor interface.

Processor executable program 37 can be loaded in MTPMIC2, is stored in RAM/FLASH module 38, and is performed by processor 32.RAM/FLASH module 38 represents data and the program internal memory of processor 32.RAM/FLASH memory modules 38 is processor readable mediums, can read on processor local bus 34.Processor 32 enters processor local bus 34 by the wire 39,40 and 41 that such as figure shows.The arrow 26 indicating VCORE illustrates that processor is powered by from VCORE supply voltage completely.VCORE supply voltage is produced by the linear voltage regulator in power management logic unit (see Fig. 4 C), by the electric power conductor (displaying) of STD bus for MCU/ADC logical block 18 is powered.After processor 32 obtains the electric current provided from VCORE supply voltage, it inscribes in STD bus 24 by bus interface module 42 on configuration register 27 and 28.

If processor 32 will inscribe data in specific configuration register, so the data of write can be carved in bus interface module 42 by processor 32.Bus interface module 42 is put into data on DIN [0-7] data line of STD bus 24.Then address is write in bus interface module 42 by processor 32.It is which that this address describes the configuration register that will write.Bus interface module 42 comprises and converts address to local clock-gating signal.This local clock gating signal is sent to one in associated configuration register by the conductor (displaying) that STD bus is special.STD bus comprises such exclusive data line and comes for each configuration register transmits local clock gating signal.Local clock gating signal makes the data on DIN [0-7] can be written in gating configuration register.Use this mode, configuration information can be written in the configuration register of any one MTPMIC by STD bus 34 by processor 32.

In the graph, the individual bit of configuration register is identified by the blockage of a band X.The storage unit of these single configuration bit is not be distributed in logic unit circuit as shown in the figure, but concentrate be arranged in configuration register.Some such configuration bit are arranged in MCU/ADC logical block 18, but its mode inscribed by STD bus is identical with the inscription mode that it is arranged in other PMIC logical blocks.

MCU/ADC logical block 18 also comprises this 8:1 multiplexer 44 able to programme of an interruptable controller 43. and makes the signal from an optional data line of STD bus can be provided to interruptable controller 43 as look-at-me.In actual design, the data input lead be coupled with multiplexer 44 is not be coupled with DIN [0-7], but is coupled with the common conductors of STD bus.Do not have enough places in Figure 4 A to show these general digital wires, therefore input multiplexer 44 display of interruptable controller is coupled with DIN [0-7].The signal being provided to three interrupting inputs lead-in wire INT [1-3] of interruptable controller from STD bus can select the configuration bit inputted freely to programme by setup control multiplexer 44 by processor 32.

A data input lead of each 8:1 multiplexer 44 can be coupled with the parts referred to herein as " mini plate ".Mini plate symbol is in the drawings the square that centre has a bit.Reference number 45 is exactly so mini plate.This mini plate can with the direct point-to-point metal level conductor of the superiors or integrated circuit in be coupled to the bonding wire of another mini plate.In current design, three mini plates of three multiplexers 44 are directly coupled with the mini plate in signal management logical block 21 by this mode thus are derived from three corresponding event signal detector circuits by the signal be coupled with interruptable controller input lead INT [1-3].Event signal detector circuit specifically describes as follows.As shown in Figure 4 A, interruptable controller input lead INT [0] is hardwired, is used for receiving the cycle settling signal in ADC submodule as shown in the figure.Interruptable controller 34 provides interrupt request singal by band line 46 to processor 32.MASK and the IRQ register of interruptable controller read and write by processor 32 in standard interrupt controller mode by processor local bus 34.

MCU/ADC logical block 18 also comprises three pairs of timers.First pair is timer 47 and 48.Each timer can operate according to single triggering/free bit value corresponding in the control register of timer under single trigger mode and free-running operation PWM mode.Reference number 49 refers to the control register of timer 147.Processor 32 by writing STARTCTRL bit to start timer 147 in register 49.The duration of pulse that timer 1 produces under single trigger mode, or the signal period that duty factor and timer 1 produce under free-running operation PWM mode be determined by many bit counts (COUNT) value stored in register 49.The signal of timer 147 exports one that can be directed to by demultiplexer 50 in STD bus many wires of selection.Processor 32, by the input lead with demultiplexer 50, writes correlative coupling preparation bit and carrys out control signal separation vessel 50.One in the output lead of demultiplexer 50 is coupled with mini plate 51 as schemed.Timer 1 is connected with mini plate 51, the signal of timer 1 is exported directly put suitable mini plate by the metal level conductor of the superiors or another part of bonding wire and integrated circuit and another block to be coupled.Processor 32 52 to be read and write via the control register of processor local bus 34 pairs of timers 147 by interconnecting.Each in often pair of timer is coupled with processor local bus 34 in a similar manner.

Time base during timer travel is a clock signal provided by wire 53.This is the same clock signal of recording processor 32 time.In one example, a 4MHz signal produced by oscillator 54 and an external crystal (displaying) are increased by its frequency of phaselocked loop (PLL) 55, reach as high as 32MHz, thereby produce the clock signal of recording processor time.In another example, although do not use oscillator 54, the 4MHz clock signal received by mini plate 76 by PLL55 as output signal use to generate clock signal.The bonding wire that mini plate 76 can be connected or welded in power management logic unit 20 on corresponding mini plate by metal layer conductive line connects, and shows the 4MHz clock signal produced by 4MHz internal oscillator here.

MCU/ADC logical block 18 also comprises UART/SPI/I2C controller module 56. processor 32 and reads and writes in the data and adr register of UART/SPI/I2C controller module 56 by processor local bus 34.By reading and writing data and adr register in a proper manner, make processor 32 that UART or SPI or I2C agreement can be used to receive by GPIO terminal 57 and 58 and transmit data.The USB of these SPI/I2C dongles 13 shown in GPIO terminal 57 and 58 and Fig. 1 is coupled.

Each GPIO terminal is a part for corresponding GPIO module.GPIO terminal 57 is parts of GPIO module 59.GPIO module 60 comprises GPIO terminal 58.Each GPIO module can be configured according to the one in selected multiple method according to the value of relevant to GPIO module two configuration bit.Processor 32 can inscribe these configuration bit in bus 32.In the embodiment of GPIO module 60, if do not transmit SCLK signal with outside upper strata lead-in wire 61 to MTPMIC2, so lower floor's lead-in wire 62 can be used as the simulating signal that analog input terminal comes receiving terminal 58 receives.This simulating signal is sent to ADC submodule parts 23 to carry out analog to digital conversion subsequently by wire 63.

ADC submodule 23 comprises an analog to digital converter (ADC) 64 and a sequencer 65.Sequencer 65 perform sequence of operation by processor 32 by writing controlling value to control to interconnection 66 in sequencer 65 via processor local bus.Sequencer 65 can be inscribed to ADC control register 67.The bit CEN arranging register 67 can start ADC64 and perform analog to digital conversion.When converting, ADC64 is by writing a high digital value by this feedback of status to sequencer 65 to the CC bit of ADC control register 67.Signal management logical block 21 comprises sampling and the hold circuit of sampling voltage signal on a specific node.Sequencer 65 performs sampling operation by the S/H bit arranged in ADC control register 67 by these samplings and hold circuit.This S/H bit is set and can provides to conductor 68 the S/H signal that an edge rises.This S/H conductor 68 is coupled with sampling and hold circuit in turn.Interconnection between the sampling of the S/H conductor 68 in ADC submodule and the signal management logical block in the present embodiment and the S/H input lead of hold circuit is realized by the special digital wire of STD bus.Fig. 4 A does not show this special digital wire because of limited space, therefore extend to DIN [0-7] wire from the S/H wire of ADC control register 67 in figure.

Sequencer 65 also can control to simulate to the ANALOGIN(of ADC64) input lead 69 provides in multiple signal one to change.This is controlled by multiplexer 70.Multiplexer 70 is much bigger multiplexers, has than input lead more in Fig. 4 A.The input lead of some multiplexers 70 is coupled with mini plate 77.These mini plates, for example, can by directly to manage from mini plate to the topmost metal layer wire of mini plate or bonding wire with driver and multiple terminal of signal management logical block and node are connected.Other input leads 78 and 79 of multiplexer 70 and the analog signal line of STD bus are coupled.

In one example, processor 32 writes 4 sequence of bit values in data acquisition buffer zone 72 in one group of 4 bit register 71.Each 4 bit value represents a node, and its voltage is measured by ADC64.The order of 4 bit values in write Parasites Fauna 71 determines the order of the ADC conversion that will occur.Sequencer 65 reads 4 bit values, and controls multiplexer 70 and simulated by the ANALOGIN(of respective nodes and ADC) input lead is coupled, and then allows conversion occur by inscribing at the CEN bit of ADC control register 67.Sequencer 65 is read and write from data acquisition buffer zone 72 by pilot 80.Then the digital value produced is stored in in corresponding data register bank 73.Sequencer repeats this process, processes one by one according to 4 bit value lists in group 71.After changing each 4 bit value in Parasites Fauna 71, when the one-period completing this operation, data acquisition buffer zone 72 can confirm cycle settling signal on conductor 74.This signal is by inputting INT [0] and carry out interrupt handler thus the digital value allowing processor 32 can come by interconnected 75 via processor local bus in read data register 73 to interruptable controller 43.Processor 32 is via sequencer 65 and by by indirect for node ID value write group 71 control data gatherer process.

driver management logical block

Fig. 4 B is the reduced graph of driver management logical block 19.Driver management logical block 19 comprises three high side driver circuit 81-83 and associated terminal 84-92, three low side driver circuit 93-95 and associated terminal 96-98, the vertical extension bus portion of a fault secure circuit 99 and STD bus.The details of one of them high side driver circuit 81 as shown in the figure.Display look-up table (LUT) structure 100 exports a digital signal to conductor 101.Can programme to LUT structure 100 thus allow the logical value of this digital signal become the combination function of any logical value wanted of any one in selected three digital bus conductor DIN [0-7].Three configuration bit relevant with multiplexer 102 determine one in three DIN [0-7] signals selected by first, three configuration bit relevant to multiplexer 103 determine one in three DIN [0-7] signals selected by second, and three configuration bit relevant to multiplexer 104 determine three DIN [0-7] signals selected by the 3rd simultaneously.The combination logic function that LUT performs is determined by shown 8 configuration bit be designated as in the dotted line module of LUT.All these configuration bit are all programmed by inscribing configuration register 29 via STD bus by processor 32.According to the value of two configuration bit of the selection input value of setting multichannel universal appliance 107, the output of LUT100 can directly be supplied to node 105, or to the registration version that node 105 provides LUT to export, or provide the signal on mini plate 106 to it.By working out suitable configuration bit for multichannel universal appliance 109-111 and AND door 112-114, processor 32 determine which DIN [0-7] signal is supplied to clock, trigger 108 setting and reset input lead.The configuration bit of AND door and the setting of trigger and reset input lead and be coupled, made to reset and triggering arranges trigger for triggering by processor.

Wire 115 and 116 is two vertically extending default signal wires.Default signal wire 115 transmits the effective high-side signal ENHS of high level.Default signal wire 116 transmits the effective low-side signal ENLS of high level.Effectively allowed by ENLS high level low-end driver remove to drive their respective terminal, and allow the invalid effect stopping low-end driver of ENLS low level.In the highest high-side driver 81, AND door 117 provides a digital signal for level shifting circuit 118.On node 119 an one zero volt digital logic low is converted to the voltage levvl on terminal 84 by level shifting circuit 118, and converts volt (inner VDDIO) digital logic low high value of 5.0 on node 119 to voltage levvl on terminal 86.Driver 120 comprises the ever-increasing logic inverter of a string size, wherein the source of the passage N pull-down transistor of last phase inverter is coupled with terminal 86, the source that the passage P of last phase inverter pulls up transistor is coupled with terminal 84, and the output lead of last phase inverter in phase inverter string is coupled with terminal 85.

In exterior arrangement, an external bootstrap capacity is coupled with high-side driver terminal 84 and 86.This bootstrap capacitor is by an external diode charging, and the voltage obtained is main supply voltage VP(such as 12 volts) deduct 0.7 volt of diode range of decrease.When outside low side channel transistor is opened and conducts, terminal 86 is by open and the outside low side passage N transistor conducted may be pulled to earth potential.Therefore the electric current from 12 volts of VP power supplys flows through forward bias external diode and bootstrap capacitor, reaches earth potential at terminal 86.When low side passage N external transistor is opened, this electric current by charging bootstrap capacitor to 11.3 volts.The door of an outside high-end passage N field effect transistor is coupled with terminal 85, and the source of high-end passage N transistor is coupled with terminal 86, and the groove coupling of high-end passage N transistor receives and obtains supply voltage VIN into 48 volts of DC voltage.When this outside high-end passage N transistor controls is opened and conducts electricity, 48 volts of VIN(are positioned at high-end passage N transistor grooves) be coupled by high-end passage N transistor AND gate terminal 86.Therefore terminal 86 is 48 volts.Owing to being charging bootstrap capacitor before, so present terminal 84 is additional 11.3 volts.Therefore the voltage of high-end for outside passage N transistor gate can be risen to 59.3 volts to keep opening and conduction state of outside high-end passage N transistor by driver 120.If outside high-end passage N transistor is closed, so high-end for outside passage N transistor gate voltage can be dropped to 48 volts by driver 120.48 volts of VIN values and 12 volts of VP values are only example.Correspondingly, available drivers 120 drives the signal level on outside high-end passage N transistor gate, and wherein high level is the voltage on terminal 84, and low level is the voltage on terminal 86.

The low side driver circuit 93-95 of driver management logical block 19 constructs similar to high side driver circuit, except low side driver circuit 93-95, it neither comprises level shifting circuit (such as level shifting circuit 118) and does not also guide height terminal (such as terminal 84 and 86).The voltage levvl driven by low-end driver is 12 volts of VP voltages when high level, is earth potential when low level.

Fault secure circuit 99 is controlled by several relevant configuration bit.These bits can be inscribed via STD bus 24 by processor 32.Be hardwired on the special emergency protection wire FAULT [0-1] of two of STD bus to two input leads of fault secure circuit.The value of configuration bit determines the logic function giving tacit consent to protection circuit execution when FAULT [0-1] signal, produces each ENHS and ENLS and outputs signal.Although the configuration bit symbol dispersion shown in Fig. 4 B in logical units, this is only the convenient use of diagram.Configuration bit is the bit of configuration register 29.

power management logic unit

Fig. 4 C is the reduced graph of power management logic unit 20.By operating power administrative unit 20 from selected multiple given application can different external power sources in one obtain power.Such as, such external power source may be lead-acid battery or the lithium battery of one 48 volts, solar battery array, and as the AC power standard 110 volts of metope alternating currents, or the external power source as outside 5 volts of direct current metope width joints exports.Power management logic unit obtains power supply from external power source there, and provides output voltage to the need for electricity of all needs for electricity and whole circuit 10 that meet all MTPMIC2.For obtaining such dirigibility, power management logic unit 120 comprises the configurable pulse width modulator assembly 122 that a group is called as configurable switch power supply pulse width modulator (CSPSPWM).CSPSPWM122 and minority are selected together with external module (MTPMIC2 is outside), can be configured in a different manner, be become a step-down controller, or the highest high pressure drop pressure converter receiving 400 volts, an or flyback converter, an or boost converter.

CSPSPWM122 comprises a small-sized low output current inner linear voltage stabilizer 123.This inner linear voltage stabilizer 123 receives the voltage without voltage stabilizing by terminal VHM124, and exports 4.5 volts of direct currents through adjustment.Internal voltage regulator 123 does not comprise small-sized electric capacity, but because the maximum electric current only exporting a milliampere of voltage stabilizer 123, therefore the electric capacity of linear voltage regulator can be provided by chip.Connection between voltage stabilizer output lead 125 to other circuit of CSPSPWM122 does not illustrate, but the remainder that internal voltage regulator 123 is utilized for CSPSPWM122 is powered.

Inner RC oscillator 126 generates 4MHz signal.After this 4MHz signal is distributed by programmable dividers 127, produce one and start the output square wave digital signal that CSPSPWM122 signal exports every subpulse.The signal output frequency of programmable dividers 127 can be selected as follows: 12.5kHz, 50kHz, 100kHz, 200kHz and 400kHz.If the 3rd control bit that the programmable configuration bit received by wire 166 is determined on wire 165 is digital logic low levels, which so in 50kHz, 100kHz, 200kHz and 400kHz will be output.If the 3rd control bit on wire 165 is digital logic high levels, so programmable dividers 127 can export the square wave of a 12.5KHZ.

At each impulse duration of main external switch, increased by the electric current of main external switch.Current sense terminal 129 is used to by the voltage step weighed via foreign current detection resistance the size detecting this increase electric current.This foreign current detects the current path that resistance is arranged in main switch.Switching Power Supply type belonging to power management logic unit, the current sense function performed by CSM terminal 129 is that superior MCU or low-side current detect.Whether CSM mode detection module 130 receives the voltage on CSM terminal 129 and decides CSM terminal from this voltage and be connected in superior MCU configuration or low-side current detection configuration.Figure 16 is the circuit diagram of CSM mode detection module 10 specifically.When external switch controls to close by terminal 156, CSM mode detection module 130 carrys out work by detecting CSM voltage.When external switch is controlled to close, if CSM voltage is less than 0.5 volt, so CSM mode detection module 130 can determine that connecting power management logic unit carrys out the detection of requirement low-side current, else if when external switch is controlled to close time, CSM voltage is higher than 0.5 volt, and so CSM mode detection module 130 determines to connect power management logic unit to require superior MCU.If CSM mode detection module 130 detects superior MCU requirement, so CSM mode detection module 130 can gauge tap 131 be coupled from the voltage of terminal VP132 and the reversal voltage of amplifier 133 input lead, thus allows amplifier 133 amplify difference between terminal CSM voltage and terminal Vpdianya.If CSM mode detection module 130 detects that low-side current detects demand, so CSM mode detection module 130 gauge tap 131 can will be coupled from the earth potential of terminal 157 and the reversal voltage of amplifier 133 input lead thus allows amplifier 133 amplify voltage difference between terminal CSM and ground connection.In this example, illustrate for anti-phase input single amplifier 133 and select signal, but this operation also realizes by the exclusive amplifier (displaying) detected for high-side current electrical measurement and low-side current that separates and its output selected by CSM mode detection module 130.

As whole Switching Power Supply (CSPSPWM, driver, and external module) when running, and when the main external switch of power supply is in opening in a pulse process, the current detection signal 134 be exaggerated exported by amplifier 133 can increase until it exceedes the amplitude of error signal 135 on node 136.When the current detection signal 134 be exaggerated exceedes this level, comparer 137 can be switched to high digital level its output signal level from low digital level.This high digital signal level is via switch 138 and reset trigger (flip-flip) 139 thus stop upper pulse.In termination, pulse can turn off outside main switch.

The primary power output voltage VP produced by whole power supply appears on terminal VP132.If the voltage on terminal VP132 is higher, so need electricity consumption fewer, and if the voltage-level detector of terminal VP132 is lower, the so just more electric power of needs.Correspondingly, terminal VP132(is distributed by programmable resistance voltage divider FB140) on voltage and voltage difference between reference voltage (as 1.2 volts of band-gap voltage generator 141 export) amplified by error amplifier 141, thus generate an analog error signal 135 on node 136.When Switching Power Supply is run, electric power as more in needs, so analog error signal 135 voltage rise, as needs reduce electric power supply, then its voltage drop.As error signal 135 voltage raises, so in switch periods process, the current detecting output signal 124 that node 143 raises will cause the upper pulse on main switch, it is made to stop afterwards, as error signal 135 voltage reduces, current detecting output signal 134 so on node 143 will cause the upper pulse on main external switch, make it stop in advance.

Signal on CSM terminal 129 is only being greater than 4.3 volts as voltage VP on terminal 132, is just considered to effective during object for current detecting.Under power initiation pattern, when voltage VP is in uphill process, and when being less than 4.3 volts, CSM testing circuit can not be used to stop pulse but pulse-width modulation circuit can run under the safe mode of a low inversion frequency of fixing 12.5KHZde, and the pulse width of this pattern is 0.8 fixing microsecond.Under this start-up mode, do not need also not use current detecting, but the power output capacity of power supply can reduce greatly.Start-up circuit 144 comprises a comparer 145 of being compared with 4.3 volts of VLOCKOUT voltages by voltage VP.If voltage VP is lower than 4.3 volts, so the voltage levvl on node 146 can be become digital low by comparer 145, thus control dispenser 127, make it export the square-wave signal of a 12.5KHZ.In addition, switch 138 can be placed in position upwards by the digital low output of comparer 145.Under position upwards, admittedly the output of prolonging element 147 stops pulse after the solid extension of 0.8 microsecond.

When power supply operates under clean boot pattern, voltage VP loop cycle rises.Rise above 4.3 volts once voltage VP, pulse-width modulator will enter power supply normal mode.Comparer 145 exports a high level on node 146, makes switch 138 be placed in downward position, thus allows current detection circuit 130 and 133 stop upper pulse.High digital level on node 146 stops the control allowing to divider 127, makes it no longer export 12.5KHZ low frequency signal.Therefore divider 127 exports the regular rectangular shape ripple of the higher inversion frequency that is determined by the programmable configuration bit of two on conductor 166.

Power supply runs and makes linear voltage regulator 148 obtain VP output voltage by VP terminal 132.By VP supply voltage, linear voltage regulator 148 generates 5.0 volts of DC voltage VSYS.Voltage VSYS powers to successively other three linear voltage regulator 149-151.These linear voltage regulators 149-151 is difference Drazin inverse voltage 1.8 volts of VCORE on wire 152-154,5.00 volts of VDDIO, and 3.3 volts of VDDA.1.8 volts of VCORE voltages on wire 152 are that the digital logic portion of the MCU/ADC logical block comprising processor 32 is powered.Once processor 32 is energized and operation from these 1.8 volts of VCORE power supplys, so configuration information just can be write back to the operation changing CSPSPWM122 in the configuration register 27 of power management logic unit 120 by processor 32.

A programmable driver 155 receives signal output (output as illustrated example trigger 139) of CSPSPWM122 and drives driver terminal DRM156.If the signal being supplied to driver 155 is high Digital Logic, so driver 155 just on VHM terminal 124 output voltage to DRM terminal 156.Correspondingly like this open external switch.If on the other hand, the signal being supplied to driver 155 is a low digital logic signal, and so driver 155 is just to ground terminal 157 output voltage to DRM terminal 145.External switch is closed like this with regard to corresponding.

Under the first drive pattern, driver 155 or DRM terminal 156 is become earth potential to close outside main switch, or DRM terminal 156 is become VHM voltage to open external switch.DRM terminal can be allowed to obtain voltage on VHM terminal by opening passage P field effect transistor 158 and closing passage N field effect transistor 159.Open passage N field effect transistor 159 DRM terminal can be allowed to become earth potential by closing passage P field effect transistor 158.Switch 162 allows the signal of frequency converter 160 export the roundabout RC of mistake single and triggers 161 and be directly supplied to the door of passage N field effect transistor 159.Therefore RC single triggers 161 does not affect the output of drive circuit 155.

When driving outside NPN transistor under some configuration in superior MCU pattern, the second drive pattern can be used in order to raise the efficiency.In the second drive pattern (" pulse pull-down pattern "), driver 155 makes the voltage on DRM terminal 156 be VHM voltage, opens outside main switch.When outside main switch will be closed, DRM terminal 156 has at the beginning is moved to earth potential (voltage on terminal 157) about 250 nanoseconds quickly, and DRM terminal 156 no longer keeps low level but is in high impedance status until external switch is opened again subsequently.During high impedance, outside main switch keeps closed condition by the non-essential resistance that is coupled between pedestal and outside NPN switch transmitter.Outside NPN transistor pedestal is not kept to be in earth potential by stoping undesired electric current to flow back through NPN transistor and flowing out NPN transistor current collector to prevent power consumption.250 nanosecond in drop-down burst lengths are decided by the delay of RC single triggering 161.In the second mode, switch 162 makes the output of frequency converter 160 be coupled with the door of passage N pulldown field effect transistor 159 by single triggering 161.Drive circuit 155 is that operation is by the logical OR of the programmable configuration bit value in configuration register 30 and determines that the output of the CSM mode detection module 130 that CSPSPWM122 operates under low-side current detecting pattern or superior MCU module decides under the first drive pattern or the second drive pattern.Logical OR function by or door 162A provide.

The error signal 135 exported by error amplifier 142 is simulating signals, but its highest possible signal level is subject to the restriction of direct current clamp circuit 163.The output lead of direct current clamp circuit 163 and the output lead of error amplifier 142 are coupled.The voltage levvl that the highest signal of clamp circuit 163 strangulation error signal 135 may be commented on is programmable, and by providing 8 bit input value to arrange in the input 121 of 8 bit IMOD digital to analog converters (DAC) 164.The 8 bit inputs of IMODDAC164 pass through processor local bus 34 by processor 32 via STD bus 24(or in other examples) inscribe.If the voltage VP on terminal 132 regulated too low needs overall power supply, so can control clamp circuit 163 and make the maximal value of error signal be no more than 2.5 volts.Which limit the amplitude of each current impulse in pulse process on power supply.IMODDAC164 can also be used for efficient solution except the feedback by error amplifier 142.This by control IMODDAC164 error signal 135 is pressed into earth potential thus the voltage that error amplifier 142 cannot be affected on node 136 realizes.

In addition, IMODDAC164 can be used to provide digital feedback loop power by processor 32 and control such as power factor correction or regulate more accurately output power attribute according to ADC criterion.In order to realize power factor correcting power supply, the input current flowing into power supply can follow the trail of the input line voltage rising and decline up and down.If power supply export output voltage higher than required voltage, the power being so fed to load will reduce, and if output voltage lower than required voltage, so bearing power just should increase.Realize this kind of power factor correction and be unable to do without MCU/ADC logical block.The processor of MCU/ADC logical block and relevant ADC thereof is measured input line voltage, and determines the situation of line voltage signal according to these measurement results.ADC also measures the VD VP that power supply exports.According to these measured values, processor 32 is provided with current clamp and makes when input line voltage changes in AC input lines voltage cycle on node 135, and current clamp also can change in proportion.Every 10 microseconds, processor 32 just regulates current clamp by inscribing 8 bit IMODDAC164.In this mode, processor 32, IMODDAC164 and clamp circuit 163 will set about the control to the control loop coming self-feedback ciucuit 140 and error amplifier 142.As long as the voltage of error amplifier 142 driving node 136 is higher than the clamp voltage of clamp circuit 163 on node 136, voltage so on node 136 just will be decided (being controlled by IMODDAC164 by processor 32) correspondingly by clamp circuit 163, the feedback circuit 140 in digital feedback control model is controlled to make the signal of amplifier 142 to export within its mxm..The grid High voltage output of error amplifier 142 is higher than the voltage of clamp circuit strangulation on node 135, and therefore error amplifier can not affect loop works.Feedback circuit 140 is effectively forbidden.Therefore processor 32 carrys out the voltage on Controlling vertex 163 by pincers 163.Similarly, in the accurate control of other requirements or an attribute of extra process output power or the embodiment of one group of attribute, the processor of MCU/ADC logical block and relevant ADC thereof measure output power attribute and maintain the control to digital feedback loop according to these measured values.Processor 32 sets current clamp and makes when measurement index can provide more high-power lower than requiring during level on node 135, when measurement index is higher than when requiring level, can reduces and provide power.Processor 32 is by carrying out periodic adjustment current clamp in the inscription of 8 bit IMODDAC164.

Error amplifier 142 has a very high fixed gain, and also has a programmable mutual conductance g _m.It is g that programmable configuration bit 173 determines error amplifier mutual conductance _m=1uS or g _m=4uS.Processor 32 can be inscribed in configuration register 30, and changes the value of configuration bit 73, thus the mutual conductance of regulating error amplifier regulating loop gain bandwidth (GB).CCOMP is a loop compensation electric capacity with fixed capacity amount.

Multiple configuration bit of power management logic unit 20 are represented by reference number 167-170 and 173.Although these bits are placed on the diverse location of logical block in the example shown, configuration bit is all the bit in independent configuration register 30.Mini plate 171 is provided thus the 4MHZ of oscillator 126 can be outputed signal the mini plate 76 that be supplied to MCU/ADC logical block 18.

signal management logical block

Fig. 4 D is the reduced graph of signal management logical block 21.Signal management logical block 21 comprises four event signal detector circuits, three differential amplifier analog input circuits, the bus segment of a STD bus, and section chief's protection circuit.One of them event signal detector 175 detail as shown in Figure 4 D.Terminal 176 has a relevant programmable I/O module 177.In this example, in the drawings, terminal is not a part for I/O module.Processor 32 can arrange two via STD bus to control the configurable bit of programmable I/O module 177.In one configuration, a simulating signal on terminal 176 is transmitted by wire 178, through multiplexer 179, and by programmable multiple signal selector 180, to a selected conductor business of STD bus 24.Usual multiple signals selector switch exports and is connected with the general digital conductor of STD bus, but does not have enough spaces in fig. 4d to show general digital conductor.Therefore the output display of programmable multiple signal selector is be coupled with DIN [0-7].

In another configuration of logical block, a simulating signal on terminal 176 is sent to the noninverting input lead of comparer 182 by conductor 181.Comparer 182 has two relevant configuration bit to be used for arranging hysteresis or allowing comparer lose efficacy.The anti-phase input lead-in wire of comparer 182 provides together with a threshold voltage able to programme.Threshold voltage able to programme is provided by the programmable multiple signal selector 183 of signal event detector circuit.Two configuration bit of programmable multiple signal selector 183 are inscribed via STD bus by processor 32.3 input leads of programmable multiple signal selector 183 and three AB [0-4] simulation conductors of STD bus are coupled.4th input lead of programmable multiple multiplexer 183 is coupled to receive the programmable voltage received from conventional programmable analog multiplexer 184.The control that conventional programmable analog multiplexer 184 is subject to processor 32 provides a selectable voltage for node 212, and the 4th input lead of multiplexer 183 provides 0.2 volt, 0.5 volt and 1.25 volts of voltages.As shown in the figure, a programmable multiple multiplexer 184 is for all four signal event detector circuits.The numeral of comparer 182 exports the wire being supplied to selected STD bus by multiplexer 179 and multiple signals selector switch 180.

Resistance 208 is coupled between terminal 176 and node 212.Resistance 210 is coupled between terminal 344 and node 212.Circuit 211 is coupled between terminal 345 and node 212.In one application, first coil node A341 of motor 309 is coupled with terminal 345 by external impedance voltage divider.Second coil Node B 342 of motor is coupled with terminal 344 by external impedance voltage divider, and the 3rd coil node C343 of motor is coupled with terminal 176 by external impedance voltage divider.On node 212, the last voltage produced describes the voltage on motor central node 346.Resistance 209,210 with 211 impedance be the same.

In addition, the signal that comparer 182 exports is triggered 185 by single and converts single gating signal to.The control that the pulse signals that single triggering 185 exports are subject to multiple signals selector switch 186 is provided to a selected DIN [0-7].The output of usual multiple signals selector switch 186 is connected with a general digital conductor of STD bus.But in fig. 4d because there is no enough spaces, so do not show general digital conductor.Therefore the output display of programmable multiple signal selector 186 is be coupled with DIN [0-7].

Multiple signals selector switch 180 and 186 there are an output lead and mini plate 187 and 188 are coupled.For example, one in these the mini plates mini plate directly inputted with the multiplexer leading to interruptable controller shown in Fig. 4 A is coupled.Due to this between signal event detector circuit and interruptable controller direct mini plate to the connection of mini plate, if the simulating signal on analog input terminal 176 is found the threshold voltage able to programme exceeded on the noninverting input lead of comparer 182, so comparer 182 can generate an event signal.This event signal is provided to terminal control unit by a mini plate and carrys out interrupt handler afterwards.

Three differential amplifier analog input circuits as shown in the figure, are positioned at the bottom of Fig. 4 D.The upper strata differential amplifier analog input circuit 189 comprising mini input terminal 190 and 191 is described below.The programmable I that each analog input terminal is relevant to one/O module 192,193 is coupled.As mentioned above, each programmable I/O model calling event detector circuit, all allows the simulating signal in its associated terminal to be coupled with conductor, and is sent on a programmable conductor of STD bus by multiple signals selector switch.Can be different and selected AB [0-4] may be comprised from the conductor of the STD bus that the output lead of multiple signals selector switch is coupled.The multiple signals selector switch 194 of six 1:6 is actually two-way multiple signals selector switch, comprises by door, and therefore simulating signal can be sent to simulation terminal from STD bus, or is sent to STD bus from simulation terminal.In another configuration of signal management logical block 21, I/O module 192 and 193 can be configured to and inputs or outputs digital buffer, at this moment, during the bi-directional logic signal selector 194 of six 1:6 and the digital bidirectional multiple signals selector switch (displaying) that is coupled of selected DIN [0-7] signal.

If programmable I/O module 192 is different with the configuration bit program of 193, the simulating signal so on two terminals 190 and 191 is just transferred on the noninverting and anti-phase input lead-in wire of differential amplifier 195 able to programme.Four configuration bit are used for setting the gain of differential amplifier 195 able to programme.The output lead of differential amplifier 195 able to programme is coupled with sampling and hold circuit 196.When sampling and hold circuit 196 samples, the simulating signal of differential amplifier able to programme output by S/H signal capture on conductor 197.As mentioned above, S/H conductor 197 connects MCU/ADC logical block, is coupled by the mark specialized simulation signal conductor of bus and the S/H bit of ADC control register.The signal that sampling and holding circuit 196,198 and 199 export is transmitted on the analog conducting wire of selected STD bus one by one by analog multiplexer 200 and multiple signals selector switch 201.In the example given, two during this two wires in AB [0-4] wire.Also have a kind of selection, simulation 1:3 multiple signals selector switch 201 can on mini plate 202 outputting analog signal.Such as, mini plate 202 is coupled by a bonding wire direct mini plate to the input lead of the input multiplexer 70 of the highest metal level conductor of mini plate or ADC64 connecting mini plate 77.Correspondingly, several the signals exported by the differential amplifier able to programme of signal management logical block can be provided to be used for analog-to-digital programmable signal path to the input of ADC64.

The fault detection logic 203 provided occurs with the form of 10 bit digital-to-analog converters (DAC) able to programme, 204,3 comparer 205-207 and protecting control circuit 208.The 10 bit inputs to DAC204 are programmed via STD bus by processor 32.

In one embodiment, if the voltage on first selected terminal be detected than second selected terminal power on pressure high 100 millivolts, so protecting control circuit 208 can send first protection level signal FAULT [0-1].If the voltage made a call on voltage ratio second the selected cross-talk on three selected terminals is low 100 millivolts, so protecting control circuit 208 can send second protection level signal FAULT [1].These guard signals FAULT [0] and FAULT [1] by direct from the protecting control circuit 208 signal management logical block 175; via FAULT [0-1] wire of STD bus; be delivered to driver management logical block 19, without any need for software process.The output of three comparer 205-207 has multiple different function can be used to determine FAULT [0] and FAULT [1] signal.Selected function is programmed via the configuration bit of bus by setting.Although configuration bit symbol as shown in Figure 4 D spreads all over logical block, configuration bit is all a part for same configuration register 31.

brushless motor controller is applied

Fig. 5 relates to the schematic diagram of the system 300 of the brushless motor controller application of a MTPMIC2.Fig. 5 A, 5B, 5C and 5D are combined pie graph 5.Fig. 5 is the simplification circuit theory diagrams of the MTPMIC2 shown in Fig. 4 in a way.What Fig. 5 A lower left showed is how Fig. 5 A, 5B, 5C and 5D are combined by this method.

System 300 comprises MTPMIC2 and external circuit components 301-337.Power management logic unit 20 and external circuit 301-337 constitute step-down step-down controller power supply through configuration.Because paper space is limited, some interior details of power management logic unit CSPSPWM122 part are not shown.Refer to Fig. 4 A and understand more details.In the configuration of Fig. 5, the voltage VIN on wire 338 is the DC voltage that battery 301 exports.The scope of VIN is approximately from 12 volts to 48 volts.In the example given, VIN is 48 volts, and battery 301 is more piece lead-acid batteries.Npn bipolar transistor 302 drives an inductor 306 under step-down configuration, generates the principal voltage VP on node 339 and terminal VP132.Resistance 307 is current sense resistors.It is coupled between terminal CSM129 and terminal VP132.In such as illustrated example, voltage VP is 12 volts.Electric capacity 308 is main memory capacitance of power supply.The voltage VP produced by power management logic unit is utilized for other MTPMIC2 logical blocks and powers, and for driving the external switch circuit 313-327 of external motor 309 to power.The power switch cycle is programmable, and between the scope that should be arranged on about 200KHZ to about 400KHZ.In the example shown, switching frequency is 12.5KHZ in the startup mode, is 200KHZ in the normal operating mode.

Before system power supply, the circuit on all MTPMIC2 is not charged.When applying cell voltage VIN, internal modulator 123 starts as power management logic element circuit provides the DC voltage of 4.5 volts.Because VP voltage is lower than 4.3 volts of VLOCKOUT voltages, starting control module 144 oscillator/the divider 126/127 of control CSPSPWM122 can be switched to 12.5KHZ low frequency and keeps fixed pulse width.These pulse widths are short and pulse that safety, frequency are relatively low is used for the outside NPN transistor 302 in safe mode.CSM mode detection module 130 determines the coupling of current detecting impedance in high-side current configuration.As response, CSM mode detection module 130 exports a digital signal, and the noninverting input lead of comparer 133 and VP terminal 132 are coupled by gauge tap 131.When CSPSPWM122 makes NPN transistor obtain cycle pulse, the voltage in memory capacitance 308 increases gradually.When starting control module 144 and determining voltage VP higher than 4.3 volts, start control module 144 and just make power supply start to be switched to higher normal mode switching frequency.This normal mode switching frequency is determined by two configuration bit in configuration register (as Fig. 3) 30.Each such bit comprises a non-volatile cell and a volatile cells.When power supply opens, non-volatile cell content is automatically loaded in volatile cells.Volatile cells content exports from configuration bit and configures interlock circuit.Normal mode inversion frequency is programmed in non-volatile cell thus when power management logic unit enters normal operation mode, it will be switched to the suitable frequency determined in advance.The frequency of this configuration of prior decision is usually between 200KHZ to 400KHZ.Start control module 144 grades when detecting that voltage Vp is greater than 4.3 volts, also can the backfeed loop of gauge tap controller make the pulsewidth of pulse no longer equal a fixed value, but according to the regulating and controlling of current detection circuit and feedback circuit.

The voltage VP that terminal 132 produces is used to power linear voltage stabilizer 148-151.External capacitive 334-337 is the external capacitive of these linear voltage regulators.The VCORE voltage that voltage stabilizer 149 exports is used for as the processor 32 of MCU/ADC logical block 18 is powered.The power exported from VCORE voltage stabilizer 149 to be supplied to the processor of MCU/ADC logical block 18 by the wire of STD bus.Once processor obtains voltage VCORE, just start to perform the program coding be stored in RAM/FLASH38.This program coding can allow processor pass through the inscription appropriate to STD bus 24, changes the content of power management logic unit customized configuration bit.Such as, configurable power management logic unit 20 makes driver 155 be programmed to operate in pulse pull-down pattern.

In the Motor control Application of Fig. 5, the coil 310-312 of three motors 309 is coupled each with pair of channels N field effect transistor (NFET).Every have an a high-end NFET and low side NFET for a pair.High-end NFET is 313-315, and low side NFET is 316-318.The electric current flowing through motor comprises from 48 volts of VIN wires 338, flow through a high-end NFET, flow through a coil, to the electric current of motor central node 346, and from motor central node 346, through another coil, then through a conduction low side NFET, flow through the electric current of a current sense resistor to ground nodes and earth lead 340.Current detecting impedance 319,320 and 321 make as figure and the differential amplifier of signal management logical block 21 are coupled MTPMIC2 can measurement and detection via the pressure drop of three current sense resistors.

Each high-end NFET such as figure and a charging diode and a bootstrap capacitor are coupled.Charging diode is diode 322,324 and 326.Bootstrap capacitor is electric capacity 323,325 and 327.Require voltage keep high-end NFET open and conduct higher than 48 volts of VIN voltages.Bootstrap capacitor is coupled as the voltage that terminal 84,87 and 90 provides about 59.3 volts.These 59.3 volts of voltages on terminal 84,87 and 90 make high-side driver 81,82 and 83 that high-end NFET voltage can be driven to open these NFET to 59.3 volts.The operation that operation and the driver of bootstrap capacitor described above manage logical block 19 is associated.

MTPMIC2 be also coupled detect motor three coil node 341-343 on voltage event.Terminal 176 is coupled with coil node C343 by impedance divider 328 and 329.Terminal 344 is coupled with coil Node B 342 by impedance divider 330 and 331.Terminal 345 is coupled with coil node A341 by impedance divider 332 and 333.

lED driver is applied

Fig. 6 is system 400 schematic diagram that a LED driver about MTPMIC2 is applied.Fig. 6 A, 6B, 6C and 6D are combined pie graph 6.Fig. 6 is the simplification circuit theory diagrams of MTPMIC2 shown in Fig. 4 to some degree.The lower right corner of Fig. 6 A illustrates Fig. 6 A, 6B, 6C and 6D and how to be combined.

System 400 comprises MTPMIC2 and external circuit components 401-434.Power management logic unit 20 and external circuit 401-434 are configured formation boost chopper.AC input 401 is power supplys.In the example given, ac-input power supply 401 is that standard 110 volts exchanges standard household metope power supply.110VAC is the completed wave of being corrected by diode bridge 402.Correcting signal becomes gentle through memory capacitance 403 thus on node 435, presents a coarse delay input voltage.FET408 is through being coupled through the main coil of transformer 411 from the pulse of VIN node 435 pull-up streaming current.Resistance 409 is current detecting impedances, is coupled between terminal CSM129 and terminal VP132.First secondary coil 436 and second secondary coil 437 produce main output voltage VP with rectification diode 412 and 413 and memory capacitance 414 and 415 on terminal Vp132.First secondary coil (above) output power when FET opens, for electric capacity 414 charges, and second secondary coil (below) output power when sending out ET and closing is that electric capacity 415 charges.The voltage of electric capacity 414 and 415 is combined and forms main output voltage VP.In the example present, VP is 12 volts.Rectification diode 405 and memory capacitance 404 export a high direct voltage VBUS on node 436.In the example present, VBUS equals direct current 400 volts.

CSM mode detection module 130 detects CSM voltage when FET408 closes.In the topological diagram of Fig. 6, when FET closes, because voltage CSM is lower than 0.5 volt, so CSM mode detection module 130 detects that a low-side current detects configuration and the noninverting input lead that gauge tap 131 is comparer 133 provides a low potential.In Fig. 5 example described above, upon start up, the remainder of processor 32 and MTPMIC2 does not have electricity.Internal voltage regulator 123 and driver 155 obtain trigger voltage by resistance 406 and electric capacity 407 from VIN voltage, at first until supply voltage VP is higher than the VHM voltage now provided by diode 410 by VP.From VHM, it is that CSPSPWM122 circuit is powered that internal voltage regulator exports 4.5 volts of direct currents.Example as described in above-mentioned Fig. 5, starts control module 144 and detects that VP is lower than 4.3 volts, and as response, it controls oscillator and starts to switch low frequency switching converter with 12.5KHZde.Upper pulse is for fixing 0.8 microsecond.FET408 obtain under this safe mode low frequency short on the pulse of pulse until voltage VP reaches 4.3 volts.When detecting that voltage VP is greater than 4.3 volts, so switching frequency of presetting under changing normal mode into of switching frequency.In this boosting configuration, in normal mode to preset switching frequency lower than the frequency of the step-down step-down controller in Fig. 5, be usually about 50KHZ.In normal mode runs, current detecting and feedback circuit are used to the pulsewidth regulating pulse.

An object of boost converter is as node 438 provides 400 volts of VBUS DC voltage.These 400 volts of DC voltage are that normal voltage is used for realizing power factor correction.Input current from 110VAC power supply 401 inputs sinusoidal ac corrugating in order to the 110VAC following the trail of 110VAC wall power supply.Bulky capacitor 404 is used to filter 120HZ waveform.The usual specification of electric capacity is for often to export 1 power 0.5 microfarad.

Once the stable and power supply of voltage VP works in the normal mode, linear voltage regulator 148-151 will produce voltage VCORE and provide it to the processor 32 in MCU/ADC.In the embodiment shown in fig. 5, once power to processor, it just starts to perform the program coding be stored in RAM/FLASH.Under software control, processor is by reconfiguring power management logic power supply 20 via configuration register 30 inscription of STD bus 24 at power management logic unit 20.Such as, inscribe configuration register 30 thus allow the special burst pull-down pattern of driver 155 lose efficacy.Correspondingly, the driver 155 in Fig. 6 or the VHM voltage voltage on terminal DRM156 taken on terminal 124, or become the earth potential on terminal GND157.Driver 155 is DRM terminal can not be become high impedance status after DRM terminal shifts earth potential onto in 150 short nanoseconds.

In Fig. 6 the example given, boost converter obtains power factor correction, and processor 32 is inscribed configuration information via STD bus and programmed to the configuration register 30 in power management logic unit, thus feedback circuit FB140 allows amplifier 142 become rail high level.Effective like this feedback circuit FB140 that prohibits affects signal on node 136.Processor 32 uses a voltage divider comprising resistance 416 and 417 and terminal 439 to use ADC to detect VIN line voltage waveform.Processor 32 uses a voltage divider comprising resistance 418 and 419 and terminal 440 to use ADC to detect VBUS voltage.According to the ADC measured value of these VIN and VBUS, processor 32 adjusts 8 bit input value of IMODDAC164 in the 60HZ cycle of 110VAC input waveform every 10 microseconds, thus the current tracking 110VAC sine wave allowing power supply produce, obtain a homophase power factor correction electric current from 110VAC wall power supply.

Three LED strings 432,433 and 434 are had to be powered by the VBUS of node 438 in step-down topology.To every the relevant drop-down NFET of LED string by the pulse of lamp string conduction current.When NFET opens, increased by the electric current of relevant inductor, and when NFET closes, then reduced by the electric current of inductor.The opening time of NFET is that adjusting pulsewidth controls the average current by relevant LED string with this.When NFET opens, electric current flows through LED string, flows through inductor, flows through NFET, flows through current sense resistor and flow to earth lead.In the case of LED string 426, current sense resistor is resistance 423.The differential amplifier of signal management logical block and ADC is used to the amplitude detecting this electric current.When NFET closes, electric current flows through LED string, inductor, and flows back to diode to VBUS wire 438.The average current flowing through LED string is in the example shown 100 milliamperes.Pulse-width signal is produced by a timer of MCU/ADC logical block.Because there are three LED strings in Fig. 6 example, therefore use three corresponding timers.

high pressure step-down

Fig. 7 is the schematic diagram of the system 500 comprising MTPMIC2 and foreign current assembly 501-514.Power management logic unit 20 and external circuit 501-514 are configured and form high pressure step-down electric pressure converter.Power management logic unit 20 is as shown in Figure 7 from the simple version being to a certain degree the power management logic unit shown in Fig. 4.DRM terminal 156 is used to the outside NPN diode transistor 508 of drive one, and it drives a PNP diode transistor 506 in turn as switch.PNP transistor 506 opens and closes and drives inductor 512.Resistance 513 is current sense resistors.12 volts of VP on node 516 are a step-down voltage, correct AC-input voltage VIN directly produce by the high pressure on node 515.The alternating current input power supplying 501 of 110VAC wall power supply in example, the rectification AC-input voltage VIN on its node 515 equals 150 volts.

return and speed

Fig. 8 is the icon of the system 600 comprising MTPMIC2 and external circuit components.Power management logic unit 20 and external circuit components 601-613 are configured formation direction flyback converter.CSM mode detection module 130 detects location current sense configuration.External field effect transistor 606 drives the main coil of transformer 609 by opening and closing.In this illustration, two secondary coil 614 and 615 are had.Secondary coil 614 provides an output voltage VISO, and the ground connection of its ground connection and secondary coil 615 is separated.Earth lead 616 and earth lead 617 are separated.Secondary coil 615 is used to provide the modulation feedback of main supply voltage VP and CSPSPWM122.If the amplitude of the voltage VP detected is lower than requiring size, so CSPSPWM122 control transistor 606 switches, and makes its upper pulse longer.If the voltage VP amplitude detected is higher than requiring size, so CSPSPWM122 controls transistor 606 and makes pulse shortening on it.Internal voltage regulator 123 and divider 155 receive the power supply from VIN voltage by resistance 604 and electric capacity 605 at first, until voltage VP rises and higher than VHM, VHM voltage is provided by diode 607 by VP in this.Output voltage VISO on wire 618 is relevant to main supply voltage VP with the turn ratio between 615 by two polar curve circles 614.

use and high-endly to drive with the LED of low side FET

Fig. 9 is the schematic diagram of the system 700 comprising MTPMIC2 and external circuit components 701-724.Driver management logical block 19 and external circuit are coupled to drive LED string 701-703.Each LED string in this example is driven by the outside NFET of an a high-end outside NFET and low side.Such as, the high-end NFET of LED string 701 is NFET713, and the low side NFET of LED string 701 is NFET716.Use the bootstrap driver pattern of high-side driver.

inverter H bridge

Figure 10 is system 800 schematic diagram comprising MTPMIC2 and external circuit components 801-812, and these two parts are combined and form H bridge type inverter.Several mode is had to charge to battery (displaying).Battery provides voltage VIN for VP node 813.Power management logic unit 20 forms the power supply producing voltage VP described above together with external module.Voltage Vp on terminal VP132 also appears on node 814.DC voltage VIN from battery is changed by inverter circuit, produces the output voltage of a 110VAC60 hertz between terminal 815 and 816.By opening high-end NFET801 and opening low side NFET804, electric current can be allowed to flow out downwards through the main portion 818 of transformer 806 from node 813, flow to ground nodes and wire 817.The amplitude of electric current is by regulating the pulsewidth of these outside NFET801 and 804 to control.NFET switching frequency is 20KHZ.Electric current can be allowed to flow through the high-end NFET803 of conduction with contrary direction from node 813, upwards flow through the main portion 818 of transformer 806, flow through low side NFET802, and to ground nodes and wire 817.This rightabout current amplitude is also by the pulse-width controlled of modulated external NFET803 and 802.Electric current obtains control and makes sinusoidal voltage appears in two polar curve circles 819.What reference number 821 represented is the core of transformer 806.Inductor 807 and electric capacity 808 are combined and constitute wave filter, can be filled into the frequency content of two pole signals except the 60 hertz frequency compositions needed.Processor 32 decides the state of H bridge by detecting the current amplitude flowing through current sense resistor 805, reach the object of control.Such as, economize on electricity 820 and 817 can be coupled to two input terminals of signal management logical block differential amplifier.Processor 32 can detect the amplitude of this electric current and the driving of corresponding adjustment H bridge by ADC64.

wireless charger

Figure 11 is the schematic diagram of system 900, and it comprises a H bridge type charger circuit similar with the H bridge type charger circuit shown in Figure 10.From as Figure 10 transformer 806, use the transformer of belt carcass 821 different, in Figure 11 circuit, secondary coil 902 magnetic couplings in the main coil of charger 901 and another electronic equipment 903, but by one air gap 904 separately.Inductor 905 and electric capacity 906 set the resonant frequency that circuit H bridge is mainly held.

configuration bit

Figure 12 table illustrates the configuration register bit of MCU/ADC logical block.Figure 13 table illustrates the configuration bit of driver management logical block.Figure 14 table illustrates the configuration bit of power management logic unit.Figure 15 table illustrates the configuration bit of signal management logical block.

power up and collocation method

Figure 17 is the process flow diagram of the method 1000 provided according to Point of Innovation of the present invention.Motorless MTPMIC2 is before powered up (the 1001st step).Give an example, CSPSPWM122 and the external circuit of power management logic unit 20 run as switching power circuit.CSPSPWM122 is starting the outside main switch applying pulse to Switching Power Supply under safe mode, and switching frequency is the fixed frequency determined in advance, and pulsewidth is fixing (the 1002nd step) also.CSM mode detection module 130 determines (the 1003rd step) when the voltage on terminal DRM156 is driven low level, and whether the voltage on CSM terminal 129 is higher than 0.5 volt.If CSM terminal 129 is higher, so the current detection circuit of CSPSPWM can be configured to (the 1004th step) as superior MCU.When Switching Power Supply is subjected to pulse, main supply voltage VP rises, until determine main supply voltage VP(the 1005th step) higher than predetermined threshold voltage.. the threshold voltage predetermined can be such as 4.3 volts.Then switching frequency is changed to the switching frequency (the 1006th step) preset and enters power supply normal operation mode.Thus linear voltage regulator is opened (the 1007th step).If all supply voltages all within suitable scope (the 1008th step), so the processor in MCU/ADC logical block is exported (the 1009th step) from the supply voltage of one of them linear voltage regulator in addition.Processor is initialised, and then on the configuration register of power management logic unit, inscribes configuration information (the 1010th step) via STD bus.Processor control and drive system management logic unit (the 1011st step) runs an output load, and processor control signal management logic unit monitors the state of output load.

When determining the 1003rd step, if when terminal DRM is in low level, CSM terminal 129 is lower than 0.5 volt, and so the current detection circuit of CSPSPWM keeps low-side current to detect configuration.When Switching Power Supply is subjected to pulse, main supply voltage VP rises, until determine main supply voltage VP(the 1012nd step) higher than the threshold voltage predetermined.The threshold voltage predetermined can be such as 4.3 volts.Then the switching frequency (the 1013rd step) that switching frequency can be modified as predetermining enters power supply normal operation mode.Then linear voltage regulator is opened (the 1014th step).If all supply voltages all in suitable scope (the 1015th step), so the processor of MCU/ADC logical block will obtain (the 1016th step) and export from the supply voltage of one of them linear voltage regulator the electric power provided.Processor is initialised, and is carved on the configuration register of power management logic unit by configuration information (the 1017th step) afterwards via STD bus.Processor control and drive system management logic unit (the 1018th step) runs an output load, and simultaneous processor control signal management logic unit monitors the state of output load.

accompanying drawing 18-21 embodiment

Figure 18-21 illustrates the another embodiment of MTPMIC2.Figure 18 illustrates the more details of driver management logical block 19.Fig. 4 A, 4C, 4D illustrate MCU/ADC logical block, power management logic unit and signal management logical block.In Fig. 4 A, the processor 32 of MCU/ADC logical block 18 performs a processor executable program thus inscribes in driver management logical block 19 via STD bus 24, and suitably height or suitably low numeral drive outside high-end and external transistor to make the digital output data signal of each high-side driver and each low-end driver be one in preset time.Namely N channel field effect transistor 313 in Fig. 5 C is one of example of outside high side transistor of being driven by this high-side driver.The outside low side transistor example of N channel field effect transistor 316 for being driven by this low-end driver.

In figure 18, high-side driver 120 is coupled by the grid of an outside high side transistor of terminal 85 and pair of outer transistor; Low-end driver 950 is coupled by the grid of an outside low side transistor of terminal 96 and pair of outer transistor; High-side driver 951 is coupled by the grid of an outside high side transistor of terminal 88 and second pair of external transistor; Low-end driver 952 is coupled by the grid of an outside low side transistor of terminal 97 and second pair of external transistor; High-side driver 953 is coupled by the grid of an outside high side transistor of terminal 91 the 3rd pair of external transistor; Low-end driver 954 is coupled by an outside low side transistor of terminal 98 and the 3rd pair of external transistor.Terminal 84,87 and 90 is all the guide terminal of high-side driver.

For example; as concluded, the digital output data signal 955 of high-side driver 120 is high level; and allow this signal by fault secure circuit 99; so the control signal 956 driven by being coupled with terminal 85 on terminal 85 is arrived high level, by driver to guide terminal 84 by high-side driver 120.In one embodiment, the drain voltage of outside high-end N channel transistor is direct current+48.0 volt, voltage on guide terminal 84 is+59.3 volts at this moment, and these+59.3 volt voltages from guide terminal are coupled with the grid of the high-end N channel transistor in outside, thus open outside high-end N channel transistor.

Similarly; if conclude that the digital output data signal 955 of high-side driver 120 is low value; and allow this signal by fault secure circuit 99, so the control signal 956 driven by coupling terminal 85 on terminal 85 is come floating source terminal 86 through driver by high-side driver 120.The voltage floated on source terminal is determined by external circuit at this moment, but is now coupled with floating source terminal 86 by terminal 85 and will closes outside high-end N channel transistor.

For example; as determined, the digital output data signal 957 of low-end driver 950 is high level; and allow high signal by fault secure circuit 99, so low-end driver 950 is by by flowing through driver to VPP terminal 132(see Fig. 4 C with the high level control signal 958 on terminal 96 strap moved end 96).Thus, outside low side N channel transistor will be opened.Similarly; as determined, the digital output data signal 957 of low-end driver 950 is low value; and allow this signal by fault secure circuit 99, so low-end driver 950 forms earth potential (see Fig. 4 C) by by flowing through driver with the low value control signal on terminal 96 strap moved end 96 on GND terminal 157.Thus, outside low side N channel transistor will be closed.High-side driver 120 and low-end driver 950 form a pair driver.Have three to such driver.

When the system is operated, differential amplifier 195 detects that terminal 190(is see Fig. 4 D) and terminal 191 on voltage difference and amplified.Figure is as shown in 5C and 5D, and current sensing resistor a such as current sensing resistor 319 can be coupled via this terminal 190 and 191.Differential amplifier 195 has a programmable-gain changed by processor 32.Output signal from differential amplifier 195 flows through sampling/hold circuit and is received on comparer first input lead by comparer 205.One threshold voltage produces circuit (such as DAC204) and provide a detection threshold voltage on the second input lead of comparer.Comparer 205 exports whether the voltage that a detection signal 959 verifies on terminal 190 is predetermined with regard to detection threshold voltage.Therefore the testing circuit comprising terminal 190, differential amplifier 195, sampling/hold circuit 198, comparer 205 and DAC204 produces a digital detection signal, shows whether on terminal 190, situation about presetting to be detected.Digital detection signal appears on the output lead of comparer.Processor 32 can change the setting of DAC204 and differential amplifier 195, and can determine that whether it is sampled, and can set LOCTL circuit 192 and 193 when sampling the output of differential amplifier 195.In one embodiment, as the voltage on terminal 190 exceeds the voltage preset, so digital detection signal 959 is digital logic low high value, otherwise digital detection signal 959 is digital logic low.Because outside is connected with detection resistance, this predetermined voltage can show whether have the electric current preset to flow through external sense resistor.As shown in Figure 4 D, three cover differential amplifiers, sampling/hold circuit and comparer is had.

The digital detection signal produced is provided to fault secure circuit.This fault secure circuit comprises the protecting control circuit 208 in Fig. 4 D and the fault secure circuit 99 in Figure 18.Processor 32 carrys out configuration protection control circuit 208 by the value inscribing programmable bits 960.Processor 32 carrys out config failure protection circuit 99 by the value inscribing programmable bits 961.The fault secure circuit 99 that protecting control circuit 208 in signal management logical block is managed in logical block for driver by two conduits of STD bus provides fault-signal FAULT [0-1].

Figure 19 is the circuit diagram of an embodiment of fault secure circuit 99.Node and conduit 105 and 962-966 provide digital output data signal for multiple high-end and fault secure circuit that is low-end driver.Fault secure circuit 99 by conduit 119 and 968-972 for multiple high-end and low-end driver provides control signal.Fault secure circuit 99 comprises the breakback circuit of an and low-end driver high-end for often pair.Such as, if the control signal 958 that low-end driver maintains on terminal 96 is high level, so breakback circuit 973 protects the control signal 956 on the terminal 85 of high-side driver 120 can not be high level; And as high-side driver 120 maintain control signal on terminal 85 956 for high level time, breakback circuit 973 can protect the control signal 958 on the terminal 96 of low-end driver 950 to keep high level.Breakback circuit had not only protected the high-end but also discrete N channel transistor of protection low side of associated external to be opened simultaneously and to conduct.The breakback circuit of often pair of driver can be controlled by inscribing a relevant programmable bits by processor, independent startup or closedown.Programmable bits 974 is startup bits able to programme of breakback circuit 973.

Figure 20 is exemplified with the operation of the function selector circuit 975-980 in Figure 19.It is programmable that the signal of each function selector circuit exports, and can by processor 32 by inscribing relevant programmable bits to change.The signal output of function selector circuit is the combination logic function of input bit able to programme and FAULT [0-1] signal.

In one embodiment, the multiple comparer output detections signals in Fig. 4 D in comparer 205-207, and fault secure circuit can receive these detection signals and correspondingly have at least a part to carry out Down Drive according to the value of one or more detection signal.Pent driver does not consider the state of the correlated digital outputting data signals being supplied to it by processor, and provides a digital logical-low control signal to its associated terminal.Once fault protection logic is programmed, due to the testing conditions on terminal, it just can Down Drive automatically, and this closing process does not rely on processor independently carries out, and inputs without any need for processor.When condition is detected, a signal path, from terminal, by a differential amplifier, flows through a sampling/hold circuit, and via a comparer, and lead up to acquiescence protection circuit until driver, it does not have signal path to pass through processor.

For example, processor may to fault detect and fault secure circuit programming, if thus there is a digital logic low high value in any one detection signal, a presetting driver will be closed.In another embodiment, fault secure circuit can close selected one in multiple different driving device, and this is selected the driver of closing to be decide according to the value of one of detection signal at least partly.In one embodiment, if special detection signal is digital logic low high value, so one first driver is closed, and as detection signal be digital logic low, so one second driver is closed.Driver can be closed separately and/or by group by this method.

Figure 21 is the process flow diagram of the method 2000 provided according to Point of Innovation of the present invention.One processor is used to (step 2001) and produces a digital output data signal.Digital output data signal 955 in Figure 18 is examples for this signal.As high-side driver is not closed, digital output data signal has first value, so on a first terminal, drives a control signal to reach high level (opening an outside high-end N channel transistor) by a high-side driver.As digital output data signal has second value, so control signal is become low value (closing outside high-end N channel transistor) on the first terminal by high-side driver.In one embodiment, first value is digital logic low high value, and second value is digital logic low.High-side driver by by the first terminal and via the startup coupling terminals of high-side driver, first paragraph word allows control signal become high level.Control signal on the first terminal is become low value by being coupled with the floating source terminal via high-side driver by the first terminal by high-side driver.

Predetermined condition on one second terminal is detected (step 2001) and as the response to this detection, a digital detection signal is determined.Terminal 190 in Fig. 4 D is examples for this second terminal, and the digital detection signal in Fig. 4 D is an example of this digital detection signal.

One fault secure circuit, as multi signal function, comprises digital detection signal, is used to (step 2002) and closes high-side driver.Fault secure circuit is once be programmed, even if digital output data signal has first value, processor also can not be relied on independently to close high-side driver.In one embodiment, fault secure circuit comprises the circuit 208 in Fig. 4 D and the circuit 99 in Figure 18.Step 2001-2002 is performed by MTPMIC.Step 2001 " uses a processor " and is performed by MTPMIC, and whole integrated circuit makes purpose processor to produce digital controlled signal to a certain extent.Digital output data signal is generated, and its generation employs processor.Similarly, step 2002 " uses a fault secure circuit " and is performed by MTPMIC, and whole integrated circuit operational failure protection circuit closes high-side driver to a certain extent.High-side driver is closed, and its closedown employs fault secure circuit.

Foregoing description is illustrative not restricted.This patent document has general applicability, is not limited to above-mentioned specific detail.After have studied disclosure of the present invention, to those skilled in the art, all practice significance may be had to the combination of various amendment of the present invention, applicability and different qualities, therefore scope difference of the present invention is determined by reference to foregoing description, and should determine by reference to the four corner of claim.

Claims (23)

1. an integrated circuit, is characterized in that, comprising:

One processor, it can produce a digital output data signal;

One the first terminal;

One high-side driver, it is coupled with described the first terminal, when described high-side driver is not closed, described digital output data signal system one first is worth, then described high-side driver is used on described the first terminal, produce a control signal high level, when described digital output data signal system one second is worth, then described high-side driver is used on described the first terminal, produce a control signal low value;

One second terminal;

One testing circuit, it exports a digital detection signal, for detect whether described second terminal have one pre-conditioned; And

One fault secure circuit; it is programmed by described processor; described fault secure circuit closes described high-side driver according to the function of the multi signal received; described digital detection signal wherein from described testing circuit is one of described multi signal; described function is programmed by described processor; and it is once be programmed, even if described digital output data signal system first value, described fault secure circuit still makes described high-side driver be closed under the signal not from described processor.

2. integrated circuit as claimed in claim 1, it is characterized in that, described processor by writing data to produce described digital output data signal in a bus, described data are sent to a driver management logical block by described bus, and described high-side driver is a part for described driver management logical block.

3. integrated circuit as claimed in claim 1, it is characterized in that, described integrated circuit comprises further:

One starts terminal, and described control signal, by by described the first terminal and described startup coupling terminals, is become high level by described high-side driver; And

One floating source terminal, described control signal, by by described the first terminal and described floating source terminal coupling, is become low value by described high-side driver.

4., as the integrated circuit in claim 1, it is characterized in that, a predetermined condition be voltage on described second terminal higher than a presetting voltage, described presetting voltage carrys out programming Control by described processor.

5. integrated circuit as claimed in claim 1, it is characterized in that, described integrated circuit comprises further:

One the 3rd terminal, described testing circuit comprises a differential amplifier, in order to amplify the voltage difference between the voltage on described second terminal and the voltage on described 3rd terminal.

6. integrated circuit as claimed in claim 1, it is characterized in that, described testing circuit comprises:

One differential amplifier, for receiving the voltage from described second terminal;

One sampling/hold circuit, exports for the signal received from described differential amplifier;

One detection threshold voltage generation circuit, exports a detection threshold voltage; And

One comparer, comprise one first input lead, one second input lead and an output lead, described comparer receives the signal output that described sampling/hold circuit produces on comparer first input lead, described comparer receives the detection threshold voltage on described second input lead, and described comparer exports described digital detection signal by described output lead.

7. integrated circuit as claimed in claim 1, wherein said function is decided by the information be stored in multiple binary numeral able to programme, and described processor is by changing described information to realize changing function.

8. an integrated circuit, is characterized in that, comprising:

One the first terminal;

One detection threshold voltage generation circuit, in order to export a detection threshold voltage;

One first comparer, in order to export one first detection signal, described first detection signal is in order to show having whether there is a preset relation between the voltage of described the first terminal and described detection threshold voltage;

One second terminal;

One first driver, produces one control signal to described second terminal with described second coupling terminals;

More than one binary numeral able to programme, for storing one first numerical information or one second numerical information;

One fault secure circuit, be coupled with described binary numeral able to programme, if described binary numeral able to programme stores described first numerical information, and described first detection signal shows that voltage on described the first terminal and described detection threshold voltage exist preset relation, then close described first driver;

One internal memory; And

One processor, also perform in order to read described internal memory the instruction be stored in described internal memory, described processor is configured, thus makes it in described binary numeral able to programme, write described first numerical information or the second numerical information.

9. integrated circuit as claimed in claim 8; it is characterized in that; also comprise a signalling channel; described signalling channel is from described the first terminal; via described first comparer, fault secure circuit, arrive described first driver, a signal is by described signalling channel transmission; described first driver is closed, and described signalling channel is not via described processor.

10. integrated circuit as claimed in claim 9, it is characterized in that, described integrated circuit comprises further: one starts terminal, and described first driver is a high-side driver, with described startup coupling terminals.

11. integrated circuit as claimed in claim 9, it is characterized in that, described the first terminal is coupled with a current sensing resistor of described integrated circuit external.

12. integrated circuit as described in claim 9, it is characterized in that, described integrated circuit comprises further:

One the 3rd terminal; And

One second driver, produce one control signal to described 3rd terminal with described 3rd coupling terminals, described first driver is a coupling high-side driver, drive a high side transistor of described integrated circuit external, described second driver is a coupling low-end driver, drives a low side transistor of described integrated circuit external.

13. integrated circuit as claimed in claim 9, is characterized in that, described detection threshold voltage programmable, and are changed by described processor.

14. integrated circuit as claimed in claim 9, it is characterized in that, described integrated circuit comprises further:

One the 3rd terminal;

One second driver, produces one control signal to described 3rd terminal with described 3rd coupling terminals;

Described fault secure circuit comprises a breakback circuit, and when described second driver produces a control signal on described 3rd terminal, described breakback circuit prevents described first driver from described second terminal, generating described control signal; If described first driver is when described second terminal produces a control signal, described breakback circuit prevents described second driver from described 3rd terminal, generating described control signal.

15. integrated circuit as claimed in claim 9, it is characterized in that, described integrated circuit comprises further:

One the 3rd terminal, the voltage on described the first terminal is relevant to the voltage on described 3rd terminal; And

One differential amplifier, it is through coupling for amplifying the voltage on the first terminal relevant to voltage on described 3rd terminal, and described differential amplifier provides an output signal for described first comparer.

16. integrated circuit as claimed in claim 15, it is characterized in that, described differential amplifier has a gain, and the gain of described differential amplifier changed by described processor.

17. integrated circuit as claimed in claim 9, it is characterized in that, described integrated circuit comprises further:

One the 3rd terminal; And

One second comparer, exports one second detection signal, in order to show that whether and between described detection threshold voltage the voltage of described 3rd terminal exist preset relation.

18. integrated circuit as described in claim 8, it is characterized in that, described integrated circuit comprises further:

One the 3rd terminal; And

One second comparer; export one second detection signal; in order to show whether the voltage of described 3rd terminal exists preset relation with described detection threshold voltage; described fault secure circuit receives described first detection signal and the second detection signal; described fault secure circuit is programmed by described processor; thus described first driver is closed according to the combination logic function preset of described first and second detection signals, described processor changes described default combination logic function.

19. integrated circuit as described in claim 8, it is characterized in that, described integrated circuit comprises further:

One the 3rd terminal; And

One second comparer; export one second detection signal; in order to show whether the voltage of described 3rd terminal exists preset relation with described detection threshold voltage, and if close described first driver when described fault secure circuit described first detection signal of reception and described first and second detection signals of the second detection signal have a preset number value.

20. integrated circuit as claimed in claim 8, it is characterized in that, described integrated circuit comprises further:

One the 3rd terminal;

One second driver, produce one control signal to described 3rd terminal with described 3rd coupling terminals, described fault secure circuit is programmed by described processor, close the described first or second driver in order to part based on described first detection signal.

21. 1 kinds of method for managing power supply, is characterized in that, comprising:

A processor is used to produce a digital output data signal, if described digital output data signal is one first value and a high-side driver is not closed, then described high-side driver is used to, on a first terminal, a control signal is become one first logic state, if described digital output data signal is one second value, then described high-side driver is used to the described control signal on described the first terminal to become one second logic state;

One second terminal detects pre-one impose a condition thus produce a digital detection signal; And

The function of the multi signal received according to a fault secure circuit closes described high-side driver, described digital detection signal wherein from described testing circuit is one of described multi signal, described processor is to described functional programming, after described function is programmed, described fault secure circuit does not need the input of described processor namely to close described high-side driver, even if the described digital output data signal provided by described processor is described first value, described processor, described high-side driver, described the first terminal, described second terminal and described fault secure circuit form an integrated circuit.

22. method for managing power supply as claimed in claim 21, it is characterized in that, described testing circuit comprises a differential amplifier, in order to amplify the voltage difference between two voltages on the 3rd terminal of described second terminal and described integrated circuit, and the step wherein generating described digital output data signal, detection predetermined condition and closedown high-side driver performs by described integrated circuit.

23. method for managing power supply as described in claim 21, it is characterized in that, described processor writes data to produce described data outputting data signals in a bus, described first logic state is comprised and described the first terminal and is started terminal is coupled by described high-side driver, and described second logic state is comprised the source terminal that described the first terminal and to be floated and is coupled by described high-side driver.