CN103367281A - Semiconductor structure with through silicon via and test circuit and method for manufacturing semiconductor structure - Google Patents
Semiconductor structure with through silicon via and test circuit and method for manufacturing semiconductor structure Download PDFInfo
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- CN103367281A CN103367281A CN2012100927441A CN201210092744A CN103367281A CN 103367281 A CN103367281 A CN 103367281A CN 2012100927441 A CN2012100927441 A CN 2012100927441A CN 201210092744 A CN201210092744 A CN 201210092744A CN 103367281 A CN103367281 A CN 103367281A
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Abstract
The invention discloses a semiconductor structure which is provided with a through silicon via and a test repairing circuit, wherein the through silicon via is arranged in a substrate and runs through an active face and a back face of the substrate; and the test repairing circuit is arranged on the back face and electrically connected with the through silicon via, thereby providing a test repairing function. According to another embodiment of the invention, the invention further provides a method for forming the semiconductor structure.
Description
Technical field
The invention relates to a kind of semiconductor structure and its manufacture method, more special, be semiconductor structure and its method of testing that has the testing and patching circuit and wear the silicon through hole about a kind of.
Background technology
In the information society in modern times, by integrated circuit (integrated circuit, IC) microprocessing systems that consists of is already by the every aspect that generally applies to live, and such as the electrical home appliances of automatic control, mobile communication equipment, personal computer etc., the use of integrated circuit arranged.And along with day by day the progressing greatly of science and technology, and human society is for the various imaginations of electronic product, so that integrated circuit is also toward more polynary, more accurate, more small-sized future development.
General alleged integrated circuit is to form by the crystal grain (die) of producing in the existing semiconductor technology.Make the process of crystal grain, by producing a wafer (wafer) beginning: at first, distinguish a plurality of zones in a wafer, and on each zone, by various semiconductor technologies such as deposition, photoetching, etching or flatening process, to form various required circuit routes.Then, whether can operate smoothly with the testing inner element carrying out general testing procedure.Then, again the regional cutting on the wafer is formed each crystal grain, and be packaged into chip (chip), chip is electrically connected to a circuit board more at last, such as a printed circuit board (PCB) (printed circuit board, PCB), make pin (pin) electrically connect of chip and printed circuit board (PCB) after, just can carry out the various processing that stylize.
In order to improve chip functions and usefulness, increase integrated level in order under the confined space, can hold more multiple semiconductor element, relevant manufacturer develops the Stack Technology of many semiconductor wafers, comprised chip package (flip-chip) technology, multi-die package (multi-chip package, MCP) technology, encapsulation stacking (package on package, PoP) technology, encapsulate built-in packaging body (package in package, PiP) technology etc. can be by each other the stacking integrated level that increases semiconductor element in the unit volume between wafer or packaging body.Develop again in recent years a kind of technology of wearing silicon through hole (through silicon via, TSV) that is called, can promote the interior bonds (interconnect) of each chip chamber in packaging body, so that stacking efficient is further up promoted.
In the existing technology, provide the very convenient mode that stacks owing to wearing the silicon through hole, therefore used in a large number, also opened the imagination of different chip designs.
Summary of the invention
So the present invention discloses a kind of with the structure of testing and patching circuit stroke at backside of substrate, and cooperate and to wear the silicon through hole, can test the not semiconductor element on the substrate active face.
According to an embodiment of the invention, the present invention provides a kind of semiconductor structure, has the silicon of wearing through hole and testing and patching circuit.Wherein, wear active face and the back side that the silicon through hole is arranged in the substrate and runs through substrate.The testing and patching circuit is arranged on the back side of substrate, and wears the silicon through hole and is electrically connected.
Execution mode according to another preferred, the present invention provides a kind of method of stroke semiconductor structure in addition.Substrate at first is provided, and it has active face and the back side.Then form in substrate and wear the silicon through hole, it runs through active face and the back side of substrate.Form the testing and patching circuit at the back side of substrate at last.
The present invention and be to form the testing and patching circuit at the back side of substrate, and by wearing the design of silicon through hole, can carry out testing and patching to the circuit on the wafer active face.By with testing and patching circuit design mode overleaf, and collocation wears the silicon through hole, can save the volume of chip, and so that the design of testing and patching circuit is more flexible.
Description of drawings
Fig. 1 to Fig. 6 is depicted as the manufacture method that has the semiconductor structure of wearing silicon through hole and testing and patching circuit among the present invention.
Wherein, description of reference numerals is as follows:
300 substrates, 318 metal interconnecting systems
302 first surfaces, 320 contact pads
304 second surfaces 322 are worn the silicon through hole
306 perforates, 324 testing and patching circuit
312 insulating barriers, 326 metal interconnecting systems
314 conductive layers, 328 contact pads
316 semiconductor elements, 330 fuses
317 the 3rd surfaces
Embodiment
For making those skilled in the art can further understand the present invention, the following description has been enumerated the several preferred implementations of the present invention, and cooperates accompanying drawing and explanation, the effect that realizes to describe content of the present invention and institute's wish in detail.
Please refer to Fig. 1 to Fig. 6, be depicted as the manufacture method that has the semiconductor structure of wearing silicon through hole and testing and patching circuit among the present invention.As shown in Figure 1, one substrate 300 at first is provided, for example be silicon base (silicon substrate), epitaxial silicon substrate (epitaxial silicon substrate), SiGe semiconductor base (silicon germanium substrate), silicon carbide substrate (silicon carbide substrate) or silicon-coated insulated (silicon-on-insulator, SOI).Substrate 300 has a first surface 302 and a second surface 304.In the preferred embodiment of the present invention, first surface 302 for example is the active face (active surface) of substrate 300, and second surface 304 for example is the back side (back surface) of substrate 300.Substrate 300 thickness are substantially 700 to 1000 microns (micro meter).Then, in first surface 302 formation one perforate 306 of substrate 300, for example the mode with dry ecthing forms perforate 306.Approximately 5 to 10 microns in the aperture of perforate 306, and the degree of depth is about 50 to 100 microns, but formation method and the execution mode of perforate 306 are not limited to this, and visual product is done different the adjustment.
As shown in Figure 2, the first surface 302 in substrate 300 forms an insulating barrier 312 first, for example is a silicon dioxide layer.Insulating barrier 312 can be formed on the surface of perforate 306 but not fill up perforate 306.Then, at first surface 302 up one-tenth one conductive layers 314 of substrate 300, wherein conductive layer 314 can fill up perforate 306 fully.In an embodiment, conductive layer 314 for example is metallic copper, and the method that forms for example is electroplating technology.
As shown in Figure 3, first surface 302 to substrate 300 carries out a flatening process, for example be etch back process or chemico-mechanical polishing (chemical mechanical polish, CMP) technique to be removing the insulating barrier 312 and conductive layer 314 beyond the perforate 306, so that insulating barrier 312, conductive layer 314 flush substantially with first surface 302.
As shown in Figure 4, before can also be optionally form various semiconductor elements and structures at the first surface 302 of substrate 300.For instance, can form at least semiconductor element 316 at first surface 302, for example be golden oxygen compound semiconductor transistor (metal oxide semiconductor transistor, MOS transistor), and form thereon a metal interconnecting system 318.Metal interconnecting system 318 can connect semiconductor element 316 in a contact pad 320, so that semiconductor element 316 can receive outer signals and do the action of I/O by contact pad 320.On the other hand, metal interconnecting system 318 can also connecting conductive layer 314 and other semiconductor element 316.
As shown in Figure 5, form after the metal interconnecting system, the second surface 304 of substrate 300 is carried out a thinning technique, and be thinned to and expose conductive layer 314.At this moment, the second surface after the thinning 304 becomes the 3rd surface 317.And the conductive layer 314 of position in perforate 306 also formed conductive electrode 315.Thus, namely in substrate 300, formed the structure of wearing silicon through hole 322.
One of them is characterised in that the present invention, formed wear silicon through hole 322 after, can be on the 3rd surface 317 of substrate 300, i.e. form a testing and patching circuit 324 on the back side of substrate 300.In an embodiment of the invention, testing and patching circuit 324 for example can comprise a metal interconnecting system 326, a contact pad 328 and a fuse 330.Wearing silicon through hole 318 can be connected with contact pad or fuse 330 connections by metal interconnecting system 326.Therefore when subsequent wafer testing and patching step, that can utilize contact pad 328 conductings wears silicon through hole 318, the follow-up circuit that the defective of detecting is arranged semiconductor element 316 on substrate 300 first surfaces 302 carried out testing and patching, if also can be repaired by structures such as fuses 330.It should be noted that testing and patching circuit 324 of the present invention is not limited to the structures such as aforesaid fuse 330 contact pads 328, also can be other semiconductor structure.But, in other embodiment, can have the testing and patching circuit at active face 302 and the back side 304 of substrate 300, this depends on the different designs of product.
As shown in Figure 6, the present invention is in having provided a kind of semiconductor structure that has the testing and patching circuit and wear the silicon through hole.Semiconductor structure includes substrate 300, wears silicon through hole 322, testing and patching circuit 324.Wear silicon through hole 322 and be arranged in the substrate 300, and run through active face 302 and the 3rd surface 317 of substrate.Testing and patching circuit 324 is arranged on the 3rd surface 317 of substrate 300, and wears silicon through hole 322 and is electrically connected.In an embodiment, semiconductor structure also comprises semiconductor element 316 and the metal interconnecting system arranges 318 on the first surface 302 of substrate 300.In another embodiment of the present invention, testing and patching circuit 324 only is arranged on the 3rd surface 317 of substrate 300, and the circuit of testing and patching step namely is not provided on the first surface 302.But, in other embodiments, can have the testing and patching circuit at active face 302 and the back side 304 of substrate 300, this depends on the different designs of product.In one embodiment of the present of invention, testing and patching circuit 324 comprises contact pad 328, fuse 330 or metal interconnecting system.
Comprehensive above the description, the present invention and be to form the testing and patching circuit at the back side of substrate, and by wearing the design of silicon through hole, can carry out testing and patching to the circuit on the wafer active face.By with testing and patching circuit design mode overleaf, and collocation wears the silicon through hole, can save the volume of chip, and so that the design of testing and patching circuit is more flexible.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a semiconductor structure is characterized in that, comprising:
Substrate has active face and the back side;
Wear the silicon through hole and be arranged in the substrate, and run through described active face and the described back side of described substrate; And
The testing and patching circuit is arranged on the described back side of described substrate, and is electrically connected with the described silicon through hole of wearing.
2. semiconductor structure according to claim 1 is characterized in that, also comprises on the described active face that semiconductor element and metal interconnecting system be arranged at described substrate.
3. semiconductor structure according to claim 1 is characterized in that described testing and patching circuit only is arranged on the described back side of described substrate.
4. semiconductor structure according to claim 1 is characterized in that described testing and patching circuit comprises contact pad or fuse.
5. a method that forms semiconductor structure is characterized in that, comprising:
Substrate is provided, and it has active face and the back side;
Form in described substrate and wear the silicon through hole, it runs through described active face and the described back side of described substrate; And
The described back side in described substrate forms the testing and patching circuit, and the described silicon through hole Electricity Even that wears of wherein said testing and patching Electricity Lu With connects.
6. form according to claim 5 the method for semiconductor structure, it is characterized in that described testing and patching circuit comprises contact pad or fuse.
7. form according to claim 5 the method for semiconductor structure, it is characterized in that, form described step of wearing the silicon through hole and comprise:
Side in the described active face of described substrate forms a perforate;
Surface in described perforate forms insulating barrier and conductive layer, to fill up described perforate; And
Carry out thinning technique from the described back side of described substrate, to expose described conductive layer.
8. form according to claim 7 the method for semiconductor structure, it is characterized in that carrying out before the thinning technique, also the described active face in described substrate forms semiconductor element or metal interconnecting system.
9. form according to claim 8 the method for semiconductor structure, it is characterized in that: described testing and patching circuit is carried out testing procedure, by the described silicon through hole of wearing so that described semiconductor element is tested.
10. form according to claim 8 the method for semiconductor structure, it is characterized in that described semiconductor element comprises MOS (metal-oxide-semiconductor) transistor.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210092744.1A CN103367281B (en) | 2012-03-31 | 2012-03-31 | Semiconductor structure and its manufacture method that there is silicon through hole and test circuit |
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| CN201210092744.1A CN103367281B (en) | 2012-03-31 | 2012-03-31 | Semiconductor structure and its manufacture method that there is silicon through hole and test circuit |
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| CN103367281A true CN103367281A (en) | 2013-10-23 |
| CN103367281B CN103367281B (en) | 2016-07-06 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104851875A (en) * | 2014-02-18 | 2015-08-19 | 联华电子股份有限公司 | Semiconductor structure with silicon through hole, manufacturing method and testing method thereof |
| CN108288613A (en) * | 2018-02-08 | 2018-07-17 | 武汉新芯集成电路制造有限公司 | A kind of integrated circuit structure and method for realizing the modification of integrated circuit last part line |
| US10340203B2 (en) | 2014-02-07 | 2019-07-02 | United Microelectronics Corp. | Semiconductor structure with through silicon via and method for fabricating and testing the same |
| CN115373926A (en) * | 2022-08-31 | 2022-11-22 | 西安微电子技术研究所 | Self-testing and self-repairing method, system, equipment and medium based on physical layer IP |
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| US20100314758A1 (en) * | 2009-06-12 | 2010-12-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-silicon via structure and a process for forming the same |
| CN101924040A (en) * | 2009-06-10 | 2010-12-22 | 财团法人工业技术研究院 | Chip repairing method and chip stack structure |
| EP2302403A1 (en) * | 2009-09-28 | 2011-03-30 | Imec | Method and device for testing TSVs in a 3D chip stack |
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2012
- 2012-03-31 CN CN201210092744.1A patent/CN103367281B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101924040A (en) * | 2009-06-10 | 2010-12-22 | 财团法人工业技术研究院 | Chip repairing method and chip stack structure |
| US20100314758A1 (en) * | 2009-06-12 | 2010-12-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-silicon via structure and a process for forming the same |
| EP2302403A1 (en) * | 2009-09-28 | 2011-03-30 | Imec | Method and device for testing TSVs in a 3D chip stack |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10340203B2 (en) | 2014-02-07 | 2019-07-02 | United Microelectronics Corp. | Semiconductor structure with through silicon via and method for fabricating and testing the same |
| US10685907B2 (en) | 2014-02-07 | 2020-06-16 | United Microelectronics Corp. | Semiconductor structure with through silicon via and method for fabricating and testing the same |
| CN104851875A (en) * | 2014-02-18 | 2015-08-19 | 联华电子股份有限公司 | Semiconductor structure with silicon through hole, manufacturing method and testing method thereof |
| CN104851875B (en) * | 2014-02-18 | 2019-07-23 | 联华电子股份有限公司 | Semiconductor structure with through silicon via and preparation method thereof and test method |
| CN108288613A (en) * | 2018-02-08 | 2018-07-17 | 武汉新芯集成电路制造有限公司 | A kind of integrated circuit structure and method for realizing the modification of integrated circuit last part line |
| CN108288613B (en) * | 2018-02-08 | 2020-03-06 | 武汉新芯集成电路制造有限公司 | Integrated circuit structure and method for realizing modification of back-end connecting line of integrated circuit |
| CN115373926A (en) * | 2022-08-31 | 2022-11-22 | 西安微电子技术研究所 | Self-testing and self-repairing method, system, equipment and medium based on physical layer IP |
| CN115373926B (en) * | 2022-08-31 | 2023-05-16 | 西安微电子技术研究所 | Self-test and self-repair method and system based on physical layer IP |
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| CN103367281B (en) | 2016-07-06 |
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