CN103365738B - The light weight soft information acquisition methods of multi-layer flash memory device - Google Patents

Abstract

The invention discloses a kind of light weight soft information acquisition methods for multi-layer flash memory device, the present invention's method be intended to by quantitatively recording noise in flash-memory channels and corresponding statistics extracts the Soft Inform ation that it stores data from multi-layer flash memory device, for LDPC code error correction algorithm provides Soft Inform ation accurately and reliably, thus significantly enhance LDPC code error-correcting performance, reduce the probability that not correctable error appears in flash chip, effectively extend the serviceable life of multi-layer flash memory device.Can this Soft Inform ation acquiring technology for multi-layer flash memory device be widely used in various employing and 2-bit equally? MLC, 3-bit? MLC (TLC) flash memory is in the system of storage medium, to extend the serviceable life of flash chip.

Description

The light weight soft information acquisition methods of multi-layer flash memory device

Technical field

The present invention relates to the technical field of data storage that solid-state hard disk controller, flash controller etc. take flush memory device as storage medium, be specifically related to a kind of lightweight software information acquisition methods for flash disk operation.

Background technology

In solid state hard disc, the non-volatile flash chip of a large amount of employing is as storage medium.But flash chip is along with the increase of erase-write cycles, and its physical characteristics progressively fails, the mistake of preserving data is caused to roll up.Finally, the bit number of mistake can exceed the error correcting capability of system, thus causes user data to lose efficacy.The decline of the physical characteristics of flash chip seems more remarkable along with the raising of flash chip manufacture craft, especially after manufacturing process enters into the stage of sub-20 nanometers, the service life of flash memory of adopting new technology only can reach and adopt 1/3 of previous generation technique flash memory.The quick downtrending in the serviceable life of flash chip greatly constrains the application of flash chip, and particularly in solid state hard disc field, the introducing of new technology defines huge challenge the serviceable life to solid state hard disc.

In order to the serviceable life of flash chip can be extended, ensure the safety of user data, be designed with correction module in solid-state hard disk controller, correction process is carried out to the data read from flash chip, eliminate the mistake in data.Traditionally, the Error Correction of Coding of main flow all adopts BCH code, and this coded system calculates fast, and error correcting capability is strong.But along with the raising of flash chip manufacturing process, BCH error correction algorithm cannot provide enough error correcting capabilities for flash chip.In communication field, widely used LDPC code (low density parity check code) starts to become the new trend of flash error correction development in the future by means of its powerful error correcting capability.

Although LDPC code error-correcting performance is powerful, play its function needs to provide the Soft Inform ation reading data as input.But flash controller can only read the discrete message be made up of logic ' 0 ' and logic ' 1 ' from the standard interface of flash chip, cannot directly for LDPC provides the Soft Inform ation required for it.At present, existing paper and patent are mainly sampled to storage unit internal physical voltage status in flash chip mainly through the voltage sensor of many groups of different threshold values of flash chip inside, and by ADC(analog-digital conversion) analog voltage of storage unit in flash chip is quantified as the mode of digital quantity, obtain Soft Inform ation, and carry out LDPC decode operation based on this.Although this mode is accurate, but complicated operation, and needing to depend on flash memory vendors provides the internal command of flash chip to help obtain Soft Inform ation, and the internal command that different flash memory vendors provides is not quite similar again, thus the application of LDPC code in solid state hard disc is limited, as reference paper [1] GuiqiangDong, NingdeXie, TongZhang.OntheUseofSoft-DecisionError-CorrectionCodesin NANDFlashMemory.IEEETransactionsoncircuitsandsystem – I:Regularpapers, Vol.58No.2.2011.2, reference paper [2] JiadongWang, ThomasCourtade, HariShankar, RichardD.Wesel.SoftInformationforLDPCDecodinginFlash:Mut ual-InformationOptimizedQuantization.IEEEGlobecom2011pro ceedings, reference paper [3] Dong-hwanLee.EstimationofNANDFlashMemoryThresholdVoltage DistributionforOptimumSoft-DecisionErrorCorrection.IEEET ransactionsonSignalProcessing, Vol.61, Issue2.2013.1.The obtain manner of another Soft Inform ation is the Disturbance Model utilized between flash memory cell, by recovering the Soft Inform ation of data in the logical value that exports from flash memory, as reference paper [4] DaesungKim, JinhoChoi, JeongseokHa.OntheSoftInformationExtractionfromHard-Decis ionOutputsinMLCNANDFlashMemory.IEEEGlobecom2012proceedin gs.This mode needs the many groups voltage sensor utilized in flash chip equally, by flash chip structural limitations, and calculation of complex, be unfavorable for Project Realization.

Summary of the invention

Technical matters to be solved by this invention is to provide a kind of light weight soft information acquisition methods for multi-level storage unit flash memory, be different from the method that prior art requires the threshold voltage value accurately estimated, can realize directly obtaining Soft Inform ation in engineering from the flush memory device of standard interface, improve the serviceable life of flash chip.

In order to can the performance of optimization LDPC algorithm, need corresponding Soft Inform ation as input, but flash chip can only provide the discrete logic information after quantification.Therefore, the present invention proposes a kind of method of the acquisition flush memory device Soft Inform ation by statistics.Its technical conceive is, by the statistics to error message in the past in flash chip physical block, quantitatively estimate the noise of flash-memory channels, when flash controller reads data, error characteristic according to Physical Page in estimated noise figure and physical block calculates the Soft Inform ation reading data, finally utilize LDPC algorithm to carry out error correction calculations to the data read, thus obtain data message accurately.

For MLC flash chip, 4 voltage statuss of 1 physical memory cell, correspond respectively to 2 logical values, i.e. high-order (MSB) logical value and low level (LSB) logical value.According to the interlace map relation of flash chip internal logic value and physics voltage status, can be obtained the voltage status of floating boom in physical memory cell by the logical value of MSB and LSB, this process is called intertexture computing; Similarly, also can be obtained MSB and the LSB logical value of respective memory unit by the floating gate state in physical memory cell, this process is called deinterleaving computing.

The light weight soft information acquisition methods for multi-level storage unit flash memory that the present invention proposes, comprises the following steps:

Step I, set the voltage status of flash memory physical memory cell as X _i(X _i∈ X, X={X ₀, X ₁, X ₂, X ₃), the logical value read from flash chip is Y by the voltage status that deinterleaving computing obtains _j(Y _j∈ Y, Y={Y ₀, Y ₁, Y ₂, Y ₃), then add up in units of physical block in the process of flash chip operation, the voltage status of preserving when physical memory cell is X _itime, the voltage status of its this physical memory cell obtained by the computing of de-interleaving intertexture is Y _jprobability P (Y _j| X _i), P (Y _j| X _i) to characterize in flash-memory channels noise to the interference of data message;

Step II, when flash controller reads data from flash chip, according to the mapping relations of flash chip, intertexture computing is carried out to the logical data collected, obtains the physics voltage status Y that in current flash chip, physical memory cell is preserved _j;

Step III, the flash memory physics voltage status utilizing Bayesian formula to calculate respectively when being obtained by deinterleaving computing are Y _j(Y _j∈ Y, Y={Y ₀, Y ₁, Y ₂, Y ₃) time, the physics voltage status that its storage unit is preserved is X _iprobability P (X _i| Y _j); X _ibe respectively X ₀, X ₁, X ₂and X ₃probability be respectively:

$P\left(X_0\right|Y_j)=\frac{P\left(Y_j\right|X_0)P\left(X_0\right)}{\underset{i=0}{\overset{3}{\mathrm{\Σ}}}P\left(X_i\right)P\left(Y_j\right|X_i)}---\left(1\right)$

$P\left(X_1\right|Y_j)=\frac{P\left(Y_j\right|X_1)P\left(X_1\right)}{\underset{i=0}{\overset{3}{\mathrm{\Σ}}}P\left(X_i\right)P\left(Y_j\right|X_i)}---\left(2\right)$

$P\left(X_2\right|Y_j)=\frac{P\left(Y_j\right|X_2)P\left(X_2\right)}{\underset{i=0}{\overset{3}{\mathrm{\Σ}}}P\left(X_i\right)P\left(Y_j\right|X_i)}---\left(3\right)$

$P\left(X_3\right|Y_j)=\frac{P\left(Y_j\right|X_3)P\left(X_3\right)}{\underset{i=0}{\overset{3}{\mathrm{\Σ}}}P\left(X_i\right)P\left(Y_j\right|X_i)}---\left(4\right)$

Wherein, P (X ₀), P (X ₁), P (X ₂) and P (X ₃) be respectively recording voltage state X in flash memory ₀, X ₁, X ₂, X ₃prior probability, namely known in advance X ₀, X ₁, X ₂and X ₃distribution probability; P (Y _j| X ₀), P (Y _j| X ₁), P (Y _j| X ₂) and P (Y _j| X ₃) be the probability record collected.

Step IV, mapping relations according to deinterleaving computing, calculate the log-likelihood ratio (LogLikelihoodRatio) of data message, thus obtain the Soft Inform ation receiving data.

The flash memory physical state received when flash controller is Y _j(Y _j∈ Y, Y={Y ₀, Y ₁, Y ₂, Y ₃) time, the log-likelihood ratio of corresponding MSB and LSB logical value obtains by following formula:

${\mathrm{LLR}}_{{\mathrm{MSB}|Y}_j}=\log \frac{P\left(X_2\right|Y_j)+P\left(X_3\right|Y_j)}{P\left(X_0\right|Y_j)+P\left(X_1\right|Y_j)}---\left(5\right)$

${\mathrm{LLR}}_{{\mathrm{LSB}|Y}_j}=\log \frac{P\left(X_1\right|Y_j)+P\left(X_2\right|Y_j)}{P\left(X_0\right|Y_j)+P\left(X_3\right|Y_j)}---\left(6\right)$

Like this, will with calculate being updated in LDPC error correction algorithm as the Soft Inform ation of MSB and LSB logical value, thus play the performance of LDPC error correction algorithm to greatest extent.

The technical scheme of further optimization is, after completing a LDPC error correction calculations, under counting current state, the physics voltage status of preserving when storage unit is X _itime, the flash memory physics voltage status obtained by deinterleaving computing is Y _jprobability P _Δ(Y _j| X _i).Upper once obtain light weight soft information time, use P _Δ(Y _j| X _i) P (Y in replacement formula (1)-(6) _j| X _i), calculate the log-likelihood ratio of MSB and LSB logical value.Be conducive to like this improve the accuracy that each Soft Inform ation obtains computing.

Further, if the t time obtains light weight soft information, complete the later storage unit physics voltage status of LDPC error correction calculations is X _i, the flash memory physics voltage status obtained by deinterleaving computing is Y _jprobability meter make P ^(t)(Y _j| X _i), t is natural number.Then utilize following formula iterative computation P ^(t)(Y _j| X _i):

P ^(t)(X _i|Y _j)＝α ₁P ^(t-1)(X _i|Y _j)+α ₂P _Δ(X _i|Y _j),α ₁,α ₁∈[0,1]

Wherein, α ₁and α ₂be respectively P ^(t-1)(Y _j| X _i) and P _Δ(Y _j| X _i) weighted value.Probability P when iteration starts ⁽⁰⁾(Y _j| X _i) can rule of thumb provide.Upper once obtain light weight soft information time, use P ^(t)(Y _j| X _i) P (Y in replacement formula (1)-(6) _j| X _i), calculate the log-likelihood ratio of MSB and LSB logical value.Thus more improve the accuracy that each Soft Inform ation obtains computing.

Further, in MLC flash chip, the error property between the inner different Physical Page of Same Physical block is also uneven, therefore, in order to optimize the performance of LDPC error correction algorithm, the present invention further considers the error characteristic information of Physical Page in the process calculating Soft Inform ation.At record probability P (Y _j| X _i) time, the present invention will record the probability situation of each Physical Page respectively: P ₁(Y _j| X _i), P ₂(Y _j| X _i), P ₃(Y _j| X _i) ... P _n(Y _j| X _i), wherein n is the number of Physical Page in physical block.When flash controller needs to calculate the Soft Inform ation in a kth Physical Page, only need to adopt P _k(Y _j| X _i) carry out calculating:

$P_k\left(X_0\right|Y_0)=\frac{P_k\left(Y_0\right|X_0)P\left(X_0\right)}{\underset{i=0}{\overset{3}{\mathrm{\Σ}}}P\left(X_i\right)P_k\left(Y_0\right|X_i)}$

$P_k\left(X_1\right|Y_0)=\frac{P_k\left(Y_0\right|X_1)P\left(X_1\right)}{\underset{i=0}{\overset{3}{\mathrm{\Σ}}}P\left(X_i\right)P_k\left(Y_0\right|X_i)}$

$P_k\left(X_2\right|Y_0)=\frac{P_k\left(Y_0\right|X_2)P\left(X_2\right)}{\underset{i=0}{\overset{3}{\mathrm{\Σ}}}P\left(X_i\right)P_k\left(Y_0\right|X_i)}$

$P_k\left(X_3\right|Y_0)=\frac{P_k\left(Y_0\right|X_3)P\left(X_3\right)}{\underset{i=0}{\overset{3}{\mathrm{\Σ}}}P\left(X_i\right)P_k\left(Y_0\right|X_i)}$

${\mathrm{LLR}}_{{\mathrm{MSB}|Y}_j}=\log \frac{P_k\left(X_2\right|Y_j)+P_k\left(X_3\right|Y_j)}{P_k\left(X_0\right|Y_j)+P_k\left(X_1\right|Y_j)}$

${\mathrm{LLR}}_{{\mathrm{LSB}|Y}_j}=\log \frac{P_k\left(X_1\right|Y_j)+P_k\left(X_2\right|Y_j)}{P_k\left(X_0\right|Y_j)+P_k\left(X_3\right|Y_j)}$

Method after optimizing improves the accuracy in Soft Inform ation acquisition process, provides more information to process to LDPC error correction algorithm, reduces the probability occurring not correctable error.The present invention utilizes the method for statistics from multi-layer flash memory device (2-bitMLC, 3-bitTLC), extract the Soft Inform ation that it stores data, thus significantly improves the performance of error correction algorithm, effectively extends the serviceable life of multi-layer flash memory device.It is in the occasion of storage medium with flush memory device that this technology is applicable to being applied to solid-state hard disk controller, flash controller etc., to improve the robustness of memory device, extends the serviceable life of memory device.

Accompanying drawing explanation

Below in conjunction with the drawings and specific embodiments, technical scheme of the present invention is further described in detail.

Fig. 1 is the mapping schematic diagram of logical value and physics voltage status in flash memory cell.

Fig. 2 is flash-memory channels model schematic.

Fig. 3 is the schematic flow sheet of Soft Inform ation acquiring technology.

Embodiment

In MLC flash chip, the voltage status that 4 kinds stable in 1 physical memory cell, can be kept.These 4 kinds of voltage statuss are mapped as the combination of 2 logical values, thus realize 1 physical memory cell and preserve 2 logical values.Fig. 1 describes the mapping relations in a certain MLC flash chip.Four kinds of physics voltage statuss are set with: E, D1, D2 and D3 in the physical memory cell of this MLC flash chip.Logical value corresponding is with it divided into high-order logical value (MSB) and low level logical value (LSB), and corresponds respectively to { 1,1}, { 1,0}, { 0,0}, { 0,1}.

Flash chip, by intertexture computing and these two kinds of modes of deinterleaving computing, achieves the mapping operations between physics voltage status and logical value.In the process of carrying out programming to flash chip, the logical value of input is converted into by intertexture computing the physics voltage status that physical memory cell should preserve by flash chip.Such as, when corresponding physical memory cell { during 1,0}, can be programmed into voltage status D1 in flash chip inside by MSB and LSB of input.Correspondingly, in the process reading flash memory chip data, the magnitude of voltage of current preservation is quantified as the voltage status determined by flash chip, and then carries out deinterleaving computing, is converted to corresponding logical value after physics voltage status being quantized.Such as, when the voltage status after quantizing in flash chip physical memory cell is D1, by deinterleaving computing, by externally exporting, MSB is 1 to flash chip, LSB is the logical value of 0.

When information is kept at the inside of flash chip, inevitably can be subject to the interference of chip internal noise.As shown in Figure 2, when data are from the write of flash chip outside, first flash chip carries out interlace operation, and the physics voltage status that then will be write by programming operation is converted into the magnitude of voltage preserved required for storage unit.When needs read data from flash chip inside, the mode that flash chip then reads by quantifying, is quantified as the voltage status determined, is then operated by deinterleaving by analog voltage, obtain corresponding logical value.The analog voltage information of preserving in the memory unit can be subject to the disturbing influence of various additive noise, and changes.The logical data that serious noise even can make reading obtain meets accident upset, thus leads to errors.

Noise disturbance in flash chip is not fixed, and along with flash chip loss in use, the disturbance of noise presents the trend constantly strengthened.This noise disturbance have impact on the serviceable life of flash chip.Therefore, in order to the Soft Inform ation in flash chip can be obtained more exactly, need to carry out record on flash chip noise in operation to the impact of voltage status in storage unit.

In the ideal case, the voltage status that flash memory cell stores is E, D1, D2, D3.In operation, the primary voltage state that hypothetical record is corresponding with perfect condition in flash memory cell is X _i(X _i∈ X, X={X ₀, X ₁, X ₂, X ₃); The logical value read from flash chip is Y by the voltage status that deinterleaving computing obtains _j(Y _j∈ Y, Y={Y ₀, Y ₁, Y ₂, Y ₃).After error correction calculations, flash controller can obtain the primary voltage state being recorded in flash memory cell, by being compared by the number of the primary voltage state of storage and the voltage status of reading, can obtain: when primary voltage state is X _itime, read-out voltage state is Y _jprobability P (Y _j| X _i).Such as, be X by statistics primary voltage state ₃number, and be X in primary voltage state ₃and the voltage status read is Y ₂number, can calculate when primary voltage state is X ₃time read-out voltage state be Y ₂probability P (Y ₂| X ₃).Due to the noise disturbance in flash chip along with operation is also changing, it is also changing on the impact of flash memory cell, so, probability P (Y after each error-correction operation terminates _j| X _i) all will go on record.

The interface of flash chip can only provide the logical value of storage unit, but LDPC error correction algorithm needs using Soft Inform ation as input, therefore, needs the input of probabilistic information as LDPC error correction algorithm that can get accepted data from the logical message received.First the present invention carries out intertexture computing to the logical data collected according to the mapping relations of flash chip, obtains the physics voltage status Y that in current flash chip, storage array is preserved.After calculating the voltage status of current memory cell, the present invention, by the probability record according to flash chip, utilizes Bayesian formula, and the flash memory physical state calculated respectively when receiving is Y _j(Y _j∈ Y, Y={Y ₀, Y ₁, Y ₂, Y ₃) time, the physical state that its storage unit is preserved is X _i(X _i∈ X, X={X ₀, X ₁, X ₂, X ₃) posterior probability P (X _i| Y _j).

Such as, the flash memory physical state received when flash controller is Y ₀time, the voltage status that this storage unit is preserved is respectively X ₀, X ₁, X ₂and X ₃probability be respectively:

$P\left(X_0\right|Y_j)=\frac{P\left(Y_j\right|X_0)P\left(X_0\right)}{\underset{i=0}{\overset{3}{\mathrm{\Σ}}}P\left(X_i\right)P\left(Y_j\right|X_i)}---\left(1\right)$

$P\left(X_1\right|Y_j)=\frac{P\left(Y_j\right|X_1)P\left(X_1\right)}{\underset{i=0}{\overset{3}{\mathrm{\Σ}}}P\left(X_i\right)P\left(Y_j\right|X_i)}---\left(2\right)$

$P\left(X_2\right|Y_j)=\frac{P\left(Y_j\right|X_2)P\left(X_2\right)}{\underset{i=0}{\overset{3}{\mathrm{\Σ}}}P\left(X_i\right)P\left(Y_j\right|X_i)}---\left(3\right)$

$P\left(X_3\right|Y_j)=\frac{P\left(Y_j\right|X_3)P\left(X_3\right)}{\underset{i=0}{\overset{3}{\mathrm{\Σ}}}P\left(X_i\right)P\left(Y_j\right|X_i)}---\left(4\right)$

Wherein, P (X ₀), P (X ₁), P (X ₂) and P (X ₃) be respectively in flash memory the prior probability of the information that stores, namely known in advance X ₀, X ₁, X ₂and X ₃distribution probability; P (Y ₀| X ₀), P (Y ₀| X ₁), P (Y ₀| X ₂) and P (Y ₀| X ₃) probability that can be collected by the past obtains.In like manner, P (X can also be calculated ₀| Y ₁), P (X ₁| Y ₁), P (X ₂| Y ₁), P (X ₃| Y ₁), P (X ₀| Y ₂), P (X ₁| Y ₂), P (X ₂| Y ₂), P (X ₃| Y ₂), P (X ₀| Y ₃), P (X ₁| Y ₃), P (X ₂| Y ₃), P (X ₃| Y ₃).

Complete on the basis calculated posterior probability, the present invention, by the mapping relations according to deinterleaving computing, calculates the log-likelihood ratio (LogLikelihoodRatio) corresponding to MSB and LSB logical value, as the Soft Inform ation receiving data

Such as, the flash memory physical state received when flash controller is Y ₀time, the log-likelihood ratio of corresponding MSB and LSB logical value obtains by following formula:

${\mathrm{LLR}}_{{\mathrm{MSB}|Y}_j}=\log \frac{P\left(X_2\right|Y_j)+P\left(X_3\right|Y_j)}{P\left(X_0\right|Y_j)+P\left(X_1\right|Y_j)}---\left(5\right)$

${\mathrm{LLR}}_{{\mathrm{LSB}|Y}_j}=\log \frac{P\left(X_1\right|Y_j)+P\left(X_2\right|Y_j)}{P\left(X_0\right|Y_j)+P\left(X_3\right|Y_j)}---\left(6\right)$

In like manner, can calculate finally, by obtained LLR _mSB|Yand LLR _lSB|Ycalculate being input in LDPC error correction algorithm as the Soft Inform ation of MSB and LSB logical value, thus play the performance of LDPC error correction algorithm to greatest extent.

After completing LDPC error correction calculations, the present invention is by the data message before and after comparison error correction computing, and counting the physical state of preserving when storage unit is X _itime, it is Y by the flash memory physical state that deinterleaving computing obtains _jprobability P (Y _j| X _i), as the erroneous condition P that flash chip physical block is current _Δ(Y _j| X _i).On this basis, the present invention is by according to the probability P of collecting in physical block in the past the t-1 time iterative process ^(t-1)(Y _j| X _i), utilize following formula to carry out interative computation, calculate the probability P of carrying out required for the t time iteration ^(t)(Y _j| X _i):

P ^(t)(X _i|Y _j)＝α ₁P ^(t-1)(X _i|Y _j)+α ₂P _Δ(X _i|Y _j),α ₁,α ₁∈[0,1]

Wherein, α ₁and α ₂be respectively P ^(t-1)(Y _j| X _i) and P _Δ(Y _j| X _i) weighted value.Probability P when iteration starts ⁽⁰⁾(Y _j| X _i) can rule of thumb provide.New probability record P ^(t)(Y _j| X _i) by the probability record P (Y on this physical block once in Soft Inform ation computation process _j| X _i) participate in computing, thus ensure that each Soft Inform ation obtains the accuracy of computing.

In order to optimize Soft Inform ation acquiring technology further, the present invention, when adding up P (Y|X), has added up the probabilistic information of each Physical Page in physical block respectively.1 is had to the physical block structure of 128 Physical Page.In the process of flash chip operation, the error probability of each Physical Page is also uneven.The present invention further considers the error characteristic information of Physical Page in the process calculating Soft Inform ation, takes meticulousr recording mode, substitutes the probability P (Y of state change in general record physical block _j| X _i).In physical block, the probability of each Physical Page will be collected separately: P ₁(Y _j| X _i), P ₂(Y _j| X _i), P ₃(Y _j| X _i) ... P _n(Y _j| X _i), wherein n is the number of Physical Page in physical block.When flash controller needs to calculate the Soft Inform ation of a kth Physical Page, only need to use P _k(Y _j| X _i) carry out calculating.

Such as, when flash controller is to the data message of the 13rd Physical Page, when carrying out Soft Inform ation acquisition, by the probability record P in this Physical Page past of index ₁₃(Y _j| X _i), be updated to Bayesian formula and carry out calculating.

$P_{13}\left(X_0\right|Y_0)=\frac{P_{13}\left(Y_0\right|X_0)P\left(X_0\right)}{\underset{i=0}{\overset{3}{\mathrm{\Σ}}}P\left(X_i\right)P_{13}\left(Y_0\right|X_i)}$

$P_{13}\left(X_1\right|Y_0)=\frac{P_{13}\left(Y_0\right|X_1)P\left(X_1\right)}{\underset{i=0}{\overset{3}{\mathrm{\Σ}}}P\left(X_i\right)P_{13}\left(Y_0\right|X_i)}$

$P_{13}\left(X_2\right|Y_0)=\frac{P_{13}\left(Y_0\right|X_2)P\left(X_2\right)}{\underset{i=0}{\overset{3}{\mathrm{\Σ}}}P\left(X_i\right)P_{13}\left(Y_0\right|X_i)}$

$P_{13}\left(X_3\right|Y_0)=\frac{P_{13}\left(Y_0\right|X_3)P\left(X_3\right)}{\underset{i=0}{\overset{3}{\mathrm{\Σ}}}P\left(X_i\right)P_{13}\left(Y_0\right|X_i)}$

Due to the probability P for Physical Page ₁₃(Y _j| X _i) than the probability P (Y of past for physical block _j| X _i) record meticulousr, the quantity of information comprised is more, this improves the correctness calculated Soft Inform ation, enhances the performance of error correction algorithm.The account form of its LLR is:

${\mathrm{LLR}}_{{\mathrm{MSB}|Y}_j}=\log \frac{P_{13}\left(X_2\right|Y_j)+P_{13}\left(X_3\right|Y_j)}{P_{13}\left(X_0\right|Y_j)+P_{13}\left(X_1\right|Y_j)}$

${\mathrm{LLR}}_{{\mathrm{LSB}|Y}_j}=\log \frac{P_{13}\left(X_1\right|Y_j)+P_{13}\left(X_2\right|Y_j)}{P_{13}\left(X_0\right|Y_j)+P_{13}\left(X_3\right|Y_j)}$

The complete workflow of Soft Inform ation acquiring technology proposed by the invention as shown in Figure 3.Realizing in process of the present invention, can by the error probability P (Y in operating process _j| X _i) (wherein, i ≠ j) preserve.When starting Soft Inform ation acquiring technology, first judge whether it is start first time.If first time starts, then according to the historical experience configuration error probability record P (Y in past _j| X _i) initial value; Otherwise, from flash chip, read data by directly starting.After reading out the logical value of data message, the mapping relations logically between information and voltage status obtain voltage status Y _j, and statistical computation probability record P (Y _j| X _i), then utilize formula (1)-(6) to calculate the Soft Inform ation of corresponding MSB and LSB logical value, and substitute into LDPC error correction algorithm and calculate, thus obtain the correct result after verifying.After LDPC error checking and correction, iteration is upgraded error probability record P (Y _j| X _i) value, to ensure the accuracy of Soft Inform ation acquisition next time.After completing renewal, the present invention, by checking whether operation new in addition, if also need new digital independent, will proceed data read operation, otherwise by out of service.

It should be noted last that, above embodiment is only in order to illustrate technical scheme of the present invention and unrestricted, although with reference to preferred embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that, can modify to technical scheme of the present invention or equivalent replacement, and not departing from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of right of the present invention.

Claims (4)

1. a light weight soft information acquisition methods for multi-layer flash memory device, is characterized in that, comprise the following steps:

Step I, set the voltage status of flash memory physical memory cell as X _i(X _i∈ X, X={X ₀, X ₁, X ₂, X ₃), the logical value read from flash chip is Y by the voltage status that intertexture computing obtains _j(Y _j∈ Y, Y={Y ₀, Y ₁, Y ₂, Y ₃), then add up in units of physical block in the process of flash chip operation, the voltage status of preserving when physical memory cell is X _itime, the voltage status of its this physical memory cell obtained by intertexture computing is Y _jprobability P (Y _j| X _i), P (Y _j| X _i) to characterize in flash-memory channels noise to the interference of data message;

Step II, when flash controller reads data from flash chip, according to the mapping relations of flash chip, intertexture computing is carried out to the logical data collected, obtains the physics voltage status Y that in current flash chip, physical memory cell is preserved _j;

Step III, the flash memory physics voltage status utilizing Bayesian formula to calculate respectively when being obtained by intertexture computing are Y _j(Y _j∈ Y, Y={Y ₀, Y ₁, Y ₂, Y ₃) time, the physics voltage status that its storage unit is preserved is X _iprobability P (X _i| Y _j); X _ibe respectively X ₀, X ₁, X ₂and X ₃probability be respectively:

$P\left(X_0\right|Y_j)=\frac{P\left(Y_j\right|X_0)P\left(X_0\right)}{\underset{i=0}{\overset{3}{\Σ}}P\left(X_i\right)P\left(Y_j\right|X_i)}---\left(1\right)$

$P\left(X_1\right|Y_j)=\frac{P\left(Y_j\right|X_1)P\left(X_1\right)}{\underset{i=0}{\overset{3}{\Σ}}P\left(X_i\right)P\left(Y_j\right|X_i)}---\left(2\right)$

$P\left(X_2\right|Y_j)=\frac{P\left(Y_j\right|X_2)P\left(X_2\right)}{\underset{i=0}{\overset{3}{\Σ}}P\left(X_i\right)P\left(Y_j\right|X_i)}---\left(3\right)$

$P\left(X_3\right|Y_j)=\frac{P\left(Y_j\right|X_3)P\left(X_3\right)}{\underset{i=0}{\overset{3}{\Σ}}P\left(X_i\right)P\left(Y_j\right|X_i)}---\left(4\right)$

Wherein, P (X ₀), P (X ₁), P (X ₂) and P (X ₃) be respectively recording voltage state X in flash memory ₀, X ₁, X ₂, X ₃prior probability, namely known in advance X ₀, X ₁, X ₂and X ₃distribution probability; P (Y _j| X ₀), P (Y _j| X ₁), P (Y _j| X ₂) and P (Y _j| X ₃) be the probability record collected;

Step IV, mapping relations according to deinterleaving computing, calculate the log-likelihood ratio (LogLikelihoodRatio) of data message, thus obtain the Soft Inform ation receiving data;

The flash memory physical state received when flash controller is Y _j(Y _j∈ Y, Y={Y ₀, Y ₁, Y ₂, Y ₃) time, the log-likelihood ratio of corresponding MSB and LSB logical value obtains by following formula:

${\mathrm{LLR}}_{MSB|Y_j}=log\frac{P\left(X_2\right|Y_j)+P\left(X_3\right|Y_j)}{P\left(X_0\right|Y_j)+P\left(X_1\right|Y_j)}---\left(5\right)$

${\mathrm{LLR}}_{LSB|Y_j}=log\frac{P\left(X_1\right|Y_j)+P\left(X_2\right|Y_j)}{P\left(X_0\right|Y_j)+P\left(X_3\right|Y_j)}---\left(6\right).$

2. the light weight soft information acquisition methods of multi-layer flash memory device according to claim 1, is characterized in that, further comprising the steps of:

After completing a LDPC error correction calculations, under counting current state, the physics voltage status of preserving when storage unit is X _itime, the flash memory physics voltage status obtained by deinterleaving computing is Y _jprobability P _Δ(Y _j| X _i);

Upper once obtain light weight soft information time, use P _Δ(Y _j| X _i) P (Y in replacement formula (1)-(6) _j| X _i), calculate the log-likelihood ratio of MSB and LSB logical value.

3. the light weight soft information acquisition methods of multi-layer flash memory device according to claim 2, is characterized in that, further comprising the steps of:

If the t time obtains light weight soft information, complete the later storage unit physics voltage status of LDPC error correction calculations is X _i, the flash memory physics voltage status obtained by deinterleaving computing is Y _jprobability meter make P ^(t)(Y _j| X _i), t is natural number; Then utilize following formula iterative computation P ^(t)(Y _j| X _i):

P ^(t)(X _i|Y _j)＝α ₁P ^(t-1)(X _i|Y _j)+α ₂P _Δ(X _i|Y _j),α ₁,α ₁∈[0,1]

Wherein, α ¹and α ²be respectively P ^(t-1)(Y _j| X _i) and P _Δ(Y _j| X _i) weighted value, probability P when iteration starts ⁽⁰⁾(Y _j| X _i) can rule of thumb provide;

Upper once obtain light weight soft information time, use P ^(t)(Y _j| X _i) P (Y in replacement formula (1)-(6) _j| X _i), calculate the log-likelihood ratio of MSB and LSB logical value.

4., according to the light weight soft information acquisition methods of the multi-layer flash memory device one of claims 1 to 3 Suo Shu, it is characterized in that, further comprising the steps of: at record probability P (Y _j| X _i) time, record the probability situation P of each Physical Page respectively _k(Y _j| X _i): P ₁(Y _j| X _i), P ₂(Y _j| X _i), P ₃(Y _j| X _i) ... P _n(Y _j| X _i), wherein n is the number of Physical Page in physical block, 1≤k≤n;

When flash controller needs to calculate the Soft Inform ation in a kth Physical Page, only following formula need be adopted to carry out calculating:

$P_k\left(X_0\right|Y_0)=\frac{P_k\left(Y_0\right|X_0)P\left(X_0\right)}{\underset{i=0}{\overset{3}{\Σ}}P\left(X_i\right)P_k\left(Y_0\right|X_i)}$

$P_k\left(X_1\right|Y_0)=\frac{P_k\left(Y_0\right|X_1)P\left(X_1\right)}{\underset{i=0}{\overset{3}{\Σ}}P\left(X_i\right)P_k\left(Y_0\right|X_i)}$

$P_k\left(X_2\right|Y_0)=\frac{P_k\left(Y_0\right|X_2)P\left(X_2\right)}{\underset{i=0}{\overset{3}{\Σ}}P\left(X_i\right)P_k\left(Y_0\right|X_i)}$

$P_k\left(X_3\right|Y_0)=\frac{P_k\left(Y_0\right|X_3)P\left(X_3\right)}{\underset{i=0}{\overset{3}{\Σ}}P\left(X_i\right)P_k\left(Y_0\right|X_i)}$

${\mathrm{LLR}}_{MSB|Y_j}=log\frac{P_k\left(X_2\right|Y_j)+P_k\left(X_3\right|Y_j)}{P_k\left(X_0\right|Y_j)+P_k\left(X_1\right|Y_j)}$

${\mathrm{LLR}}_{LSB|Y_j}=log\frac{P_k\left(X_1\right|Y_j)+P_k\left(X_2\right|Y_j)}{P_k\left(X_0\right|Y_j)+P_k\left(X_3\right|Y_j)}.$