CN103353854A - Method and equipment for increasing data hold time - Google Patents
Method and equipment for increasing data hold time Download PDFInfo
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- CN103353854A CN103353854A CN2013102582939A CN201310258293A CN103353854A CN 103353854 A CN103353854 A CN 103353854A CN 2013102582939 A CN2013102582939 A CN 2013102582939A CN 201310258293 A CN201310258293 A CN 201310258293A CN 103353854 A CN103353854 A CN 103353854A
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Abstract
The invention discloses a method and equipment for increasing data hold time, and belongs to the field of communication. The method comprises the steps as follows: receiving signals transmitted by an SDA (serial data) signal wire and an SCL (serial clock) signal wire; confirming a transmission direction of the SDA signal wire according to the signal transmitted on the SDA signal wire and the signal transmitted on the SCL signal wire; and increasing data hold time of the signal transmitted on the SDA signal wire. The data hold time of the signal transmitted on the SDA signal wire is increased by the method and equipment according to the transmission direction of the SDA signal wire.
Description
Technical field
The present invention relates to the communications field, particularly a kind of method and apparatus that increases data hold time.
Background technology
I
2C(Inter-Integrated Circuit, inter-integrated circuit) bus comprises SDA(Serial Data, serial data) signal wire and SCL(Serial Clock, serial clock) signal wire, the SDA signal wire connects I
2C main device and I
2C is from device, and the SCL signal wire connects I
2C main device and I
2C is from device.Because after data hold time referred to that the rising edge of SCL signal arrives, the data on the SDA kept stablizing the constant time.Work as I
2The C main device reads or writes I
2During the data of C from device, if I
2The data hold time of C from device may make I during less than Preset Time
2The C main device reads or writes I
2C makes a mistake during data from device.
Wherein, at I
2All I in the C communication protocol
2C principal and subordinate device all is open-drain door output, and the output of open-drain door is generally low level or high-impedance state, because high-impedance state can not be identified, thus high-impedance state need to be converted to high level, and high-impedance state is converted to high level and need to connects a pull-up resistor.Because each I
2All there is equivalent capacity on the C principal and subordinate device pin, and may there be external capacitor on the SCL signal wire, make this equivalence electric capacity, external capacitor and this pull-up resistor consist of a RC charge-discharge circuit, because all there is a time constant in the RC charge-discharge circuit in charging process and discharge process, cause the rising edge of SDA and SCL and negative edge to become slow.Within a clock period, when the time of the rising edge of SCL signal was longer, the high level time of this SCL signal was shorter, caused data hold time to shorten.At present, a kind of method that increases data hold time is provided, be specially: the external capacitor on the SCL signal wire is removed, add external capacitor at the SDA signal wire, reduce simultaneously pull-up resistor, so reduced the rising edge of SCL signal and the time of negative edge, increased the rising edge of SDA signal and the time of negative edge, and then increased data hold time.
In realizing process of the present invention, the inventor finds that there is following problem at least in prior art:
As the I that is connected on the same SCL signal wire
2When C principal and subordinate device is more, the I on this SCL signal wire
2Equivalent capacity on the C principal and subordinate device pin is larger, only removes the external capacitor on this SCL signal wire, makes the time decrease of the rising edge of SCL signal and negative edge limited, and when pull-up resistor hour, be input to I
2Electric current in the C principal and subordinate device is larger, can be to I
2C principal and subordinate device causes damage.
Summary of the invention
In order to solve the problem of prior art, the embodiment of the invention provides a kind of method and apparatus that increases data hold time.Described technical scheme is as follows:
First aspect, a kind of method that increases data hold time, described method comprises:
Receive the signal of serial data SDA signal wire and serial clock SCL signal wire transmission;
Determine the transmission direction of described SDA signal wire according to the signal that transmits on the signal that transmits on the described SDA signal wire and the described SCL signal wire;
According to the transmission direction of described SDA signal wire, increase the data hold time of the signal that transmits on the described SDA signal wire.
In conjunction with first aspect, in the possible implementation of the first of above-mentioned first aspect, described according to transmitting on the described SDA signal wire signal and described SCL signal wire on the signal that transmits determine to comprise the transmission direction of described SDA signal wire:
According to the signal that transmits on the signal that transmits on the described SDA signal wire and the described SCL signal wire, determine inter-integrated circuit I
2The state of C bus;
According to described I
2The state of C bus is determined the transmission direction of described SDA signal wire.
In conjunction with the possible implementation of the first of first aspect, in the possible implementation of the second of above-mentioned first aspect, described according to described I
2The state of C bus is determined the transmission direction of described SDA signal wire, comprising:
According to described I
2The state of C bus, the transmission direction of from the corresponding relation of the bus state stored and transmission direction, obtaining described SDA signal wire.
In conjunction with first aspect, in the third possible implementation of above-mentioned first aspect, described transmission direction according to described SDA signal wire increases the data hold time of the signal that transmits on the described SDA signal wire, comprising:
If the transmission direction of described SDA signal wire is by inter-integrated circuit I
2The C main device passes to I
2C then delays time the signal that transmits on the described SDA signal wire from device, to increase the data hold time of the signal that transmits on the described SDA signal wire.
Second aspect, a kind of equipment that increases data hold time, described equipment comprises:
Receiver module is used for the signal that reception serial data SDA signal wire and serial clock SCL signal wire transmit;
Determination module is used for determining according to the signal that transmits on the signal that transmits on the described SDA signal wire and the described SCL signal wire transmission direction of described SDA signal wire;
Increase module, be used for the transmission direction according to described SDA signal wire, increase the data hold time of the signal that transmits on the described SDA signal wire.
In conjunction with second aspect, in the possible implementation of the first of above-mentioned second aspect, described determination module comprises:
The first determining unit is used for according to the signal that transmits on the signal that transmits on the described SDA signal wire and the described SCL signal wire, determines inter-integrated circuit I
2The state of C bus;
The second determining unit is used for according to described I
2The state of C bus is determined the transmission direction of described SDA signal wire.
In conjunction with the possible implementation of the first of second aspect, in the possible implementation of the second of above-mentioned second aspect, described the second determining unit comprises:
Obtain subelement, be used for according to described I
2The state of C bus, the transmission direction of from the corresponding relation of the bus state stored and transmission direction, obtaining described SDA signal wire.
In conjunction with second aspect, in the possible implementation of the first of above-mentioned second aspect, described increase module comprises:
Delay unit is by inter-integrated circuit I if be used for the transmission direction of described SDA signal wire
2The C main device passes to I
2C then delays time the signal that transmits on the described SDA signal wire from device, to increase the data hold time of the signal that transmits on the described SDA signal wire.
The third aspect, a kind of equipment that increases data hold time, described equipment comprises storer and processor, is used for carrying out described a kind of method that increases data hold time.
In embodiments of the present invention, CPLD determines the transmission direction of SDA signal wire according to the signal that transmits on the signal that transmits on the SDA signal wire and the SCL signal wire, when the transmission direction of SDA signal wire is by I
2The C main device passes to I
2C is during from device, and CPLD delays time to the signal that transmits on this SDA signal wire, and then increases the data hold time of the signal that transmits on the SDA signal wire.
Description of drawings
In order to be illustrated more clearly in the technical scheme in the embodiment of the invention, the accompanying drawing of required use was done to introduce simply during the below will describe embodiment, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is a kind of method flow diagram that increases data hold time that the embodiment of the invention provides;
Fig. 2 is a kind of I that the embodiment of the invention provides
2C main device and I
2C is from the annexation synoptic diagram of device;
Fig. 3 is the method flow diagram that the another kind that provides of the embodiment of the invention increases data hold time;
Fig. 4 is a kind of I that the embodiment of the invention provides
2The transition of C bus state concern synoptic diagram;
Fig. 5 is a kind of device structure synoptic diagram that increases data hold time that the embodiment of the invention provides;
Fig. 6 is the device structure synoptic diagram that the another kind that provides of the embodiment of the invention increases data hold time.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, embodiment of the present invention is described further in detail below in conjunction with accompanying drawing.
The embodiment of the invention provides a kind of method that increases data hold time, and referring to Fig. 1, the method comprises:
Step 101: the signal that receives the transmission of serial data SDA signal wire and serial clock SCL signal wire;
Step 102: determine the transmission direction of SDA signal wire according to the signal that transmits on the signal that transmits on the SDA signal wire and the SCL signal wire;
Step 103: according to the transmission direction of SDA signal wire, increase the data hold time of the signal that transmits on the SDA signal wire.
In embodiments of the present invention, CPLD determines the transmission direction of SDA signal wire according to the signal that transmits on the signal that transmits on the SDA signal wire and the SCL signal wire, when the transmission direction of SDA signal wire is by I
2The C main device passes to I
2C is during from device, and CPLD delays time to the signal that transmits on this SDA signal wire, and then increases the data hold time of the signal that transmits on the SDA signal wire.
The embodiment of the invention provides a kind of method that increases data hold time.Wherein, as shown in Figure 2, at I
2C main device and I
2C is from adding a CPLD(Complex Programmable Logic Device between the device, CPLD) chip, signal on the SCL signal wire can be input in this CPLD chip, but this CPLD chip is not controlled the signal on this SCL signal wire, signal demand on the SDA signal wire is input to I again through the processing of this CPLD chip
2C is from device.Referring to Fig. 3, the method comprises:
Step 201:CPLD receives the signal of SDA signal wire and the transmission of SCL signal wire;
Wherein, the signal that transmits on the signal that transmits on the SDA signal wire and the SCL signal wire can be I
2The C main device passes to I
2C also can be I from the signal of device
2C passes to I from device
2The signal of C main device.
Step 202:CPLD determines I according to the signal that transmits on the signal that transmits on the SDA signal wire and the SCL signal wire
2The state of C bus;
Wherein, at I
2In the C communication specification, I
2The state of C bus be divided into idle condition, transmission beginning, address transfer, from device reply, read data state, main device reply, write data mode and 8 states of end of transmission (EOT).
Wherein, I
2The C bus is that the sign of idle condition is that SCL signal and SDA signal all are in high level state; I
2The sign that the C bus transfer begins is that the SCL signal is between high period, the SDA signal occur one by high level to low level saltus step.I
2The sign that the C bus transfer finishes is that the SCL signal is between high period, and the SDA signal occurs one by the saltus step of low level to high level.
Wherein, I
2The status change of C bus relation can be as shown in Figure 4, in Fig. 4, and when SCL signal and SDA signal all are in high level state, this I
2The C bus is in idle condition, and CPLD judges I
2Whether the C bus begins transmission, if so, and I then
2The C main device sends commencing signal, and this moment, CPLD determined I
2The C bus is in the transmission initial state; When transmitting first clock period on the SCL signal wire, I
2The C bus enters the address transfer state, and when transmission is during a clock period on the SCL signal wire, the SDA signal wire will transmit the information of 1bit, after the operation mark of the address information of 7bit and 1bit is transmitted, and I
2The C bus is in from the device response status; If I
2The C bus represents write operation when the signal of the 8bit of address transfer state transfer is " 0 ", represent read operation when the signal of this 8bit is " 1 ".
Work as I
2When the C main device is carried out read operation, and I
2When C certain device from device is judged address that SDA signal wire transmits for self address, this I then
2C makes from device and replying, at this moment I
2The C bus is carried out the read data state, after the data of 8bit run through, and I
2The C bus is in the main device response status, if I
2When the C main device is not replied, I
2The C bus enters the end of transmission (EOT) state.
Work as I
2When the C main device is carried out write operation, and I
2When C certain device from device is judged address that SDA signal wire transmits for self address, this I then
2C makes from device and replying, at this moment I
2The C bus is write data mode, after the data of 8bit write, and I
2The C bus is in from the device response status, if I
2When the C main device is not replied, I
2The C bus enters the end of transmission (EOT) state.
Wherein, work as I
2On the SDA signal wire that the C bus comprises during proceed to transmit signal, the front 7bit of first byte is address information, 8bit is operation mark, when being " 0 ", this operation mark represents write operation, represent read operation when this operation mark is " 1 ", the 9th clock period is answer signal, Low level effective, high level represents nonreply, end of transmission (EOT).Under normal circumstances, during write operation, I
2The C main device is initiated terminating operation, and during read operation, I
2After the C main device is received last data, not to I
2C replys from device, end of transmission (EOT).
Step 203:CPLD is according to I
2The state of C bus is determined the transmission direction of SDA signal wire;
Particularly, CPLD is according to I
2The state of C bus, the transmission direction of from the corresponding relation of the bus state stored and transmission direction, obtaining the SDA signal wire.
Wherein, the state of having stored and the corresponding relation of transmission direction can be as shown in table 1 state and the corresponding relation of transmission direction.
Table 1
| Bus state | Transmission direction |
| Idle condition | Main pass to from |
| The transmission beginning | Main pass to from |
| Address transfer | Main pass to from |
| Reply from device | From passing to the master |
| The read data state | From passing to the master |
| Main device is replied | Main pass to from |
| Write data mode | Main pass to from |
| End of transmission (EOT) | Main pass to from |
Step 204: if the transmission direction of SDA signal wire is by I
2The C main device passes to I
2C is from device, and then CPLD delays time the signal that transmits on the SDA signal wire, to increase the data hold time of the signal that transmits on the SDA signal wire.
Particularly, if the transmission direction of SDA signal wire is by I
2The C main device passes to I
2C is from device, and then CPLD makes the data hold time of the signal that transmits on the rear SDA signal wire of time-delay greater than Preset Time the signal lag default value that transmits on the SDA signal wire.
Further, the transmission direction when the SDA signal wire is by I
2C passes to I from device
2The C main device then directly transmits the data on the SDA signal wire.
Wherein, CPLD only processes the signal that transmits on the SDA signal wire, the signal that transmits on the SCL signal wire is not processed, and has reduced the complexity of processing, the resource of having saved CPLD.
For example, the transmission direction when CPLD judgement SDA signal wire is by I
2The C main device passes to I
2C is during from device, the signal lag 200nS of CPLD to transmitting on this SDA signal wire.
In embodiments of the present invention, CPLD determines the transmission direction of SDA signal wire according to the signal that transmits on the signal that transmits on the SDA signal wire and the SCL signal wire, when the transmission direction of SDA signal wire is by I
2The C main device passes to I
2C is during from device, and CPLD delays time to the signal that transmits on this SDA signal wire, and then increases the data hold time of the signal that transmits on the SDA signal wire.
Referring to Fig. 5, the embodiment of the invention provides a kind of equipment that increases data hold time, and this equipment comprises:
Receiver module 301 is used for the signal that reception serial data SDA signal wire and serial clock SCL signal wire transmit;
Determination module 302 is used for determining according to the signal that transmits on the signal that transmits on the SDA signal wire and the SCL signal wire transmission direction of SDA signal wire;
Increase module 303, be used for the transmission direction according to the SDA signal wire, increase the data hold time of the signal that transmits on the SDA signal wire.
Wherein, determination module 302 comprises:
The first determining unit is used for according to the signal that transmits on the signal that transmits on the SDA signal wire and the SCL signal wire, determines inter-integrated circuit I
2The state of C bus;
The second determining unit is used for according to I
2The state of C bus is determined the transmission direction of SDA signal wire.
Further, the second determining unit comprises:
Obtain subelement, be used for according to I
2The state of C bus, the transmission direction of from the corresponding relation of the bus state stored and transmission direction, obtaining the SDA signal wire.
Wherein, increasing module 303 comprises:
Delay unit is by inter-integrated circuit I if be used for the transmission direction of SDA signal wire
2The C main device passes to I
2C then delays time the signal that transmits on the SDA signal wire from device, to increase the data hold time of the signal that transmits on the SDA signal wire.
In embodiments of the present invention, CPLD determines the transmission direction of SDA signal wire according to the signal that transmits on the signal that transmits on the SDA signal wire and the SCL signal wire, when the transmission direction of SDA signal wire is by I
2The C main device passes to I
2C is during from device, and CPLD delays time to the signal that transmits on this SDA signal wire, and then increases the data hold time of the signal that transmits on the SDA signal wire.
Referring to Fig. 6, the embodiment of the invention provides a kind of equipment that increases data hold time, and this equipment comprises:
Receive the signal of serial data SDA signal wire and serial clock SCL signal wire transmission;
Determine the transmission direction of described SDA signal wire according to the signal that transmits on the signal that transmits on the described SDA signal wire and the described SCL signal wire;
According to the transmission direction of described SDA signal wire, increase the data hold time of the signal that transmits on the described SDA signal wire.
Wherein, described according to transmitting on the described SDA signal wire signal and described SCL signal wire on the signal that transmits determine to comprise the transmission direction of described SDA signal wire:
According to the signal that transmits on the signal that transmits on the described SDA signal wire and the described SCL signal wire, determine inter-integrated circuit I
2The state of C bus;
According to described I
2The state of C bus is determined the transmission direction of described SDA signal wire.
Wherein, described according to described I
2The state of C bus is determined the transmission direction of described SDA signal wire, comprising:
According to described I
2The state of C bus, the transmission direction of from the corresponding relation of the bus state stored and transmission direction, obtaining described SDA signal wire.
Further, described transmission direction according to described SDA signal wire increases the data hold time of the signal that transmits on the described SDA signal wire, comprising:
If the transmission direction of described SDA signal wire is by inter-integrated circuit I
2The C main device passes to I
2C then delays time the signal that transmits on the described SDA signal wire from device, to increase the data hold time of the signal that transmits on the described SDA signal wire.
In embodiments of the present invention, CPLD determines the transmission direction of SDA signal wire according to the signal that transmits on the signal that transmits on the SDA signal wire and the SCL signal wire, when the transmission direction of SDA signal wire is by I
2The C main device passes to I
2C is during from device, and CPLD delays time to the signal that transmits on this SDA signal wire, and then increases the data hold time of the signal that transmits on the SDA signal wire.
Need to prove: the equipment of the increase data hold time that above-described embodiment provides is at I
2In the C communication service, only the division with above-mentioned each functional module is illustrated, in the practical application, can as required the above-mentioned functions distribution be finished by different functional modules, the inner structure of the equipment of being about to is divided into different functional modules, to finish all or part of function described above.In addition, the equipment of the increase data hold time that above-described embodiment provides belongs to same design with the embodiment of the method that increases data hold time, and its specific implementation process sees embodiment of the method for details, repeats no more here.
The invention described above embodiment sequence number does not represent the quality of embodiment just to description.
The all or part of step that one of ordinary skill in the art will appreciate that realization above-described embodiment can be finished by hardware, also can come the relevant hardware of instruction to finish by program, described program can be stored in a kind of computer-readable recording medium, the above-mentioned storage medium of mentioning can be ROM (read-only memory), disk or CD etc.
The above only is preferred embodiment of the present invention, and is in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of doing, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. a method that increases data hold time is characterized in that, described method comprises:
Receive the signal of serial data SDA signal wire and serial clock SCL signal wire transmission;
Determine the transmission direction of described SDA signal wire according to the signal that transmits on the signal that transmits on the described SDA signal wire and the described SCL signal wire;
According to the transmission direction of described SDA signal wire, increase the data hold time of the signal that transmits on the described SDA signal wire.
2. the method for claim 1 is characterized in that, described according to transmitting on the described SDA signal wire signal and described SCL signal wire on the signal that transmits determine to comprise the transmission direction of described SDA signal wire:
According to the signal that transmits on the signal that transmits on the described SDA signal wire and the described SCL signal wire, determine inter-integrated circuit I
2The state of C bus;
According to described I
2The state of C bus is determined the transmission direction of described SDA signal wire.
3. method as claimed in claim 2 is characterized in that, and is described according to described I
2The state of C bus is determined the transmission direction of described SDA signal wire, comprising:
According to described I
2The state of C bus, the transmission direction of from the corresponding relation of the bus state stored and transmission direction, obtaining described SDA signal wire.
4. the method for claim 1 is characterized in that, described transmission direction according to described SDA signal wire increases the data hold time of the signal that transmits on the described SDA signal wire, comprising:
If the transmission direction of described SDA signal wire is by inter-integrated circuit I
2The C main device passes to I
2C then delays time the signal that transmits on the described SDA signal wire from device, to increase the data hold time of the signal that transmits on the described SDA signal wire.
5. an equipment that increases data hold time is characterized in that, described equipment comprises:
Receiver module is used for the signal that reception serial data SDA signal wire and serial clock SCL signal wire transmit;
Determination module is used for determining according to the signal that transmits on the signal that transmits on the described SDA signal wire and the described SCL signal wire transmission direction of described SDA signal wire;
Increase module, be used for the transmission direction according to described SDA signal wire, increase the data hold time of the signal that transmits on the described SDA signal wire.
6. equipment as claimed in claim 5 is characterized in that, described determination module comprises:
The first determining unit is used for according to the signal that transmits on the signal that transmits on the described SDA signal wire and the described SCL signal wire, determines inter-integrated circuit I
2The state of C bus;
The second determining unit is used for according to described I
2The state of C bus is determined the transmission direction of described SDA signal wire.
7. equipment as claimed in claim 6 is characterized in that, described the second determining unit comprises:
Obtain subelement, be used for according to described I
2The state of C bus, the transmission direction of from the corresponding relation of the bus state stored and transmission direction, obtaining described SDA signal wire.
8. equipment as claimed in claim 5 is characterized in that, described increase module comprises:
Delay unit is by inter-integrated circuit I if be used for the transmission direction of described SDA signal wire
2The C main device passes to I
2C then delays time the signal that transmits on the described SDA signal wire from device, to increase the data hold time of the signal that transmits on the described SDA signal wire.
9. an equipment that increases data hold time is characterized in that, described equipment comprises storer and processor, is used for carrying out such as the described a kind of method that increases data hold time of the arbitrary claim of claim 1 to 4.
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| CN2013102582939A CN103353854A (en) | 2013-06-26 | 2013-06-26 | Method and equipment for increasing data hold time |
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|---|---|---|---|
| CN2013102582939A CN103353854A (en) | 2013-06-26 | 2013-06-26 | Method and equipment for increasing data hold time |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101324875A (en) * | 2007-06-11 | 2008-12-17 | 大唐移动通信设备有限公司 | Method and apparatus for expanding I<2>C bus |
| CN101763331A (en) * | 2010-01-18 | 2010-06-30 | 中兴通讯股份有限公司 | System and method for realizing I2C bus control |
| CN101770443A (en) * | 2009-01-07 | 2010-07-07 | 成都市华为赛门铁克科技有限公司 | Time sequence adjusting method for internal IC (integrated circuit) bus, corresponding device and system thereof |
| US20110225339A1 (en) * | 2010-03-09 | 2011-09-15 | Chi-Ming Chen | Data transmission system and a programmable spi controller |
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2013
- 2013-06-26 CN CN2013102582939A patent/CN103353854A/en active Pending
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| CN101324875A (en) * | 2007-06-11 | 2008-12-17 | 大唐移动通信设备有限公司 | Method and apparatus for expanding I<2>C bus |
| CN101770443A (en) * | 2009-01-07 | 2010-07-07 | 成都市华为赛门铁克科技有限公司 | Time sequence adjusting method for internal IC (integrated circuit) bus, corresponding device and system thereof |
| CN101763331A (en) * | 2010-01-18 | 2010-06-30 | 中兴通讯股份有限公司 | System and method for realizing I2C bus control |
| US20110225339A1 (en) * | 2010-03-09 | 2011-09-15 | Chi-Ming Chen | Data transmission system and a programmable spi controller |
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| Title |
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Application publication date: 20131016 |