CN103326898B - A kind of ether interface links detection system and the method for settling time - Google Patents
A kind of ether interface links detection system and the method for settling time Download PDFInfo
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Abstract
The invention discloses detection system and the method for a kind of ether interface link LINK settling time, relate to the communications field.In described detection system, reseting module exports reset RESET signal to control module; Processor module control RESET signal when detecting beginning is transformed to low level by high level; Control module, when RESET signal becomes high level from low level, sends enabling signal to counting module, when LINK signal becomes low level from high level, sends stop signal to counting module; Counting module upon receiving the initiation signal, starts the cycle count to reference clock signal, when receiving stop signal, stops the cycle count to reference clock signal, exports count results; Processor module obtains ether interface link settling time according to the computation of Period of count results and reference clock signal.Described detection system and method, can measure the settling time of LINK fast and accurately, improves certainty of measurement.
Description
Technical field
The present invention relates to communication technical field, particularly a kind of ether interface links detection system and the method for settling time.
Background technology
The application widely that over 30 years, Ethernet obtains due to the feature of its low cost, high reliability and simplification, and the foundation linking (LINK) in Ethernet is the prerequisite of carrying out Ethernet communication.The situation of ether interface LINK is varied, as the interconnection of 1000BASE-T interface auto-negotiation, 100BASE-TX interface auto-negotiation interconnects, the auto-negotiation interconnection of 1000BASE-T interface and 100BASE-TX interface, the non-automatic negotiation interconnection of 100BASE-TX interface, the auto-negotiation of 1000BASE-SX and non-automatic negotiation interconnection etc., under different interface modes, LINK is all different for settling time.And in some practical applications; such as, all need to be grasped LINK this parameter settling time in the application scenarioss such as port protection, Two-channel switching and data flow; and this parameter does not also all provide in general databook; therefore system designer often instructs related application based on experience value, does not reach best effect.In sum, under distinct interface pattern, the accurate detection of ether LINK settling time is just seemed important.
Be at present generally read by stopwatch to the detection mode of LINK settling time, manually ether interface resetted, at the end of reset signal, start stopwatch counting, after LINK indicator light is lighted, stop counting, now can read value settling time of LINK.In said method, the end time more difficult assurance of reset signal, test subjectivity is comparatively large, and measuring accuracy is poor.
Summary of the invention
(1) technical problem that will solve
The technical problem to be solved in the present invention is: the detection system providing a kind of ether interface to link settling time and method, to improve the accuracy of detection to ether interface link settling time.
(2) technical scheme
For solving the problems of the technologies described above, the invention provides the detection system of a kind of ether interface link settling time, it comprises: reseting module, processor module, control module and counting module;
Described reseting module, for exporting reset RESET signal to described control module, described RESET signal is initially high level;
Described processor module, for accessing described reseting module when detecting and starting, is transformed to low level to control described RESET signal by high level;
Described control module, for receiving described RESET signal and link LINK signal, when described RESET signal becomes high level from low level, send enabling signal to described counting module, when described LINK signal becomes low level from high level, send stop signal to described counting module;
Described counting module, for receiving reference clock signal, and when receiving described enabling signal, start the cycle count to described reference clock signal, when receiving described stop signal, stop the cycle count to described reference clock signal, and export count results to described processor module;
Described processor module, also links settling time for obtaining ether interface according to the computation of Period of described count results and described reference clock signal.
Wherein, described control module, also for sending reset signal when described RESET signal is low level to described counting module;
Described counting module, also for when receiving described reset signal, resets count results.
Wherein, described LINK signal indicates pin to export by the LINK of ether interface chip;
Described reseting module, also exports RESET signal for the reseting pin to described ether interface chip, and controls described ether interface chip reset when described RESET signal is low level.
Wherein, be transformed to high level after described RESET signal is transformed to low level after predetermined hold-time, the described scheduled time is greater than resetting time of described ether interface chip.
Wherein, described detection system also comprises: clock module;
Described clock module, for exporting described reference clock signal to described counting module;
Described processor module, also for accessing described clock module, to obtain the cycle of described reference clock signal, and adjusts the cycle of described reference clock signal.
Wherein, described processor module, obtains ether interface and links settling time specifically for described count results being multiplied with the cycle of described reference clock signal.
Wherein, described processor module, the mean value also linking settling time for calculating a predetermined value ether interface links settling time as final ether interface.
The present invention also provides a kind of ether interface to link the detection method of settling time, and it comprises:
Reseting module exports reset RESET signal to control module, and described RESET signal is initially high level;
Processor module accesses described reseting module when detecting and starting, and is transformed to low level to control described RESET signal by high level;
Control module receives described RESET signal and link LINK signal, when described RESET signal becomes high level from low level, send enabling signal to counting module, when described LINK signal becomes low level from high level, send stop signal to described counting module;
Counting module receives reference clock signal, and when receiving described enabling signal, start the cycle count to described reference clock signal, when receiving described stop signal, stop the cycle count to described reference clock signal, and export count results to described processor module;
Processor module obtains ether interface link settling time according to the computation of Period of described count results and described reference clock signal.
Wherein, described detection method also comprises:
Described control module sends reset signal when described RESET signal is low level to described counting module;
Count results, when receiving described reset signal, resets by described counting module.
Wherein, described detection method also comprises:
The LINK of ether interface chip indicates pin to export LINK signal to described control module;
Described reseting module exports RESET signal to the reseting pin of described ether interface chip, and controls described ether interface chip reset when described RESET signal is low level.
Wherein, be transformed to high level after described RESET signal is transformed to low level after predetermined hold-time, the described scheduled time is greater than resetting time of described ether interface chip.
Wherein, described detection method also comprises:
Clock module exports reference clock signal to described counting module;
Clock module described in processor die block access, to obtain the cycle of described reference clock signal, and adjusts the cycle of described reference clock signal.
Wherein, processor module obtains ether interface link settling time, being specially according to the computation of Period of described count results and described reference clock signal:
Processor module described count results was multiplied with the cycle of described reference clock signal obtain ether interface link settling time.
Wherein, described detection method also comprises:
Obtain a predetermined value ether interface and link settling time;
The mean value calculating described predetermined value ether interface link settling time is as final ether interface link settling time.
(3) beneficial effect
In the detection system of ether interface LINK of the present invention settling time and method, reseting module, for exporting reset RESET signal to described control module, described RESET signal is initially high level; Processor module, for accessing described reseting module when detecting and starting, is transformed to low level to control described RESET signal by high level; Control module, for receiving described RESET signal and link LINK signal, when described RESET signal becomes high level from low level, send enabling signal to described counting module, when described LINK signal becomes low level from high level, send stop signal to described counting module; Counting module, for receiving reference clock signal, and when receiving described enabling signal, start the cycle count to described reference clock signal, when receiving described stop signal, stop the cycle count to described reference clock signal, and export count results to described processor module; Processor module, also links settling time for obtaining ether interface according to the computation of Period of described count results and described reference clock signal.By adopting described detection system and method, the automation of measuring can be realized, the settling time of LINK can be measured fast and accurately, improve certainty of measurement.
Accompanying drawing explanation
Fig. 1 is the modular structure schematic diagram that ether interface described in the embodiment of the present invention 1 links the detection system of settling time;
Fig. 2 be detection system described in the embodiment of the present invention 1 realize principle schematic;
Fig. 3 is the flow chart that ether interface described in the embodiment of the present invention 2 links the detection method of settling time.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples for illustration of the present invention, but are not used for limiting the scope of the invention.
Ether interface of the present invention links the detection system of settling time, can based on the CPLD(ComplexProgrammableLogicDevice adopting low cost, CPLD) realize to relevant integrated device, it mainly comprises: reseting module, processor module, control module and counting module.Described reseting module, for exporting reset RESET signal to described control module, described RESET signal is initially high level.Described processor module, for accessing described reseting module when detecting and starting, is transformed to low level to control described RESET signal by high level.Described control module, for receiving RESET signal and link LINK signal, when described RESET signal becomes high level from low level, send enabling signal to described counting module, when described LINK signal becomes low level from high level, send stop signal to described counting module.Described counting module, for receiving reference clock signal, and when receiving described enabling signal, start the cycle count to described reference clock signal, when receiving described stop signal, stop the cycle count to described reference clock signal, and export count results to described processor module.Described processor module, also links settling time for obtaining ether interface according to the computation of Period of described count results and described reference clock signal.
By the detection system adopting ether interface of the present invention to link settling time, can realize the automation of measuring, can measure the settling time of LINK fast and accurately, certainty of measurement is high, and by adjustment reference clock signal, certainty of measurement can reach Microsecond grade.
Embodiment 1
Fig. 1 is the modular structure schematic diagram that ether interface described in the embodiment of the present invention 1 links the detection system of settling time, as shown in Figure 1, described detection system 110 comprises: control module 111, counting module 112, reseting module 113, clock module 114 and processor module 115.
Described reseting module 113, for exporting reset RESET signal to described control module 111 and ether interface chip 130, described RESET signal is initially high level.
Particularly, described reseting module 113 is generally register.Described RESET signal also inputs to described ether interface chip 130 by the reseting pin of described ether interface chip 130, to reset to described ether interface chip 130.
Described processor module 115, for accessing described reseting module 113 when detecting and starting, is transformed to low level to control described RESET signal by high level.
Particularly, described processor module 115 is generally CPU, testing staff can start the instruction of detection to described processor module 115 input by modes such as buttons, namely trigger described processor module 115 to start to detect, when described processor module 115 receives the instruction starting to detect, carry out write operation to described reseting module 113, the described RESET signal that described reseting module 113 exports is transformed to low level by high level.
Described control module 111, for receiving described RESET signal, sends reset signal when described RESET signal is low level to described counting module 112.
Further, when described RESET signal is low level, described RESET signal also resets for controlling described ether interface chip 130.
High level is transformed to after predetermined hold-time after described RESET signal is transformed to low level, because described RESET signal inputs to described ether interface chip 130 by the reseting pin of described ether interface chip 130, like this when described RESET signal is transformed to high level by low level, described ether interface chip 130 is triggered and starts to set up LINK.Wherein, the described scheduled time is greater than ether interface chip 130 and resets the required time, is generally greater than 50 milliseconds, such as can be set to 200 milliseconds.
Described control module 111, also for receiving LINK signal, and, when described RESET signal becomes high level from low level, send enabling signal to described counting module 112, when described LINK signal becomes low level from high level, send stop signal to described counting module 112.
Particularly, described LINK signal generally indicates pin to provide by the LINK of described ether interface chip 130.Described LINK signal is initially high level, represents that LINK sets up when described LINK signal becomes low level from high level.
Described counting module 112, for receiving reference clock signal, and when receiving described enabling signal, start the cycle count to described reference clock signal, when receiving described stop signal, stop the cycle count to described reference clock signal, and export count results to described processor module 115.
Particularly, described reference clock signal is exported by described clock module 114.Further, described clock module 114 connects the clock generator 140 of described detection system 110 outside, described clock module 114 obtains reference clock signal after carrying out the process such as frequency division after receiving the original clock signal of described clock generator 140 output, then sends to described counting module 112.The cycle of described reference clock signal can affect the accuracy of detection of described detection system, and generally, the cycle of described reference clock signal is 1 millisecond, and now the counting precision of described counter is millisecond rank; According to actual needs, the counting precision of described counter can also be improved further, such as make the cycle of described reference clock signal be 1 microsecond.In addition, the bit wide of described counting module 112 should be enough large, to ensure correctly to export count results.
In addition, described counting module 112, also for when receiving described reset signal, resets count results, so that test next time.
Described processor module 115, also links settling time for obtaining ether interface according to the computation of Period of described count results and described reference clock signal.
Particularly, described processor module described count results was multiplied with the cycle of described reference clock signal obtain ether interface link settling time.
In addition, described processor module 115, also for accessing described clock module, to obtain the cycle of described reference clock signal, and adjusts the cycle of described reference clock signal.
And, described processor module 115, can also after obtaining predetermined value (such as 5,10) individual ether interface link settling time, the mean value calculating described predetermined value ether interface link settling time links settling time, to improve accuracy in detection further as final ether interface.
Fig. 2 be detection system described in the embodiment of the present invention 1 realize principle schematic, as shown in Figure 2, (in Fig. 2 the 1st article of dotted line place), counting is started to the cycle of reference clock REFCLK signal when described counting module 112 becomes high level from described RESET signal from low level, when LINK signal becomes low level from high level, (in Fig. 2 the 2nd article of dotted line place) stops the cycle count to REFCLK signal, and exports count results.Namely the cycle that count results is multiplied by REFCLK signal by processor module 115 obtains ether interface LINK T settling time.
Use detection system of the present invention, can detect the settling time of LINK fast and accurately, accuracy of detection is high; When after repeatedly test obtains multiple count results, calculate the mean value of multiple count results, accuracy in detection can be improved further.
Embodiment 2
Fig. 3 is the flow chart that ether interface described in the embodiment of the present invention 2 links the detection method of settling time, and as shown in Figure 3, described detection method comprises:
310: reseting module exports reset RESET signal to control module, and described RESET signal is initially high level.
Particularly, described reseting module is generally register, and described register connects described processor module, and described processor module is generally CPU.
320: processor module accesses described reseting module when detecting and starting, and is transformed to low level to control described RESET signal by high level.
Particularly, testing staff can start the instruction of detection to described processor module input by modes such as buttons, namely trigger described processor die BOB(beginning of block) to detect, when described processor module receives the instruction starting to detect, write operation is carried out to described reseting module, described RESET signal can be controlled and be transformed to low level by high level.
In addition, described method also comprises: described reseting module exports RESET signal to the reseting pin of ether interface chip, and controls described ether interface chip reset when described RESET signal is low level.
High level is transformed to after predetermined hold-time after described RESET signal is transformed to low level, because described RESET signal inputs to described ether interface chip by the reseting pin of described ether interface chip, like this when described RESET signal is transformed to high level by low level, described ether interface chip is triggered and starts to set up LINK.Wherein, the described scheduled time is greater than the time required for ether interface chip reset, is generally greater than 50 milliseconds, such as can be set to 200 milliseconds.
330: control module receives described RESET signal and link LINK signal, when described RESET signal becomes high level from low level, send enabling signal to counting module, when described LINK signal becomes low level from high level, send stop signal to described counting module.
Particularly, described LINK signal generally indicates pin to provide by the LINK of described ether interface chip.Described LINK signal is initially high level, represents that LINK sets up when described LINK signal becomes low level from high level.
In addition, described detection method also comprises:
Described control module sends reset signal when described RESET signal is low level to described counting module;
Count results, when receiving described reset signal, resets by described counting module.
340: counting module receives reference clock signal, and when receiving described enabling signal, start the cycle count to described reference clock signal, when receiving described stop signal, stop the cycle count to described reference clock signal, and export count results to described processor module.
Particularly, described reference clock signal is exported by clock module, therefore, also comprises before described step 340: clock module exports reference clock signal to described counting module.
The cycle of described reference clock signal can affect the accuracy of detection of described detection system, and generally, the cycle of described reference clock signal is 1 millisecond, and now the counting precision of described counter is millisecond rank; According to actual needs, the counting precision of described counter can also be improved further, such as make the cycle of described reference clock signal be 1 microsecond.In addition, the bit wide of described counting module should be enough large, to ensure correctly to export count results.
350: processor module obtains ether interface link settling time according to the computation of Period of described count results and described reference clock signal.
Particularly, described processor module described count results was multiplied with the cycle of described reference clock signal obtain ether interface link settling time.In addition, described method can also comprise: clock module described in processor die block access, to obtain the cycle of described reference clock signal, and adjusts the cycle of described reference clock signal.
Ether interface LINK settling time can be obtained by performing above-mentioned steps 310 to 350.
By repeating the above-mentioned steps 310 to 350 of pre-determined number, predetermined value (such as 5,10) individual ether interface LINK settling time can be obtained.Calculate the mean value of described predetermined value ether interface LINK settling time, using as final ether interface LINK settling time, accuracy can be improved further.
In the detection system of ether interface LINK settling time described in the embodiment of the present invention and method, reseting module, for exporting reset RESET signal to described control module, described RESET signal is initially high level; Processor module, for accessing described reseting module when detecting and starting, is transformed to low level to control described RESET signal by high level; Control module, for receiving described RESET signal and LINK signal, when described RESET signal becomes high level from low level, send enabling signal to described counting module, when described LINK signal becomes low level from high level, send stop signal to described counting module; Counting module, for receiving reference clock signal, and when receiving described enabling signal, start the cycle count to described reference clock signal, when receiving described stop signal, stop the cycle count to described reference clock signal, and export count results to described processor module; Processor module, also links settling time for obtaining ether interface according to the computation of Period of described count results and described reference clock signal.By adopting described detection system and method, the automation of measuring can be realized, the settling time of LINK can be measured fast and accurately, improve certainty of measurement high.
Above execution mode is only for illustration of the present invention; and be not limitation of the present invention; the those of ordinary skill of relevant technical field; without departing from the spirit and scope of the present invention; can also make a variety of changes and modification; therefore all equivalent technical schemes also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (12)
1. ether interface links the detection system of settling time, it is characterized in that, comprising: reseting module, processor module, control module and counting module;
Described reseting module, for exporting reset RESET signal to described control module, described RESET signal is initially high level;
Described processor module, for accessing described reseting module when detecting and starting, is transformed to low level to control described RESET signal by high level;
Described control module, for receiving described RESET signal and link LINK signal, when described RESET signal becomes high level from low level, send enabling signal to described counting module, when described LINK signal becomes low level from high level, send stop signal to described counting module; Wherein, described RESET signal inputs to described ether interface chip by the reseting pin of ether interface chip, and when described RESET signal is transformed to high level by low level, described ether interface chip is triggered and starts to set up LINK; Described LINK signal indicates pin to provide by the LINK of described ether interface chip, and described LINK signal is initially high level, when described LINK signal becomes low level from high level, represents that LINK sets up;
Described counting module, for receiving reference clock signal, and when receiving described enabling signal, start the cycle count to described reference clock signal, when receiving described stop signal, stop the cycle count to described reference clock signal, and export count results to described processor module;
Described processor module, also links settling time for obtaining ether interface according to the computation of Period of described count results and described reference clock signal;
Described control module, also for sending reset signal when described RESET signal is low level to described counting module;
Described counting module, also for when receiving described reset signal, resets count results.
2. detection system as claimed in claim 1, is characterized in that, described LINK signal indicates pin to export by the LINK of ether interface chip;
Described reseting module, also exports RESET signal for the reseting pin to described ether interface chip, and controls described ether interface chip reset when described RESET signal is low level.
3. detection system as claimed in claim 2, is characterized in that, be transformed to high level after described RESET signal is transformed to low level after predetermined hold-time, and the described scheduled time is greater than resetting time of described ether interface chip.
4. detection system as claimed in claim 1, it is characterized in that, described detection system also comprises: clock module;
Described clock module, for exporting described reference clock signal to described counting module;
Described processor module, also for accessing described clock module, to obtain the cycle of described reference clock signal, and adjusts the cycle of described reference clock signal.
5. detection system as claimed in claim 1, is characterized in that, described processor module, obtains ether interface link settling time specifically for described count results being multiplied with the cycle of described reference clock signal.
6. the detection system as described in any one of claim 1 to 5, is characterized in that,
Described processor module, the mean value also linking settling time for calculating a predetermined value ether interface links settling time as final ether interface.
7. ether interface links the detection method of settling time, it is characterized in that, comprising:
Reseting module exports reset RESET signal to control module, and described RESET signal is initially high level;
Processor module accesses described reseting module when detecting and starting, and is transformed to low level to control described RESET signal by high level;
Control module receives described RESET signal and link LINK signal, when described RESET signal becomes high level from low level, send enabling signal to counting module, when described LINK signal becomes low level from high level, send stop signal to described counting module; Wherein, described RESET signal inputs to described ether interface chip by the reseting pin of ether interface chip, and when described RESET signal is transformed to high level by low level, described ether interface chip is triggered and starts to set up LINK; Described LINK signal indicates pin to provide by the LINK of described ether interface chip, and described LINK signal is initially high level, when described LINK signal becomes low level from high level, represents that LINK sets up;
Counting module receives reference clock signal, and when receiving described enabling signal, start the cycle count to described reference clock signal, when receiving described stop signal, stop the cycle count to described reference clock signal, and export count results to described processor module;
Processor module obtains ether interface link settling time according to the computation of Period of described count results and described reference clock signal;
Described detection method also comprises:
Described control module sends reset signal when described RESET signal is low level to described counting module;
Count results, when receiving described reset signal, resets by described counting module.
8. detection method as claimed in claim 7, it is characterized in that, described detection method also comprises:
The LINK of ether interface chip indicates pin to export LINK signal to described control module;
Described reseting module exports RESET signal to the reseting pin of described ether interface chip, and controls described ether interface chip reset when described RESET signal is low level.
9. detection method as claimed in claim 8, is characterized in that, be transformed to high level after described RESET signal is transformed to low level after predetermined hold-time, and the described scheduled time is greater than resetting time of described ether interface chip.
10. detection method as claimed in claim 7, it is characterized in that, described detection method also comprises:
Clock module exports reference clock signal to described counting module;
Clock module described in processor die block access, to obtain the cycle of described reference clock signal, and adjusts the cycle of described reference clock signal.
11. detection methods as claimed in claim 7, is characterized in that, processor module obtains ether interface link settling time, being specially according to the computation of Period of described count results and described reference clock signal:
Processor module described count results was multiplied with the cycle of described reference clock signal obtain ether interface link settling time.
12. detection methods as described in any one of claim 7 to 11, it is characterized in that, described detection method also comprises:
Obtain a predetermined value ether interface and link settling time;
The mean value calculating described predetermined value ether interface link settling time is as final ether interface link settling time.
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| US20070053341A1 (en) * | 2005-09-06 | 2007-03-08 | Lizzi Ronald S | System and method for synchronizing companion electronic devices |
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| CN201185428Y (en) * | 2007-05-30 | 2009-01-21 | 上海泰坦通信工程有限公司 | Time synthesis measuring instrument |
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