CN103308076B - A kind of frequency-voltage conversion circuit - Google Patents
A kind of frequency-voltage conversion circuit Download PDFInfo
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- CN103308076B CN103308076B CN201310201528.0A CN201310201528A CN103308076B CN 103308076 B CN103308076 B CN 103308076B CN 201310201528 A CN201310201528 A CN 201310201528A CN 103308076 B CN103308076 B CN 103308076B
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Abstract
The present invention proposes a kind of frequency-voltage conversion circuit, mainly comprise logic control circuit and main body circuit, wherein use fixed current to capacitor charging and pass through delayed discharge, crest voltage on charging capacitor is preserved a period of time to gather electric capacity collection and to store this magnitude of voltage, simultaneously for avoid sampling switch on the impact of charging capacitor as far as possible, use source follower as high-speed buffer isolation charging capacitor and sample circuit, and by eliminating the sampled level displacement introduced by source follower based on the feedback circuit of operational amplifier, make the crest voltage on output voltage recovery charging capacitor.Owing to introducing high-speed buffer isolation charging capacitor and gathering switch, the present invention has higher precision relative to tradition rechargeable F-V converter, simultaneously due to the high bandwidth of delayed discharge and impact damper, the present invention can under wide incoming frequency scope reliably working.
Description
Technical field
The present invention relates to a kind of frequency-voltage conversion circuit, particularly a kind of frequency-voltage conversion circuit of high-precision wide input range.
Background technology
FV convertor or F-V converter, be a kind of control, detect in have the change of extensive use to send device.FV convertor is the nucleus module of FLL (Frequency-Locked Loop), and FLL is generally used for, in carrier tracking loop, directly following the tracks of carrier frequency, has good dynamic property.The principle of FLL circuit, mainly based on voltage to frequency conversion and voltage compare, has been come by the frequency-voltage conversion circuit (FVC) in FLL and error amplifier.In order to ensure the frequency accuracy that FLL exports, the precision of frequency-voltage conversion circuit is key wherein.
Structure about frequency-voltage conversion circuit has pertinent literature and proposes some different methods for designing.A kind of relatively more conventional method uses the frequency of low-pass filter to voltage conversion circuit, in the method, the response time of FVC determines primarily of the time constant of low-pass filter, if time constant is large, then the response time is slow, if but time constant is little, then voltage output can produce sizable ripple, and therefore instantaneous frequency measures the impossible of change.Wanlop proposes an analog sine waves FV convertor, this circuit is primarily of differentiator, integrator, linear transconductance divider and square root circuit composition, although the method can measure instantaneous frequency change, but incoming frequency is lower, be only 50Hz to 5KHz, and restriction input signal must be sinusoidal wave.Djemouai proposes dynamical CMOS frequency to electric pressure converter.This architectural configurations is simple, and do not need to use low-pass filter and larger electric capacity and resistance, therefore only need very little circuit area, output voltage does not exchange ripple.The method adopts charge redistribution principle, and to capacitor charging and the voltage gathered on electric capacity, the final voltage gathered on electric capacity is output voltage.But the method if desired reduces error, the periodicity of conversion must be increased, thus reduce slewing rate.And owing to crossing the Charge injection effect that Multi-Switch is introduced, reduce the output accuracy of this structure.
Summary of the invention
Goal of the invention: for above-mentioned prior art Problems existing and deficiency, the object of this invention is to provide the frequency-voltage conversion circuit that a kind of conversion accuracy is high, incoming frequency is wide.
Technical scheme: for achieving the above object, the invention provides a kind of frequency-voltage conversion circuit, comprises logic control circuit and main body circuit;
Wherein, described logic control circuit is the square-wave signal VCKPP of input fixed frequency, signal VCKP is obtained through two-stage phase inverter, signal VCKP obtains signal VCKN through one-level phase inverter, signal VCKN exports as first rejection gate one end input through nine grades of inverter delay elements again, the first rejection gate other end is input as VCKPP, rejection gate output signal is VCKN1, VCKN1 and VCKPP is as the input of second level rejection gate, output signal obtains signal VCKSP through one-level phase inverter again for VCKSP1, VCKSP1;
Described main body circuit comprises: current biasing circuit, constant current source circuit, transmission gate switch, charging capacitor, discharge switch, source follower, sample circuit, level displacement circuit and RC filter network, wherein, described current biasing circuit provides biased to described constant current source circuit, in front half input cycle, the control signal that described transmission gate switch provides according to described logic control circuit, makes described constant current source circuit to described charging capacitor charging, in rear half period, steady current is switched to ground by the control signal that described transmission gate switch provides according to described logic control circuit, pass through delayed discharge, crest voltage on described charging capacitor keeps, the control signal conducting that sampling switch simultaneously in described sample circuit provides according to described logic control circuit, the crest voltage on described charging capacitor is made to flow into described sample circuit after described source follower, described sample circuit collection also stores this magnitude of voltage, after sampling circuit samples terminates, the control signal that described sampling switch provides according to described logic control circuit disconnects, the control signal conducting that discharge switch provides according to described logic control circuit, described charging capacitor electric discharge, the voltage that described sample circuit exports simultaneously exports successively after described level displacement circuit and described RC filter network.
Described constant current source circuit comprises the 5th PMOS (M5), the 6th PMOS (M6), the 7th PMOS (M7), the 8th PMOS (M8) and the 20 NMOS tube (M20), the common-source amplifier of the current source load the 20 NMOS tube (M20) that wherein said 5th PMOS (M5) and the 6th PMOS (M6) are formed, described common-source amplifier and the 8th PMOS (M8) form feedback loop, and the drain voltage of the 7th PMOS (M7) is clamped in fixed value by described feedback loop.The fluctuation of the drain voltage of the 8th PMOS (M8) is under the effect of feedback loop, export the change of automatically adjustment the 8th PMOS (M8) grid voltage through common-source amplifier, to be fluctuated the curent change brought by the 8th PMOS (M8) drain voltage to offset.Because the output end voltage change of constant current source circuit only causes the change that the 7th PMOS (M7) drain terminal voltage is very little, therefore constant current source circuit externally shows the current value of approximately constant, and equivalent output impedance obtains and significantly improves.
Principle of work: the present invention, in front half input clock cycle, uses fixed current to charge to charging capacitor, gather and the crest voltage storing charging capacitor as output voltage.At the end of charge cycle, by delayed discharge, the crest voltage on charging capacitor is preserved a period of time so that late-class circuit collection store this magnitude of voltage, after collection sequential terminates, charging capacitor discharges, and enters the next cycle after electric discharge terminates, continue charging, gather, the process of electric discharge; In order to avoid the Charge injection effect of sampling switch is on the impact of crest voltage, employ voltage follower as the impact damper between charging capacitor and the collection electric capacity of sample circuit, Acquisition Circuit collection and store this impact damper export crest voltage, pass through based on the degenerative level shift circuit of amplifier, output end voltage value returns to the crest voltage on charging capacitor.
Beneficial effect: compared with prior art, the present invention is owing to introducing high-speed buffer isolation charging capacitor and gathering switch, make frequency inverted become the precision of voltage higher, simultaneously due to the high bandwidth of delayed discharge and impact damper, the present invention can under wide incoming frequency scope reliably working.
Accompanying drawing explanation
Fig. 1 is main body circuit schematic diagram of the present invention;
Fig. 2 is logic control circuit schematic diagram of the present invention;
Fig. 3 is logic control circuit of the present invention each output control terminal simulation waveform figure;
Fig. 4 is the voltage simulation waveform figure of charging capacitor voltage of the present invention and main body circuit major control end;
Fig. 5 is the simulation waveform figure of charging capacitor voltage of the present invention and output voltage;
Fig. 6 is the variation diagram of circuit incoming frequency of the present invention output voltage when changing within the scope of 10MHz-120MHz.
Embodiment
Below in conjunction with the drawings and specific embodiments, illustrate the present invention further.
The main circuit of frequency-voltage conversion circuit as shown in Figure 1, comprise current biasing circuit 1, constant current source circuit 2, transmission gate switch 3, charging capacitor 4, sample circuit 5, source follower 6, level displacement circuit 7, RC filter network 8 and electric discharge quick closing valve 9, current biasing circuit 1 provides biased to described constant current source circuit 2, in front half input cycle, the control signal that described transmission gate switch 3 provides according to described logic control circuit, makes described constant current source circuit 2 charge to described charging capacitor 4, in rear half period, steady current is switched to ground by the control signal that described transmission gate switch 3 provides according to described logic control circuit, pass through delayed discharge, crest voltage on described charging capacitor 4 keeps, the control signal conducting that sampling switch simultaneously in described sample circuit 5 provides according to described logic control circuit, the crest voltage on described charging capacitor is made to flow into described sample circuit 5 after described source follower 6, described sample circuit 5 gathers and stores this magnitude of voltage, after sample circuit 5 sampling terminates, the control signal that described sampling switch provides according to described logic control circuit disconnects, the control signal conducting that discharge switch 9 provides according to described logic control circuit, described charging capacitor 4 discharges, the voltage that described sample circuit 5 exports simultaneously exports successively after described level displacement circuit 7 and described RC filter network 8.
One end that main circuit is specially reference current source meets described first NMOS tube M1 respectively, the grid of described second NMOS tube M2 and described 20 NMOS tube M20, the source electrode of the drain electrode of the first NMOS tube M1 and the drain electrode of the second NMOS tube M2 and described 3rd NMOS tube M3, the drain electrode of the 3rd NMOS tube M3 and the 4th PMOS M4 is connected with after source shorted, 4th PMOS M4, 7th PMOS M7 is connected with the grid of the 6th PMOS M6, the grid of the 5th PMOS M5 connects the drain electrode of the 7th PMOS M7 and the source electrode of the 8th PMOS M8 respectively, the drain electrode of the 5th PMOS M5 connects the grid of the 8th PMOS M8 and the drain electrode of the 20 NMOS tube M20 respectively, the drain electrode of the 8th PMOS M8 meets the 9th NMOS tube M9 respectively, the drain electrode of the 12 NMOS tube M12 and the tenth PMOS M10, the source electrode of the 13 PMOS M13, the drain electrode of the 11 NMOS tube M11 connects the source electrode of the 9th NMOS tube M9 respectively, the drain electrode of the tenth PMOS M10, one end of charging capacitor C0 and the grid of the 14 NMOS tube M14, the source electrode of 11 NMOS tube M11, the source electrode of the 12 NMOS tube M12, the drain electrode of the 13 PMOS M13, the drain electrode of the 14 NMOS tube M14 and the other end ground connection of charging capacitor, the source electrode of the 14 NMOS tube M14 connects the 15 PMOS M15 and the drain electrode of the 17 PMOS M17 and the source electrode of the 16 NMOS tube M16 respectively, the drain electrode of the 16 NMOS tube M16 respectively with the source electrode of the 17 PMOS M17, sampling capacitance C1 one end is connected with the electrode input end of operational amplifier, the output terminal of operational amplifier is connected with the grid of the 19 PMOS M19 and one end of resistance R0 respectively, the source electrode of the 19 PMOS M19 is connected with the drain electrode of the 18 PMOS M18 and the negative input of operational amplifier respectively, the other end of resistance R0 is connected with one end of the second electric capacity C2, the other end ground connection of the second electric capacity C2.
Wherein, current biasing circuit 1 is made up of reference current source, the first NMOS tube M1, the second NMOS tube M2, the 3rd NMOS tube M3 and the 4th PMOS M4,3rd NMOS tube M3 makes the second NMOS tube M2 similar to the voltage between source electrode to the drain electrode of the 4th PMOS M4, thus makes current mirror replica current more accurate.Constant current source circuit 2 adopts gain bootstrap technology, to increase the output impedance of this current source circuit, this constant current source circuit 2 comprises the 5th PMOS M5, the 6th PMOS M6, the 7th PMOS M7, the 8th PMOS M8 and the 20 NMOS tube M20, the common-source amplifier of current source load the 20 NMOS tube M20 that wherein said 5th PMOS M5 and the 6th PMOS M6 is formed, described common-source amplifier and the 8th PMOS M8 form feedback loop, and the drain voltage of the 7th PMOS M7 is clamped in fixed value by described feedback loop.The fluctuation of the drain voltage of the 8th PMOS M8, under the effect of feedback loop, exports the change of the grid voltage of automatically adjustment the 8th PMOS M8 through common-source amplifier, to be fluctuated the curent change brought by the 8th PMOS M8 drain voltage to offset.Because the output end voltage change of this current source circuit only causes the change that the drain voltage of the 7th PMOS M7 is very little, this current source circuit externally shows the current value of approximately constant, and equivalent output impedance obtains and significantly improves.
As shown in Figure 2, logic control circuit is the square-wave signal VCKPP of input fixed frequency, signal VCKP is obtained through two-stage phase inverter, signal VCKP obtains signal VCKN through one-level phase inverter, signal VCKN exports as first rejection gate one end input through nine grades of inverter delay elements again, the first rejection gate other end is input as VCKPP, rejection gate output signal is VCKN1, VCKN1 and VCKPP is as the input of second level rejection gate, output signal obtains signal VCKSP through one-level phase inverter again for VCKSP1, VCKSP1;
Wherein, square-wave signal VCKPP obtains through two phase inverters the grid that signal VCKP inputs the 9th NMOS tube M9 and the 13 PMOS M13 from the input end of logic control circuit, another control signal VCKN contrary with VCKP inputs the grid of the tenth PMOS M10 and the 12 NMOS tube M12,9th NMOS tube M9 and the tenth PMOS M10 forms transmission gate switch, connects charging capacitor C0.In front half input clock cycle, the 9th NMOS tube M9 and the tenth PMOS M10 forms transmission gate switch conducting, is charged to charging capacitor C0 by constant current source circuit, rear half input cycle, 9th NMOS tube M9 and the tenth PMOS M10 forms transmission gate switch and disconnects, charging terminates, and the voltage peak on charging capacitor C0 keeps a period of time, the now transmission gate switch conducting of the 12 NMOS tube M12 and the 13 PMOS M13 composition, late-class circuit starts sampling, bias current sources is formed into the path on ground simultaneously, charging capacitor C0 connects first order source follower, the output of first order source follower connects the transmission gate switch of the 17 PMOS M17 and the 16 NMOS tube M16 composition, wherein, the signal VCKSP1 that logic control circuit exports inputs the grid of the 16 NMOS tube M16, VCKSP1 obtains signal VCKSP through one-level phase inverter again and is input to the 17 PMOS M17, the electrode input end of the output termination operational amplifier of the 17 PMOS M17, the output terminal of operational amplifier connects second level source follower, the negative pole input of the output termination operational amplifier of second level source follower forms negative feedback, the output terminal of operational amplifier is connected with the RC filter network that resistance R0 and electric capacity C2 form simultaneously, after collection sequential terminates, charging capacitor C0 is by the 11 NMOS tube M11 electric discharge, enter the next cycle after electric discharge terminates, continue charging, crest voltage keeps, the process of electric discharge,
Wherein, first order source follower is made up of the 14 NMOS tube M14 and the 15 PMOS M15, second level source follower is made up of the 18 PMOS M18 and the 19 PMOS M19, the level displacement circuit that the level shift that first order source follower produces Vgs be made up of amplifier and second level source follower rear class is offset, thus voltage on the voltage of guarantee operational amplifier output terminal and charging capacitor C0 is equal.
Logical circuit each output control terminal simulation waveform figure, is followed successively by VCKPP signal from top to bottom as shown in Figure 3, VCKP signal, VCKN signal, VCKN1 signal, VCKSP1 signal and VCKSP signal, wherein VCKPP signal is input square-wave signal, the as shown in Figure 3 time sequence status of each signal.In inventing as shown in Figure 4, the voltage simulation waveform figure of charging capacitor C0 voltage and main body circuit major control end, is followed successively by charging capacitor C0 voltage, VCKP, VCKN1 and VCKSP1 from top to bottom in figure; As seen from the figure when VCKP signal is high level, charging capacitor C0 is in charged state, and when VCKSP1 signal is high level, charging capacitor C0 is in voltage hold mode, and when VCKN1 signal is high level, charging capacitor C0 is in discharge condition.The charging capacitor C0 voltage invented as shown in Figure 5 and the simulation waveform figure of output voltage, as can be seen from the figure, output voltage raises gradually, tends towards stability at 5 all after dates, stable value is equal with the peak value of charging capacitor (C0), and therefore voltage to frequency conversion is more accurate.As shown in Figure 6, when circuit incoming frequency of the present invention changes within the scope of 10MHz-120MHz, the variation diagram of output voltage, bold portion is the relation curve of output voltage and frequency input signal, dotted portion is ask result reciprocal to this curve, be be the straight line of a fixed slope in 10MHz-110MHz in incoming frequency, demonstrate the inverse relation of output voltage and incoming frequency.As can be seen from the figure, within the scope of the incoming frequency of 10MHz-110MHz, this slope is substantially constant, and therefore this FV convertor accurately can distinguish the incoming frequency of 10MHz-110MHz, has shown incoming frequency scope wider.
Claims (2)
1. a frequency-voltage conversion circuit, is characterized in that: comprise logic control circuit and main body circuit,
Wherein, described logic control circuit is the square-wave signal VCKPP of input fixed frequency, signal VCKP is obtained through two-stage phase inverter, signal VCKP obtains signal VCKN through one-level phase inverter, signal VCKN exports as first rejection gate one end input through nine grades of inverter delay elements again, the first rejection gate other end is input as VCKPP, rejection gate output signal is VCKN1, VCKN1 and VCKPP is as the input of second level rejection gate, output signal obtains signal VCKSP through one-level phase inverter again for VCKSP1, VCKSP1;
Described main body circuit comprises: current biasing circuit, constant current source circuit, transmission gate switch, discharge switch, charging capacitor, source follower, sample circuit, level displacement circuit and RC filter network, wherein, described current biasing circuit provides biased to described constant current source circuit, in front half input cycle, the control signal VCKP that described transmission gate switch provides according to described logic control circuit and VCKN, makes described constant current source circuit to described charging capacitor charging, in rear half period, steady current is switched to ground by the control signal VCKN that described transmission gate switch provides according to described logic control circuit and VCKPP, pass through delayed discharge, crest voltage on described charging capacitor keeps, the control signal VCKSP that sampling switch simultaneously in described sample circuit provides according to described logic control circuit and VCKSP1 conducting, the crest voltage on described charging capacitor is made to flow into described sample circuit after described source follower, described sample circuit collection also stores this magnitude of voltage, after sampling circuit samples terminates, the control signal VCKSP that described sampling switch provides according to described logic control circuit and VCKSP1 disconnects, the control signal VCKN1 conducting that discharge switch provides according to described logic control circuit, described charging capacitor electric discharge, the voltage that described sample circuit exports simultaneously exports successively after described level displacement circuit and described RC filter network.
2. frequency-voltage conversion circuit according to claim 1, it is characterized in that: the constant current source circuit in main circuit comprises the 5th PMOS (M5), 6th PMOS (M6), 7th PMOS (M7), 8th PMOS (M8) and the 20 NMOS tube (M20), wherein said 5th PMOS (M5) and the 20 NMOS tube (M20) form common-source amplifier, described common-source amplifier and the 8th PMOS (M8) form feedback loop, the drain voltage of the 7th PMOS (M7) is clamped in fixed value by described feedback loop, one end of reference current source in main circuit connects the first NMOS tube (M1) respectively, the grid of the second NMOS tube (M2) and described 20 NMOS tube (M20), the source electrode of the drain electrode of the first NMOS tube (M1) and the drain electrode of the second NMOS tube (M2) and the 3rd NMOS tube (M3), the drain electrode of the 3rd NMOS tube (M3) and the 4th PMOS (M4) is connected with after source shorted, 4th PMOS (M4), 7th PMOS (M7) is connected with the grid of the 6th PMOS (M6), the grid of the 5th PMOS (M5) connects the drain electrode of the 7th PMOS (M7) and the source electrode of the 8th PMOS (M8) respectively, the drain electrode of the 5th PMOS (M5) connects the grid of the 8th PMOS (M8) and the drain electrode of the 20 NMOS tube (M20) respectively.
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| CN201310201528.0A CN103308076B (en) | 2013-05-24 | 2013-05-24 | A kind of frequency-voltage conversion circuit |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104597316A (en) * | 2015-01-08 | 2015-05-06 | 聚光科技(杭州)股份有限公司 | Weak current detecting device and method |
| CN105281774B (en) * | 2015-10-10 | 2018-11-16 | 陕西千山航空电子有限责任公司 | A kind of frequency turns potential circuit and method |
| CN105628953B (en) * | 2016-01-13 | 2019-08-06 | 中国航空动力机械研究所 | Aero-engine dynamic test system, frequency-voltage transformation circuit and method |
| CN105811966B (en) * | 2016-02-26 | 2019-06-04 | 上海华虹宏力半导体制造有限公司 | Frequency turns potential circuit |
| CN107315440B (en) * | 2017-08-29 | 2018-09-25 | 桂林电子科技大学 | A kind of high-speed broadband band frequency-voltage conversion circuit |
| CN110061703A (en) * | 2019-05-22 | 2019-07-26 | 澳特翼南京电子科技有限公司 | A kind of High accuracy voltage follower of wide input voltage |
| CN116094526A (en) * | 2022-12-31 | 2023-05-09 | 成都电科星拓科技有限公司 | Method and device for converting pulse frequency into voltage |
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