CN103281076A - Clock source and signal processing method thereof - Google Patents
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- CN103281076A CN103281076A CN2013102031391A CN201310203139A CN103281076A CN 103281076 A CN103281076 A CN 103281076A CN 2013102031391 A CN2013102031391 A CN 2013102031391A CN 201310203139 A CN201310203139 A CN 201310203139A CN 103281076 A CN103281076 A CN 103281076A
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Abstract
The embodiment of the invention discloses a clock source and a signal processing method thereof, belongs relates to the field of electronic information and solves the problems of complex design and long production cycle of such products. The clock source comprises at least one satellite navigation receiver, a clock generator, a processor and a high-stability crystal oscillator; the clock generator is directly connected with the high-stability crystal oscillator, the processor is directly connected with and the at least one satellite navigation receiver, and the processor and isthe clock generator are directly connected with the clock generator and the at least one satellite navigation receiver. The clock source and the signal processing method thereof are used for processing clock signals.
Description
Technical field
The present invention relates to electronic information field, relate in particular to a kind of clock source and method for processing signals thereof.
Background technology
Along with science and technology development, the satellite synchronizing clock source in the demand of high-tech sectors such as Aero-Space, weapon test, astronomical observation more and more widely.Current most satellite synchronizing clock product-derived all is to receive navigation satellite (GPS (Global Positioning System, global positioning system) or Beidou satellite navigation system) 1PPS (1pulse per second, pulse per second (PPS)) signal, 1PPS signal fusing with the generation of local clock frequency division, by processor both time difference data being carried out filtering again handles, control D/A (Digital to Analog converter then, digital-to-analogue conversion) transducer produces corresponding aanalogvoltage, realizes calibrating the function of local clock output with this.
But present product needed is produced special time difference measurement circuit, frequency division frequency multiplier circuit and D/A change-over circuit separately the navigation satellite 1PPS signal that the clock source receives is handled, so the product design complexity, and the production cycle is longer.
Summary of the invention
Embodiments of the invention provide a kind of clock source and method for processing signals thereof, can reduce the design complexities of product, the production cycle of shortening product.
For achieving the above object, embodiments of the invention adopt following technical scheme:
First aspect, embodiments of the invention provide a kind of clock source, comprising:
At least one satellite navigation receiver, clock generator, processor and high stability crystal oscillator, described clock generator directly is connected with described high stability crystal oscillator, described processor and described at least one satellite navigation receiver, described processor directly is connected with described clock generator and described at least one satellite navigation receiver, wherein
Described at least one satellite navigation receiver is used for receiving at least one road satellite navigation signals, described at least one road satellite navigation signals demodulation is generated the synchronous pps pulse per second signal of at least one road satellite, and the synchronous pps pulse per second signal of described at least one road satellite is sent to described processor and described clock generator;
Described processor is used for receiving the synchronous pps pulse per second signal of described at least one road satellite that described at least one satellite navigation receiver sends, the synchronous pps pulse per second signal of road satellite that selection is in the lock state and priority is higher generates control command and described control command is sent to described clock generator according to selection result as the target pps pulse per second signal;
Described high stability crystal oscillator is used for generating reference frequency signal and described reference frequency signal is sent to described clock generator;
Described clock transmitter is used for receiving the described reference frequency signal that described high stability crystal oscillator sends, receive the described control command that described processor sends, and receive the synchronous pps pulse per second signal of satellite of the described target pps pulse per second signal of conduct that described at least one satellite navigation receiver sends according to described control command, generate standard-frequency signal with reference to described reference frequency signal and described target pps pulse per second signal.
In first kind of possible implementation, in conjunction with first aspect, described clock generator comprises: system clock generator, control unit, digital phase-locked loop, digital to analog converter, filtering forming circuit and clock distributor;
Wherein, described system clock generator is used for receiving the described reference clock signal that described high stability crystal oscillator sends, and produces system clock frequency according to described reference clock signal;
Described control unit, be used for receiving the described control command that described processor sends, and control the synchronous pps pulse per second signal of satellite that described input switch unit receives the described target pps pulse per second signal of conduct that described at least one satellite navigation receiver sends according to described control command, and by described input switch unit described target pps pulse per second signal is sent to described digital phase-locked loop;
Described digital phase-locked loop is used for receiving the described target pps pulse per second signal that described input switch unit sends, and generates digital signal with reference to described target pps pulse per second signal and described system clock frequency, and described digital signal is sent to digital to analog converter;
Described digital to analog converter, be used for receiving the described digital signal that described digital phase-locked loop sends, described digital signal is changed into analog signal, and after described analog signal carried out filtering and handle by described filtering forming circuit, carry out clock distribution by described clock distributor and export described standard-frequency signal.
In second kind of possible implementation, in conjunction with first kind of first aspect possible implementation, described digital phase-locked loop comprises: Direct Digital Frequency Synthesizers, digital loop filters, frequency divider, phase discriminator and frequency adjustment word generator;
Wherein, described Direct Digital Frequency Synthesizers is used for generating digital signal with reference to described system clock frequency, and described digital signal is sent to described frequency divider;
Described frequency divider is used for receiving the digital signal that described Direct Digital Frequency Synthesizers sends, and handles by frequency division, isolates one tunnel inner pps pulse per second signal from described digital signal, and sends described inner pps pulse per second signal to described phase discriminator;
Described phase discriminator, be used for receiving the described inner pps pulse per second signal of described target pps pulse per second signal and the transmission of described frequency divider, measure the phase difference of described inner pps pulse per second signal and described target pps pulse per second signal, and after described phase difference carried out filtering and handle by described digital loop filters, be sent to described frequency adjustment word generator;
Described frequency adjustment word generator be used for to receive the described phase difference that described phase discriminator sends, and according to the tuning word of described phase difference generated frequency, and described frequency tuning word is sent to described Direct Digital Frequency Synthesizers;
Described Direct Digital Frequency Synthesizers also be used for to receive the described frequency tuning word that described frequency adjustment word generator sends, and according to the frequency of the described digital signal of described frequency tuning regulation.
In the third possible implementation, in conjunction with second kind of first aspect possible implementation, described Direct Digital Frequency Synthesizers specifically is used for according to formula
Regulate the frequency of described digital signal, wherein, F
DdsBe the frequency of described digital signal, M is described frequency tuning word, and N is the Clock Multiplier Factor of systematic clock generator, f
XtalFrequency for described reference clock signal.
In the 4th kind of possible implementation, in conjunction with second kind of first aspect possible implementation, described processor also is used for the described frequency tuning word of record, when described at least one satellite navigation receiver all is in out-of-lock condition, the described frequency tuning word that records is sent to described clock generator;
Described clock generator, also be used for receiving by described control unit the described frequency tuning word of the record of described processor transmission, and the described frequency tuning word of described record is forwarded to described Direct Digital Frequency Synthesizers by described frequency adjustment word generator, so that described Direct Digital Frequency Synthesizers is according to the frequency of the described digital signal of described frequency tuning regulation.
In the 5th kind of possible implementation, in conjunction with above-mentioned each described clock source, described clock source also comprises: display screen;
Described at least one satellite navigation receiver also is used for the satellite navigation signals demodulation of described at least one road is generated world UTC unified time temporal information, and sends described UTC temporal information to described processor;
Described processor also be used for to receive described UTC temporal information, select to be in the lock state and the UTC temporal information of the synchronous pps pulse per second signal correspondence of road satellite that priority is higher as object time information, and described object time information is sent to display screen;
Described display screen is used for receiving the described object time information that described processor sends, and shows described temporal information.
The method that second aspect, embodiments of the invention provide a kind of clock signal to handle comprises:
The clock source receives at least one road satellite navigation signals;
Described at least one road satellite navigation signals demodulation is generated the synchronous pps pulse per second signal of at least one road satellite;
The synchronous pps pulse per second signal of road satellite that selection is in the lock state and priority is higher is as the target pps pulse per second signal;
Generate reference frequency signal, generate standard-frequency signal with reference to described reference frequency signal and described target pps pulse per second signal.
In first kind of possible implementation, in conjunction with first aspect, the described reference frequency signal of described reference and described target pps pulse per second signal generate standard-frequency signal, comprising:
Produce system clock frequency according to described reference frequency signal;
Generate digital signal with reference to described target pps pulse per second signal and described system clock frequency;
Described digital signal is changed into analog signal, described analog signal is carried out filtering handle, and the analog signal after the filtering processing is carried out clock distribution export described standard-frequency signal.
In second kind of possible implementation, in conjunction with first kind of first aspect possible implementation, the described target pps pulse per second signal of described reference is converted to digital signal with described system clock frequency, comprising:
Generate digital signal with reference to described system clock frequency;
Handle by frequency division, from described digital signal, isolate inner pps pulse per second signal;
Measure the phase difference of described inner pps pulse per second signal and described target pps pulse per second signal;
According to the tuning word of described phase difference generated frequency, and according to the frequency of the described digital signal of described frequency tuning regulation.
In the third possible implementation, described according to the tuning word of described phase difference generated frequency in conjunction with second kind of first aspect possible implementation, and according to the frequency of the described digital signal of described frequency tuning regulation, comprising:
According to formula
Regulate the frequency of described digital signal, wherein F
DdsBe the frequency of described digital signal, M is described frequency tuning word, and N is the Clock Multiplier Factor of described systematic clock generator, f
XtalFrequency for described reference clock signal.
In the 4th kind of possible implementation, in conjunction with second kind of first aspect possible implementation, described method also comprises:
Record described frequency tuning word;
When the synchronous pps pulse per second signal of described at least one road satellite all is in out-of-lock condition, the frequency of the described digital signal of described frequency tuning regulation of reference record.
In the 5th kind of possible implementation, in conjunction with above-mentioned arbitrary method, described method also comprises:
The satellite navigation signals demodulation of described at least one road is generated world UTC unified time temporal information;
The UTC temporal information of the synchronous pps pulse per second signal correspondence of road satellite that selection is in the lock state and priority is higher is as object time information;
Show described object time information.
Clock source and method for processing signals thereof that the embodiment of the invention provides, handle the synchronous pps pulse per second signal of satellite by utilizing a kind of clock generator, with reference to the synchronous pps pulse per second signal of satellite and the direct outputting standard frequency signal of internal reference clock signal, reduced product design complexities, shortened the production cycle.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
A kind of clock source structure schematic diagram that Fig. 1 provides for the embodiment of the invention;
A kind of clock generator structure chart that Fig. 2 provides for the embodiment of the invention;
A kind of method for processing signals schematic flow sheet that Fig. 3 provides for the embodiment of the invention;
The another kind of method for processing signals schematic flow sheet that Fig. 4 provides for the embodiment of the invention.
Reference numeral:
The 11-processor;
The 12-clock generator;
13-first satellite navigation receiver;
14-second satellite navigation receiver;
The 15-high stability crystal oscillator;
The 16-display screen;
21-system clock generator;
22-imports switch unit;
The 23-control unit;
The 24-clock distributor;
25-filtering forming circuit;
The 26-digital to analog converter;
The 27-digital phase-locked loop;
The 271-frequency divider;
The 272-phase discriminator;
The 273-digital loop filters;
274-frequency adjustment word generator;
The 275-Direct Digital Frequency Synthesizers.
Embodiment
Below in conjunction with accompanying drawing a kind of clock source and method for processing signals thereof that the embodiment of the invention provides are carried out in detail, intactly describe.
Embodiments of the invention provide a kind of clock source, with reference to shown in Figure 1, this clock source comprises: at least one satellite navigation receiver is (among Fig. 1 with first satellite navigation receiver 13,14 two satellite navigations of second satellite navigation receiver are received as example and describe), clock generator 12, processor 11 and high stability crystal oscillator 15, clock generator 12 and high stability crystal oscillator 15, processor 11 and two satellite navigation receivers directly connect, processor 11 directly is connected with clock generator 12 and two satellite navigation receivers, wherein, processor 11 is connected with clock generator 12 by four-wire system SPI (Serial Peripheral Interface, synchronous serial Peripheral Interface) bus.Preferred 2～8 of the quantity of satellite navigation receiver, here do not do concrete restriction, Beidou satellite navigation system is to use two kinds of satellite navigation systems more widely because the GPS global positioning system is unified, so be that example describes in this clock signal with these two kinds of satellites, the clock signal of other satellites also can receive.
First satellite navigation receiver 13 and second satellite navigation receiver 14 are used for receiving at least one road satellite navigation signals, two satellite navigation receivers are distinguished the satellite navigation signals of receiving world locational system and Beidou satellite navigation system, at least one road satellite navigation signals demodulation that receives is generated the synchronous pps pulse per second signal of at least one road satellite, and at least one road synchronous pps pulse per second signal of satellite that will generate is sent to processor 11 and clock generator 12.
High stability crystal oscillator 15 is used for generating reference frequency signal and reference frequency signal is sent to clock generator 12, and optional, the frequency of this signal adopts 10MHz.
The clock transmitter is used for receiving the reference frequency signal of high stability crystal oscillator 15 transmissions and the control command that processor 11 sends, and according to control command receiving target pps pulse per second signal, generates standard-frequency signal with reference to reference frequency signal and target pps pulse per second signal.Wherein, the frequency of the standard-frequency signal of final output can set up on their own by clock generator according to user's request, and the standard-frequency signal commonly used of general output can be signal of 1PPS (pps pulse per second signal), 10MHz etc.This moment, the clock source was operated in taming pattern.
The clock source that the embodiment of the invention provides, handle the synchronous pps pulse per second signal of satellite by utilizing clock generator, with reference to the synchronous pps pulse per second signal of satellite and the direct outputting standard frequency signal of internal reference clock signal, reduced product design complexities, shortened the production cycle.
Embodiments of the invention also provide a kind of concrete clock source, with reference to shown in Figure 1, this clock source comprises: first satellite navigation receiver 13, second satellite navigation receiver 14, clock generator 12, processor 11, high stability crystal oscillator 15 and display screen 16, clock generator 12 directly is connected with high stability crystal oscillator 15, processor 11 and two satellite navigation receivers, and processor 11 directly is connected with clock generator 12, display screen 16 and two satellite navigation receivers.
Optionally, with reference to shown in Figure 2, clock generator 12 specifically comprises: system clock generator 21, input switch unit 22, control unit 23, digital phase-locked loop 27, digital to analog converter 26, filtering forming circuit 25 and clock distributor 24.
With reference to shown in Figure 2, digital phase-locked loop 27 specifically comprises: frequency divider 271, phase discriminator 272, digital loop filters 273, frequency adjustment word generator 274, Direct Digital Frequency Synthesizers 275.
Wherein, first satellite navigation receiver 13 and second satellite navigation receiver 14 are used for receiving at least one road satellite navigation signals, two satellite navigation receivers are distinguished the satellite navigation signals of receiving world locational system and Beidou satellite navigation system, at least one road satellite navigation signals demodulation that receives is generated the synchronous pps pulse per second signal of at least one road satellite and UTC (Universal Time Coordinated, Coordinated Universal Time(UTC)) temporal information is sent to processor 11 and clock generator 12 with the synchronous pps pulse per second signal of at least one road satellite and UTC temporal information.
Here, priority can be the primary and backup relation of user-defined two satellite navigation receivers, and namely priority is higher when satellite navigation receiver is main receiver, and priority is lower when satellite navigation receiver is emergency receiver.
High stability crystal oscillator 15 is used for generating reference frequency signal and reference frequency signal is sent to clock generator 12, and general, the frequency of this signal is 10MHz.
In clock generator 12 inside, system clock generator 21 for the reference clock signal that receives high stability crystal oscillator 15, produces system clock frequency according to reference clock signal.
In digital phase-locked loop 27, Direct Digital Frequency Synthesizers 275 is used for reference target pps pulse per second signal and system clock frequency and generates digital signal, and digital signal is sent to frequency divider 271.
Frequency adjustment word generator 274 be used for to receive the phase difference that phase discriminator 272 sends, and according to the tuning word of phase difference generated frequency, and the frequency tuning word is sent to Direct Digital Frequency Synthesizers 275.
Direct Digital Frequency Synthesizers 275 is used for receive frequency and regulates the frequency tuning word that word generator 274 sends, and according to the frequency of frequency tuning regulation digital signal.
Concrete, Direct Digital Frequency Synthesizers 275 is according to formula
Regulate the frequency of digital signal, wherein, F
DdsBe the frequency of digital signal, M is the frequency tuning word, and N is the Clock Multiplier Factor of systematic clock generator 102, f
XtalFrequency for reference clock signal.
Digital phase-locked loop 27 is by frequency divider 271, phase discriminator 272, digital loop filters 273, frequency adjustment word generator 274, the tuning word of Direct Digital Frequency Synthesizers 275 circulation generated frequencies, at first, Direct Digital Frequency Synthesizers 275 frame of reference clock frequencies generate unsettled digital signal, from this digital signal, divide the one tunnel inner pps pulse per second signal that occurs frequently to compare with the target pps pulse per second signal that receives, produce the frequency tuning word and regulate the frequency of this digital signal, digital signal after will regulating again feeds back to frequency divider 271, generate new inside pps pulse per second signal, itself and the target pps pulse per second signal that receives are again compared, further regulate the frequency of this digital signal, the adjusting of so constantly this digital signal and outside target pulse signal being compared can be so that inner pps pulse per second signal remains consistent with the frequency of the target pps pulse per second signal that receives.
Said process, the clock source is operated in taming pattern, in order to guarantee when at least one satellite navigation receiver all is in out-of-lock condition, comparatively precise standard frequency signal is still enough exported in the clock source, in the process of the tuning word of generated frequency, processor 11 also is used for the tuning word of recording frequency, when at least one satellite navigation receiver all is in out-of-lock condition, the frequency tuning word that records is sent to clock generator 12.
Like this, under out-of-lock condition, the frequency of the digital signal that the Direct Digital synthesizer produces regulated in frequency tuning word during lock-out state by record, can be so that the digital signal of output still can keep higher accuracy and stability in the out-of-lock condition of short-term, this moment, the clock source was operated in the maintenance pattern.
Digital to analog converter 26, be used for receiving the digital signal that Direct Digital Frequency Synthesizers 275 sends, digital signal is changed into analog signal, and analog passband signal is crossed filtering forming circuit 25 carry out carrying out clock distribution outputting standard frequency signal by clock distributor 24 after filtering is handled.Herein, the frequency of standard-frequency signal can set up on their own according to user's needs, and the most frequently used is 1PPS signal and 10MHz signal, and, clock distributor 24 can distribute the multichannel standard-frequency signal simultaneously, and preferred situation is the accurate frequency signal of output 4 road signs.
Concrete, first satellite navigation receiver 103 in the embodiment of the invention and second satellite navigation receiver 104 are selected M12T time service type GPS receiver and the Big Dipper two generations time service type receiver respectively for use, high stability crystal oscillator is selected the MV89 high stability crystal oscillator for use, processor is selected the STM32F107VC microprocessor for use, and clock generator 102 selects for use the AD9548 chip as clock generator.
The clock source that the embodiment of the invention provides, handle the synchronous pps pulse per second signal of satellite by utilizing clock generator, with reference to the synchronous pps pulse per second signal of satellite and the direct outputting standard frequency signal of internal reference clock signal, reduced product design complexities, shortened the production cycle.
Embodiments of the invention provide a kind of Signal Processing method, and with reference to shown in Figure 3, this method comprises:
301, the clock source receives at least one road satellite navigation signals.
302, the satellite navigation signals demodulation of at least one road is generated the synchronous pps pulse per second signal of at least one road satellite.
303, the synchronous pps pulse per second signal of road satellite that selection is in the lock state and priority is higher is as the target pps pulse per second signal.
304, generate reference frequency signal, generate standard-frequency signal with reference to reference frequency signal and target pps pulse per second signal.
The method for processing signals that the embodiment of the invention provides, handle the synchronous pps pulse per second signal of satellite by utilizing clock generator, with reference to the synchronous pps pulse per second signal of satellite and the direct outputting standard frequency signal of internal reference clock signal, reduced product design complexities, shortened the production cycle.
Embodiments of the invention also provide another kind of method for processing signals, and with reference to shown in Figure 4, this method comprises:
401, the clock source receives at least one road satellite navigation signals.
402, the satellite navigation signals demodulation of at least one road is generated the synchronous pps pulse per second signal of at least one road satellite and UTC temporal information.
403, the synchronous pps pulse per second signal of road satellite that selection is in the lock state and priority is higher is as the target pps pulse per second signal, the UTC temporal information of the synchronous pps pulse per second signal correspondence of road satellite that selection is in the lock state and priority is higher is as object time information, and shows this object time information.
404, generate reference frequency signal, produce system clock frequency according to reference frequency signal.
405, the frame of reference clock frequency generates digital signal.
406, from digital signal, isolate one tunnel inner pps pulse per second signal, and measure the phase difference of inner pps pulse per second signal and target pps pulse per second signal.
407, according to the tuning word of phase difference generated frequency, and according to the frequency of frequency tuning regulation digital signal.
Concrete, according to formula
Regulate the frequency of digital signal, wherein F
DdsBe the frequency of digital signal, M is the frequency tuning word, and N is the Clock Multiplier Factor of systematic clock generator 102, f
XtalFrequency for reference clock signal.
408, the tuning word of recording frequency, when at least one road synchronous pps pulse per second signal of satellite all is in out-of-lock condition, the frequency of the frequency tuning regulation digital signal of reference record.
409, digital signal is changed into analog signal.
410, analog signal is carried out filtering and handle, and the analog signal after the filtering processing is carried out clock distribution outputting standard frequency signal.
The method for processing signals that the embodiment of the invention provides, handle the synchronous pps pulse per second signal of satellite by utilizing clock generator, with reference to the synchronous pps pulse per second signal of satellite and the direct outputting standard frequency signal of internal reference clock signal, reduced product design complexities, shortened the production cycle.
More than; only be the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.
Claims (12)
1. clock source, it is characterized in that, comprise: at least one satellite navigation receiver, clock generator, processor and high stability crystal oscillator, described clock generator directly is connected with described high stability crystal oscillator, described processor and described at least one satellite navigation receiver, described processor directly is connected with described clock generator and described at least one satellite navigation receiver, wherein
Described at least one satellite navigation receiver is used for receiving at least one road satellite navigation signals, described at least one road satellite navigation signals demodulation is generated the synchronous pps pulse per second signal of at least one road satellite, and the synchronous pps pulse per second signal of described at least one road satellite is sent to described processor and described clock generator;
Described processor is used for receiving the synchronous pps pulse per second signal of described at least one road satellite that described at least one satellite navigation receiver sends, the synchronous pps pulse per second signal of road satellite that selection is in the lock state and priority is higher generates control command and described control command is sent to described clock generator according to selection result as the target pps pulse per second signal;
Described high stability crystal oscillator is used for generating reference frequency signal and described reference frequency signal is sent to described clock generator;
Described clock transmitter is used for receiving the described reference frequency signal that described high stability crystal oscillator sends, receive the described control command that described processor sends, and receive the synchronous pps pulse per second signal of satellite of the described target pps pulse per second signal of conduct that described at least one satellite navigation receiver sends according to described control command, generate standard-frequency signal with reference to described reference frequency signal and described target pps pulse per second signal.
2. clock according to claim 1 source is characterized in that described clock generator comprises: system clock generator, control unit, digital phase-locked loop, digital to analog converter, filtering forming circuit and clock distributor;
Wherein, described system clock generator is used for receiving the described reference clock signal that described high stability crystal oscillator sends, and produces system clock frequency according to described reference clock signal;
Described control unit, be used for receiving the described control command that described processor sends, and receive the synchronous pps pulse per second signal of satellite of the described target pps pulse per second signal of conduct that described at least one satellite navigation receiver sends according to described control command control input switch unit, and by described input switch unit described target pps pulse per second signal is sent to described digital phase-locked loop;
Described digital phase-locked loop is used for receiving the described target pps pulse per second signal that described input switch unit sends, and generates digital signal with reference to described target pps pulse per second signal and described system clock frequency, and described digital signal is sent to digital to analog converter;
Described digital to analog converter, be used for receiving the described digital signal that described digital phase-locked loop sends, described digital signal is changed into analog signal, and after described analog signal carried out filtering and handle by described filtering forming circuit, carry out clock distribution by described clock distributor and export described standard-frequency signal.
3. clock according to claim 2 source is characterized in that described digital phase-locked loop comprises: Direct Digital Frequency Synthesizers, digital loop filters, frequency divider, phase discriminator and frequency adjustment word generator;
Wherein, described Direct Digital Frequency Synthesizers is used for generating digital signal with reference to described system clock frequency, and described digital signal is sent to described frequency divider;
Described frequency divider is used for receiving the described digital signal that described Direct Digital Frequency Synthesizers sends, and handles by frequency division, isolates one tunnel inner pps pulse per second signal from described digital signal, and sends described inner pps pulse per second signal to phase discriminator;
Described phase discriminator, be used for receiving the described inner pps pulse per second signal of described target pps pulse per second signal and the transmission of described frequency divider, measure the phase difference of described inner pps pulse per second signal and described target pps pulse per second signal, and after described phase difference carried out filtering and handle by described digital loop filters, be sent to described frequency adjustment word generator;
Described frequency adjustment word generator be used for to receive the described phase difference that described phase discriminator sends, and according to the tuning word of described phase difference generated frequency, and described frequency tuning word is sent to described Direct Digital Frequency Synthesizers;
Described Direct Digital Frequency Synthesizers also be used for to receive the described frequency tuning word that described frequency adjustment word generator sends, and according to the frequency of the described digital signal of described frequency tuning regulation.
4. clock according to claim 3 source is characterized in that,
Described Direct Digital Frequency Synthesizers specifically is used for according to formula
Regulate the frequency of described digital signal, wherein, F
DdsBe the frequency of described digital signal, M is described frequency tuning word, and N is the Clock Multiplier Factor of systematic clock generator, f
XtalFrequency for described reference clock signal.
5. clock according to claim 3 source is characterized in that,
Described processor also is used for the described frequency tuning word of record, when described at least one satellite navigation receiver all is in out-of-lock condition, the described frequency tuning word that records is sent to described clock generator;
Described clock generator, also be used for receiving by described control unit the described frequency tuning word of the record of described processor transmission, and the described frequency tuning word of described record is forwarded to described Direct Digital Frequency Synthesizers by described frequency adjustment word generator, so that described Direct Digital Frequency Synthesizers is according to the frequency of the described digital signal of described frequency tuning regulation.
6. according to each described clock source of claim 1～5, it is characterized in that described clock source also comprises: display screen;
Described at least one satellite navigation receiver also is used for the satellite navigation signals demodulation of described at least one road is generated world UTC unified time temporal information, and sends described UTC temporal information to described processor;
Described processor also be used for to receive described UTC temporal information, select to be in the lock state and the UTC temporal information of the synchronous pps pulse per second signal correspondence of road satellite that priority is higher as object time information, and described object time information is sent to display screen;
Described display screen is used for receiving the described object time information that described processor sends, and shows described temporal information.
7. the method that clock signal is handled is characterized in that, comprising:
The clock source receives at least one road satellite navigation signals;
Described at least one road satellite navigation signals demodulation is generated the synchronous pps pulse per second signal of at least one road satellite;
The synchronous pps pulse per second signal of road satellite that selection is in the lock state and priority is higher is as the target pps pulse per second signal;
Generate reference frequency signal, generate standard-frequency signal with reference to described reference frequency signal and described target pps pulse per second signal.
8. method according to claim 7 is characterized in that, the described reference frequency signal of described reference and described target pps pulse per second signal generate standard-frequency signal, comprising:
Produce system clock frequency according to described reference frequency signal;
Generate digital signal with reference to described target pps pulse per second signal and described system clock frequency;
Described digital signal is changed into analog signal, described analog signal is carried out filtering handle, and the analog signal after the filtering processing is carried out clock distribution export described standard-frequency signal.
9. method according to claim 8 is characterized in that, the described target pps pulse per second signal of described reference is converted to digital signal with described system clock frequency, comprising:
Generate digital signal with reference to described system clock frequency;
Handle by frequency division, from described digital signal, isolate one tunnel inner pps pulse per second signal;
Measure the phase difference of described inner pps pulse per second signal and described target pps pulse per second signal;
According to the tuning word of described phase difference generated frequency, and according to the frequency of the described digital signal of described frequency tuning regulation.
10. method according to claim 9 is characterized in that, and is described according to the tuning word of described phase difference generated frequency, and according to the frequency of the described digital signal of described frequency tuning regulation, comprising:
And according to formula
Regulate the frequency of described digital signal, wherein F
DdsBe the frequency of described digital signal, M is described frequency tuning word, and N is the Clock Multiplier Factor of described systematic clock generator, f
XtalFrequency for described reference clock signal.
11. method according to claim 9 is characterized in that, described method also comprises:
Record described frequency tuning word;
When the synchronous pps pulse per second signal of described at least one road satellite all is in out-of-lock condition, the frequency of the described digital signal of described frequency tuning regulation of reference record.
12. according to each described method of claim 7～11, it is characterized in that described method also comprises:
The satellite navigation signals demodulation of described at least one road is generated world UTC unified time temporal information;
The UTC temporal information of the synchronous pps pulse per second signal correspondence of road satellite that selection is in the lock state and priority is higher is as object time information;
Show described object time information.
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| CN201310203139.1A CN103281076B (en) | 2013-05-28 | 2013-05-28 | A kind of method of clock source and signal transacting thereof |
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| CN201310203139.1A CN103281076B (en) | 2013-05-28 | 2013-05-28 | A kind of method of clock source and signal transacting thereof |
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| CN105680853A (en) * | 2014-12-05 | 2016-06-15 | 吉林克斯公司 | Phase-locked loop with adjustable output distributor |
| CN106877963A (en) * | 2016-12-29 | 2017-06-20 | 河北远东通信系统工程有限公司 | A kind of synchronised clock with learning functionality keeps system and method |
| CN107222210A (en) * | 2017-06-07 | 2017-09-29 | 中国电子科技集团公司第二十四研究所 | It is a kind of that the DDS systems of numeric field clock phase can be configured by SPI |
| CN109814370A (en) * | 2019-01-30 | 2019-05-28 | 深圳国人通信股份有限公司 | A kind of clock system |
| CN111427074A (en) * | 2020-06-10 | 2020-07-17 | 天津七一二通信广播股份有限公司 | GBAS-based high-reliability time system service equipment |
| CN113644910A (en) * | 2021-08-18 | 2021-11-12 | 合肥新港海岸科技有限公司 | Clock generation method and system based on standard frequency signal |
| CN114994727A (en) * | 2022-07-18 | 2022-09-02 | 成都迅翼卫通科技有限公司 | Equipment for realizing high-precision time calibration and satellite positioning |
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| CN106877963A (en) * | 2016-12-29 | 2017-06-20 | 河北远东通信系统工程有限公司 | A kind of synchronised clock with learning functionality keeps system and method |
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| CN111427074A (en) * | 2020-06-10 | 2020-07-17 | 天津七一二通信广播股份有限公司 | GBAS-based high-reliability time system service equipment |
| CN113644910A (en) * | 2021-08-18 | 2021-11-12 | 合肥新港海岸科技有限公司 | Clock generation method and system based on standard frequency signal |
| CN114994727A (en) * | 2022-07-18 | 2022-09-02 | 成都迅翼卫通科技有限公司 | Equipment for realizing high-precision time calibration and satellite positioning |
| CN114994727B (en) * | 2022-07-18 | 2022-12-02 | 成都迅翼卫通科技有限公司 | Equipment for realizing high-precision time calibration and satellite positioning |
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