CN103268267A - NANDFLASH bad sector dynamic label processing method based on blocks - Google Patents
NANDFLASH bad sector dynamic label processing method based on blocks Download PDFInfo
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- CN103268267A CN103268267A CN2013101970994A CN201310197099A CN103268267A CN 103268267 A CN103268267 A CN 103268267A CN 2013101970994 A CN2013101970994 A CN 2013101970994A CN 201310197099 A CN201310197099 A CN 201310197099A CN 103268267 A CN103268267 A CN 103268267A
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Abstract
The invention discloses a NANDFLASH bad sector dynamic label processing method based on blocks. A NANDFLASH chip is detected firstly, and then normal read-write using is carried out. Valid information of each block is labeled with one block as a unit rather than with one page as a unit, so that a system does not need to read labeling value before operation is carried out on each page of flash memory, the system only needs to read labels before a new block is operated, the system does not need to label the state of each page after the operation is finished, and the system only needs to mark the valid state of each block before the block is used or when the block is needed.
Description
Technical field
The present invention relates to the dynamically labeled disposal route of a kind of block-based NANDFLASH bad block.
Background technology
Flash memory FLASH(flash memory) is the present ratio of performance to price and the highest erasable, the nonvolatile memory of reliability.The flash memory cost is low, volume is little, the ability that withstands shocks is strong, memory capacity is big, has been widely used as the external memory parts in embedded system.The main flow flash memory is divided into NOR type and NAND type now, and NAND type flash memory writes with erasing speed faster than NOR type, and unit memory capacity is big, and cost is lower than NOR type, so NAND type flash memory has more advantage than NOR type flash memory on mass data storage.
NANDFLASH be also referred to as invalid block, but invalid block has growth property at random in to the flash disk operation process because can there be bad block in technological reason, and how detecting and manage the flash memory invalid block is one of key issue of data reliable memory.Flash memory invalid block detection at present and Managed Solution have following two kinds, the one, stand-by block is replaced invalid block, when invalid block appears in flash memory, by address mapping table, utilize stand-by block to replace invalid block, can guarantee the continuity of address, but this method can not be guaranteed stand-by block validity, in high reliability is used the secondary stand-by block need be set and shine upon the one-level stand-by block, will waste more storage space, and the implementation process complexity need expend cpu resource.The 2nd, the bypass invalid block, when running into invalid block, directly to next active block operation, this method can guarantee the validity of write-in block.But the state of each page information in this method mark flash memory, system needs spended time to go to read mark value before to each page operations of flash memory like this, and after operation is finished the state of this page or leaf of mark, spend the more time.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, provide a kind of block-based NANDFLASH bad block dynamically labeled disposal route.
Technical solution of the present invention is:
The dynamically labeled disposal route of a kind of block-based NANDFLASH bad block detects the NANDFLASH chip earlier, normally reads and writes use afterwards.
The described step that the NANDFLASH chip is detected is as follows:
(1) initialization bad block information table;
(2) NANDFLASH chip block-by-block is wiped;
(3) make the piece sequence number j=1 of NANDFLASH chip;
(4) read the normal byte area that mode reads all pages of j piece according to page or leaf;
(5) if finding certain page of uncomplete content is 0xFF, then this piece is invalid block, and the bit of this piece correspondence in the invalid block label table is put 0;
(6) piece sequence number j=j+1;
(7) j is judged that if last piece, namely j 〉=n-1 then changeed for (8) step, otherwise changeed for (4) step;
(8) according to the page or leaf writing mode to the piece except the invalid block that the 0th and (5) step mark go out all the normal byte area of page or leaf write 0x00;
(9) make piece sequence number j=1;
(10) read the normal byte area that mode reads all pages that remove the j piece according to page or leaf;
(11) if finding certain page of uncomplete content is 0x00, then this piece is invalid block, and the bit of this piece correspondence in the invalid block label table is put 0;
(12) piece sequence number j=j+1;
(13) j is judged that if last piece, namely j 〉=n-1 then changeed for (14) step, otherwise changeed for (10) step;
(14) the piece block-by-block of chip except the 0th wiped;
(15) storage bad block information table leaves the invalid block label table on the vacant byte area or other nonvolatile memory of preceding k page or leaf of the 1st piece of NANDFLASH chip k=n/8/s.
Described the NANDFLASH chip is is normally read and write to use comprise the steps:
(a) establish total n piece, comprise the p page or leaf in every, normal running pageid page or leaf makes pageid divided by p, discusss to be that q, remainder are rem;
(b) if remainder rem is not equal to 0, then the pageid page or leaf is not the 1st page of q piece, then to the normal read-write of this page or leaf, finishes; If remainder rem equals 0, change (c) step;
(c) from the bad block information table, read the zone bit of q piece correspondence;
(d) if not invalid block, namely zone bit is 1, then to the normal read-write of this page or leaf, finishes;
(e) if invalid block, namely zone bit is 0, and current block is last 1, then finishes, otherwise makes q=q+1, skips this piece, returns step (c).
Described initialization information table is specially:
The bad block information table comprises n bit, represent the 1st validity with the 1st bit, the 2nd bit represents the 2nd validity, by that analogy, during initialization, n bit all put 1, namely effective, 0 representative is invalid, and described n is the piece number of institute's uses NANDFLASH chip, and every page of NANDFLASH chip has the individual normally byte of m and the individual vacant byte of s.
The present invention's beneficial effect compared with prior art is:
(1) be that unit carries out mark and processing to bad block with piece rather than page or leaf, system needn't all go to read mark value before each page or leaf of flash memory is operated, and only need before new piece (block) is operated, to read the mark of this piece correspondence in the invalid block label table, reduce taking of hardware resource, improved the speed that bad block is handled;
(2) set up dynamic bad block information table by the actual detected mode, before chip uses or system think and when needing chip carried out actual detected, set up the bad block information table according to the actual detected result, set up or renewal bad block information table, thus credibility and the real-time of guarantee bad block information table;
(3) the bad block information table is represented the validity of 1 piece with 1bit, conserve storage, and the bad block information table places before the 1st on other nonvolatile memory of some pages vacant byte regions or system (such as certain sector of NorFlash), can ensure reliably, make things convenient for system to the use of NandFlash again;
(4) handle bad block according to the bad block information table with bypass mode, disposal route is simple, reliable, rapid, is fit to embedded system and uses.
Description of drawings
Fig. 1 is the chip detecting method process flow diagram
Fig. 2 is the method flow diagram of normal read-write pageid page or leaf
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is further described in detail.
The method of bypass invalid block among the present invention is the effective information that unit comes each piece of mark with piece rather than with the page or leaf, and system needn't all go to read mark value before each page or leaf of flash memory is operated like this, and only needs to read before new piece is operated mark; Also need not the state of each page of mark after operation is finished, only need before use or need the effective status of each piece of tense marker.The K9K8G08U0M that produces with Samsung is example, and it is relevant with the chip model that the time of bypass invalid block can be saved about 98.4%(efficient).Bad block information table is placed on the 1st preceding some pages vacant byte regions, can fully save user's space.The foundation of bad block information table and renewal can dynamically be carried out at any time, can realize the dynamically effectively management of bad block easily.
Block-based dynamic N ANDFLASH bad block mark disposal route provided by the invention mainly comprises chip detection and two steps of normal read-write use.
Before chip is used, perhaps use after a period of time system to think and in case of necessity entire chip is detected.If the NANDFLASH chip that uses has the n piece, every page has m normal byte and s vacant byte, and then step is:
(1) initialization bad block information table.The bad block information table comprises n bit, represents the 1st validity with the 1st bit, and the 2nd bit represents the 2nd validity, by that analogy.During initialization, n bit all put the 1(1 representative effectively, 0 representative is invalid).
(2) the chip block-by-block is wiped (can not wiping when detecting for the first time);
(3) read the normal byte area that mode reads all pages of each piece except the 0th according to page or leaf, if certain page of uncomplete content is 0xFF, then this piece is invalid block, and the bit of this piece correspondence in the invalid block label table is put 0;
(4) according to the page or leaf writing mode to the piece except the invalid block that the 0th and (3) step mark go out all the normal byte area of page or leaf write full 0x00; Read mode with page or leaf again it is read, if to read uncomplete content be 0x00 to certain page or leaf, then this page place piece also is invalid block, and the bit of this piece correspondence in the invalid block label table is put 0;
(5) the piece block-by-block of chip except the 0th wiped;
(6) the invalid block label table is left on the vacant byte area (k=n/8/s) of preceding k page or leaf of the 0th piece of NANDFLASH chip or other nonvolatile memory in the system (such as certain sector of NorFlash).
After to chip detection, system can normally read and write use.During use, system needn't all go to read mark value before each page or leaf (page) of flash memory is operated, and only need before new piece (block) is operated, to read the mark of this piece correspondence in the invalid block label table, if mark value is 1 then normal running, otherwise directly skip this piece.The embodiment of normal running pageid page or leaf is:
(1) according to page or leaf sequence number pageid(nonnegative integer, since 0) judge that whether this page be the 1st page of certain piece.If comprise the p page or leaf in every, pageid is q divided by p merchant, and remainder is i.If pageid can be divided exactly by p, namely remainder i is 0, and then this page is the 1st page of certain piece.
(2) if waiting to operate page or leaf is not the 1st page of q piece, then to the normal read-write of this page or leaf, end; If the 1st page of waiting to operate page or leaf and be the q piece changeed for (3) step;
(3) from the invalid block label table, read the zone bit of this piece correspondence;
(4) if zone bit is 1, then to the normal read-write of this page or leaf; If zone bit is 0, and current block is last 1 (q is more than or equal to n-1), then withdraws from, otherwise makes q=q+1, skips this piece, changes for (3) step.
Claims (4)
1. the dynamically labeled disposal route of block-based NANDFLASH bad block is characterized in that earlier the NANDFLASH chip being detected, and normally reads and writes use afterwards.
2. the dynamically labeled disposal route of a kind of block-based NANDFLASH bad block according to claim 1, it is characterized in that: the described step that the NANDFLASH chip is detected is as follows:
(1) initialization bad block information table;
(2) NANDFLASH chip block-by-block is wiped;
(3) make the piece sequence number j=1 of NANDFLASH chip;
(4) read the normal byte area that mode reads all pages of j piece according to page or leaf;
(5) if finding certain page of uncomplete content is 0xFF, then this piece is invalid block, and the bit of this piece correspondence in the invalid block label table is put 0;
(6) piece sequence number j=j+1;
(7) j is judged that if last piece, namely j 〉=n-1 then changeed for (8) step, otherwise changeed for (4) step;
(8) according to the page or leaf writing mode to the piece except the invalid block that the 0th and (5) step mark go out all the normal byte area of page or leaf write 0x00;
(9) make piece sequence number j=1;
(10) read the normal byte area that mode reads all pages of j piece according to page or leaf;
(11) if finding certain page of uncomplete content is 0x00, then this piece is invalid block, and the bit of this piece correspondence in the invalid block label table is put 0;
(12) piece sequence number j=j+1;
(13) j is judged that if last piece, namely j 〉=n-1 then changeed for (14) step, otherwise changeed for (10) step;
(14) the piece block-by-block of chip except the 0th wiped;
(15) storage bad block information table leaves the invalid block label table on the vacant byte area or other nonvolatile memory of preceding k page or leaf of the 1st piece of NANDFLASH chip k=n/8/s.
3. the dynamically labeled disposal route of a kind of block-based NANDFLASH bad block according to claim 1 is characterized in that: described that the NANDFLASH chip is is normally read and write the step of use is as follows:
(a) establish total n piece, comprise the p page or leaf in every, normal running pageid page or leaf makes pageid divided by p, discusss to be that q, remainder are rem;
(b) if remainder rem is not equal to 0, then the pageid page or leaf is not the 1st page of q piece, then to the normal read-write of this page or leaf, finishes; If remainder rem equals 0, change step (c);
(c) from the bad block information table, read the zone bit of q piece correspondence;
(d) if not invalid block, namely zone bit is 1, then to the normal read-write of this page or leaf, finishes;
(e) if invalid block, namely zone bit is 0, and current block is last 1, then finishes, otherwise makes q=q+1, skips this piece, changes step (c).
4. the dynamically labeled disposal route of a kind of block-based NANDFLASH bad block according to claim 2, it is characterized in that: described initialization information table concrete grammar is:
The bad block information table comprises n bit, represent the 1st validity with the 1st bit, the 2nd bit represents the 2nd validity, by that analogy, during initialization, n bit all put 1, namely effective, 0 representative is invalid, and described n is the piece number of institute's uses NANDFLASH chip, and every page of NANDFLASH chip has the individual normally byte of m and the individual vacant byte of s.
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106021121A (en) * | 2015-03-30 | 2016-10-12 | 凯为公司 | Packet processing system, method and device to optimize packet buffer space |
CN113110794A (en) * | 2020-01-10 | 2021-07-13 | 株洲中车时代电气股份有限公司 | Data storage method and system for NandFlash |
US11297012B2 (en) | 2015-03-30 | 2022-04-05 | Marvell Asia Pte, Ltd. | Packet processing system, method and device having reduced static power consumption |
CN114627932A (en) * | 2020-12-09 | 2022-06-14 | 南京长峰航天电子科技有限公司 | NAND FLASH storage chip bad area detection management method |
US11824796B2 (en) | 2013-12-30 | 2023-11-21 | Marvell Asia Pte, Ltd. | Protocol independent programmable switch (PIPS) for software defined data center networks |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1577784A (en) * | 2003-07-29 | 2005-02-09 | 华为技术有限公司 | Writing buffer-supporting FLASH internal unit testing metod |
US20060075284A1 (en) * | 2004-09-30 | 2006-04-06 | Skan Peter L | Method for over-the-air firmware update of NAND flash memory based mobile devices |
US20060239075A1 (en) * | 2005-04-26 | 2006-10-26 | Microsoft Corporation | NAND flash memory management |
CN101013602A (en) * | 2006-01-31 | 2007-08-08 | 株式会社东芝 | Semiconductor storage device |
CN101562051A (en) * | 2008-04-18 | 2009-10-21 | 深圳市朗科科技股份有限公司 | Flash memory medium scan method |
CN102541676A (en) * | 2011-12-22 | 2012-07-04 | 福建新大陆通信科技股份有限公司 | Method for detecting and mapping states of NAND FLASH |
-
2013
- 2013-05-24 CN CN2013101970994A patent/CN103268267A/en active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1577784A (en) * | 2003-07-29 | 2005-02-09 | 华为技术有限公司 | Writing buffer-supporting FLASH internal unit testing metod |
US20060075284A1 (en) * | 2004-09-30 | 2006-04-06 | Skan Peter L | Method for over-the-air firmware update of NAND flash memory based mobile devices |
US20060239075A1 (en) * | 2005-04-26 | 2006-10-26 | Microsoft Corporation | NAND flash memory management |
CN101013602A (en) * | 2006-01-31 | 2007-08-08 | 株式会社东芝 | Semiconductor storage device |
CN101562051A (en) * | 2008-04-18 | 2009-10-21 | 深圳市朗科科技股份有限公司 | Flash memory medium scan method |
CN102541676A (en) * | 2011-12-22 | 2012-07-04 | 福建新大陆通信科技股份有限公司 | Method for detecting and mapping states of NAND FLASH |
Non-Patent Citations (2)
Title |
---|
余辉龙、何昕、魏仲慧、王东鹤: "NAND型闪存大容量图像存储器无效块管理", 《微电子学与计算机》, vol. 27, no. 2, 28 February 2010 (2010-02-28), pages 1 - 4 * |
林刚: "NAND Flash坏块管理算法及逻辑层驱动设计", 《中国优秀硕士学位论文全文数据库(信息科技辑)》, 31 January 2010 (2010-01-31), pages 137 - 31 * |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11824796B2 (en) | 2013-12-30 | 2023-11-21 | Marvell Asia Pte, Ltd. | Protocol independent programmable switch (PIPS) for software defined data center networks |
CN106021121A (en) * | 2015-03-30 | 2016-10-12 | 凯为公司 | Packet processing system, method and device to optimize packet buffer space |
CN106021121B (en) * | 2015-03-30 | 2021-10-22 | 马维尔亚洲私人有限公司 | Packet processing system, method and apparatus to optimize packet buffer space |
US11297012B2 (en) | 2015-03-30 | 2022-04-05 | Marvell Asia Pte, Ltd. | Packet processing system, method and device having reduced static power consumption |
US11652760B2 (en) | 2015-03-30 | 2023-05-16 | Marvell Asia Pte., Ltd. | Packet processing system, method and device having reduced static power consumption |
CN113110794A (en) * | 2020-01-10 | 2021-07-13 | 株洲中车时代电气股份有限公司 | Data storage method and system for NandFlash |
CN113110794B (en) * | 2020-01-10 | 2023-09-08 | 株洲中车时代电气股份有限公司 | Data storage method and system for NandFlash |
CN114627932A (en) * | 2020-12-09 | 2022-06-14 | 南京长峰航天电子科技有限公司 | NAND FLASH storage chip bad area detection management method |
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Application publication date: 20130828 |