CN103246582A - FPGA (Field Programmable Gate Array) fault detection method and device - Google Patents
FPGA (Field Programmable Gate Array) fault detection method and device Download PDFInfo
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Abstract
The invention discloses an FPGA (Field Programmable Gate Array) fault detection method which comprises loading a pre-generated FPGA chip detection software; performing fault detection on an FPGA chip through the FPGA chip detection software; obtaining an error detecting result of the FPGA chip through the FPGA chip detection software; and confirming faulted hardware circuits inside the FPGA chip according to the obtained FPGA chip detecting result. The invention also provides an FPGA fault detection device. The FPGA fault detection method and device is capable of detecting the faulted hardware circuits inside the FPGA chip. The FPGA fault detection device is low in cost.
Description
Technical field
The present invention relates to circuit fault-tolerant technique field, particularly a kind of field programmable gate array (FPGA) fault detection method and device.
Background technology
The fpga chip cost is low, has the advantages such as dirigibility of overprogram, is widely used at signal to handle control, fields such as data transmission.In the operative scenario of fpga chip, be subjected to external environment high temperature, electromagnetic environment is abominable, and factor affecting such as chip power supply or interface signal overshoot, along with fpga chip is more and more longer working time, transistor circuit in the fpga chip etc. can be damaged, and then cause register (reg) in the fpga chip, look-up table (lut), random access memory (RAM), multiplier (DSP), phaselocked loop (PLL), serial transceiver (SERDES), signal driver hardware circuit faulty resources such as (BUFFER) makes that fpga chip can't operate as normal.
After the fpga chip internal hardware circuit resource fault, the user can not initiatively perceive, and is only using this fpga chip, when finding that this fpga chip can't operate as normal, could determine the internal hardware circuit resource fault of this fpga chip.And, after finding the fpga chip fault, have only the fpga chip with fault to turn back to manufacturer, by fpga chip is shone X-ray, could determine the hardware circuit resource of fpga chip internal fault, it is higher to detect cost.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of FPGA fault detection method, this method can detect the hardware circuit resource of fpga chip internal fault, and cost is lower.
In order to achieve the above object, the invention provides a kind of FPGA fault detection method, this method comprises:
Load the fpga chip that generates in advance and detect software;
Use described fpga chip to detect software fpga chip is carried out fault detect;
Obtain fpga chip and detect software to the fault detect result of fpga chip, determine the hardware circuit of fault in the fpga chip according to the fpga chip testing result of obtaining.
The present invention also provides a kind of FPGA failure detector, and this device comprises: software loading unit, fault detection unit, fault determining unit;
Described software loading unit is used for loading the fpga chip that generates in advance and detects software;
Described fault detection unit is used for using described fpga chip to detect software fpga chip is carried out fault detect;
Described fault determining unit is used for obtaining fpga chip and detects software to the fault detect result of fpga chip, determines the hardware circuit of fault in the fpga chip according to the fpga chip testing result of obtaining.
By top technical scheme as can be known, among the present invention, by generating fpga chip detection software in advance and being loaded in the fpga chip to be detected, use this fpga chip to detect software the hardware circuit in the fpga chip to be detected is carried out fault detect, thereby can detect the hardware circuit of fpga chip internal fault, and cost is lower.
Description of drawings
Fig. 1 is embodiment of the invention FPGA fault detection method process flow diagram;
Fig. 2 is that the embodiment of the invention is to the fault detect synoptic diagram of DSP;
Fig. 3 is that the embodiment of the invention is to the fault detect synoptic diagram of RAM;
Fig. 4 is that the embodiment of the invention is to the fault detect synoptic diagram of PLL;
Fig. 5 is that the embodiment of the invention is to the fault detect synoptic diagram of BUFFER;
Fig. 6 is that the embodiment of the invention is to the fault detect synoptic diagram of SERDES;
Fig. 7 is that the embodiment of the invention is to the reg of delegation among the FPGA and lut testing process synoptic diagram;
Fig. 8 is the structural representation of embodiment of the invention FPGA failure detector.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with the accompanying drawing embodiment that develops simultaneously, technical scheme of the present invention is elaborated.
Referring to Fig. 1, Fig. 1 is embodiment of the invention FPGA fault detection method process flow diagram, may further comprise the steps:
The fpga chip that step 101, loading generate in advance detects software;
In the embodiment of the invention shown in Figure 1, before step 101, also need first IOBUS interface to FPGA to detect, be specifically as follows: in arbitrary register of FPGA, write preset data by the IOBUS interface earlier, and to the data negate in described arbitrary register, read the data in described arbitrary register again, data and the preset data of reading are compared, if the data of reading are identical with value after the preset data negate, determine that then the IOBUS interface is normal, otherwise, determine the IOBUS interface fault.
In the embodiment of the invention shown in Figure 1, use described fpga chip to detect software described in the step 102 method that fpga chip carries out fault detect be specifically as follows:
FPGA is divided into first area and second area.
Generate input signal at the first area piece in the first area, this input signal is input to each first area piece in the first area, output signal behind all reg so that this input signal is flowed through in this first area piece and the lut is judged reg or the lut that whether has fault in this first area piece according to input signal and the output signal of first area piece; Generate input signal at other hardware circuit except reg and lut in the second area, this input signal is input to described other hardware circuit, judges whether fault of described other hardware circuit according to the input signal of described other hardware circuit and output signal.
Generate input signal at the first area piece in the second area, this input signal is input to each first area piece in the second area, output signal behind all reg so that this input signal is flowed through in this first area piece and the lut is judged reg or the lut that whether has fault in this first area piece according to input signal and the output signal of first area piece; Generate input signal at described other hardware circuit in the first area, this input signal is input to other hardware circuit described in the first area, judges whether fault of described other hardware circuit according to the input signal of described other hardware circuit and output signal.
In fact, use described fpga chip to detect software described in the step 102 and also can adopt other several different methods to the method that fpga chip carries out fault detect, for example, FPGA is divided into zone more than two or two, successively the hardware circuit in each zone is carried out fault detect, and the final fault detect that realizes all hardware circuit in the fpga chip; Perhaps, fault detect is carried out to the hardware circuit in the zone of selecting earlier in one or more zone after selecting to divide, and again the hardware circuit in the remaining areas is carried out fault detect etc.
Described other hardware circuit can comprise multiplier DSP.When the reg in each the first area piece in the first area and lut were tested, each DSP in the second area carried out fault detect simultaneously.When the reg in each the first area piece in the second area and lut were tested, each DSP in the first area carried out fault detect simultaneously.
Specifically to the detection method of each DSP referring to the embodiment of the invention shown in Figure 2 fault detect synoptic diagram to DSP, with two data (first data as shown in Figure 2 and second data predefined or that generate at random, also be the input signal of DSP) be input to DSP to be tested, the products that compare output data (also being output signal) and two the input data of DSP, if it is identical, illustrate that then this DSP is normal, if it is inequality, this DSP fault then is described, can records the positional information of this fault DSP.Here, the quantity of DSP and position are relevant with the model of concrete FPGA among the FPGA, can determine the position of each DSP wherein based on the model of detected FPGA.Can be in for detection of the rear end unbound document of FPGA DSP be tied to (positional information that also is about to each DSP is written in the unbound document of rear end) on the position to be tested, the positional information of each DSP that records in can be based on the rear end unbound document when detecting detects.Owing to be to detect at each DSP, if detect the DSP fault, the accurate position of the DSP of fault location then.
Described other hardware circuit can also comprise random access memory ram.When the reg in each the first area piece in the first area and lut were tested, each RAM in the second area carried out fault detect simultaneously.When the reg in each the first area piece in the second area and lut were tested, each RAM in the first area carried out fault detect simultaneously.
Wherein, at the detection method of each RAM referring to the embodiment of the invention shown in Figure 3 fault detect synoptic diagram to RAM, generate or preestablish data (shown in the 3rd data among Fig. 3) at first at random, these data can be PN18 data, order according to address increment is written to RAM to be tested with these data then, after these data being write full each RAM, again according to order sense data from this RAM of address increment, if there is arbitrary address, the data that are written to this address are inconsistent with the data of reading from this address, can determine that then this RAM in place, described arbitrary address fault, can record described arbitrary address.Also can accurately navigate to the abort situation of RAM to the detection of RAM.Here, the quantity of RAM and position are relevant with the model of concrete FPGA among the FPGA, can determine the position of each RAM wherein based on the model of detected FPGA, can be in for detection of the rear end unbound document of FPGA RAM be tied to (positional information that also is about to each RAM is written in the unbound document of rear end) on the position to be tested, the positional information of each RAM that records in can be based on the rear end unbound document when detecting detects.
Described other hardware circuit can also comprise phase-locked loop pll.When the reg in each the first area piece in the first area and lut were tested, each PLL in the second area carried out fault detect simultaneously.When the reg in each the first area piece in the second area and lut were tested, each PLL in the first area carried out fault detect simultaneously.
Wherein, at the detection method of each PLL referring to the embodiment of the invention shown in Figure 4 fault detect synoptic diagram to PLL, the pin input clock of this fpga chip is input to PLL to be tested as the reference clock of PLL, this PLL divides the clock that occurs frequently, the clock that utilizes the PLL branch to occur frequently drives a counter 1, also utilize the pin input clock of fpga chip to drive another counter 2 simultaneously, the value that compares two counters then, if it is identical, determine that then this PLL does not break down, if inequality, then determine this PLL fault, can record the Position Number of this PLL.Here, the quantity of PLL and position are relevant with the model of concrete FPGA among the FPGA, can determine the position of each PLL wherein based on the model of detected FPGA, can be in for detection of the rear end unbound document of FPGA PLL be tied to (positional information that also is about to each PLL is written in the unbound document of rear end) on the position to be tested, the positional information of each PLL that records in can be based on the rear end unbound document when detecting detects.Owing to be to detect at each PLL, again because the stationkeeping of each PLL, if detect the PLL fault, the accurate position of the PLL of fault location then.
Described other hardware circuit can also comprise BUFFER.When the reg in each the first area piece in the first area and lut were tested, each BUFFER in the second area carried out fault detect simultaneously.When the reg in each the first area piece in the second area and lut were tested, each BUFFER in the first area carried out fault detect simultaneously.
Wherein, at the detection method of each BUFFER referring to the embodiment of the invention shown in Figure 5 fault detect synoptic diagram to BUFFER, the pin input clock of fpga chip is input to BUFFER to be tested as input signal, utilize the output clock of this BUFFER to drive a counter 3, utilize the pin input clock of this fpga chip to drive another counter 4 simultaneously, the value that compares two counters, if it is identical, determine that then this BUFFER does not break down, if it is inequality, then determine this BUFFER fault, record the Position Number of this BUFFER.Here, the quantity of BUFFER and position are relevant with the model of concrete FPGA among the FPGA, can determine the position of each BUFFER wherein based on the model of detected FPGA, can be in for detection of the rear end unbound document of FPGA BUFFER be tied to (positional information that also is about to each BUFFER is written in the unbound document of rear end) on the position to be tested, the positional information of each BUFFER that records in can be based on the rear end unbound document when detecting detects.Owing to be to detect at each BUFFER, again because the stationkeeping of each BUFFER, if detect the BUFFER fault, the accurate position of the BUFFER of fault location then.
Described other hardware circuit can also comprise SERDES.When the reg in each the first area piece in the first area and lut were tested, each SERDES in the second area carried out fault detect simultaneously.When the reg in each the first area piece in the second area and lut were tested, each SERDES in the first area carried out fault detect simultaneously.
Wherein, at the detection method of each SERDES referring to the embodiment of the invention shown in Figure 6 fault detect synoptic diagram to SERDES, in advance SERDES to be tested is configured to loopback mode, and generate or preestablish data (shown in the 4th data among Fig. 6) at random, these data can be the PN18 data, these data are input to the SERDES that configures the SERDES loopback mode, the data of this SERDES loopback output are compared with the data of importing this SERDES, if it is identical, determine that then this SERDES does not break down, if inequality, then determine this SERDES fault, record the Position Number of this SERDES.Here, the quantity of SERDES and position are relevant with the model of concrete FPGA among the FPGA, can determine the position of each SERDES wherein based on the model of detected FPGA, in reality realizes, can be in for detection of the rear end unbound document of FPGA SERDES be tied to (positional information that also is about to each SERDES is written in the unbound document of rear end) on the position to be tested, the positional information of each SERDES that records in can be based on the rear end unbound document when detecting detects.Because the stationkeeping of each SERDES, if detect the BUFFER fault, the accurate position of the BUFFER of fault location then.
The described method that FPGA is divided into first area and second area is specifically as follows: FPGA is divided into two zones up and down, correspond respectively to first area and second area, wherein, the first area has comprised that the 1st row of FPGA is capable to x, second area has comprised the capable last column to FPGA of remaining x+1, wherein x is greater than 0, and less than a natural number of total line number of FPGA.Two zones about also FPGA can being divided into, correspond respectively to first area and second area, wherein, the first area has comprised that the 1st row of FPGA are listed as to y, second area has comprised that remaining y+1 is listed as last row of FPGA, wherein y is greater than 0, and less than a natural number of total columns of FPGA.Here, described row and column all is that basic programmable logic cells with FPGA is unit, and delegation refers to the basic programmable logic cells of the delegation among the FPGA, and row refer to the basic programmable logic cells of row.Described basic programmable logic cells is made up of reg and lut, and according to the difference of FPGA model, the reg in the basic programmable logic cells and the composition of lut are also inequality, and relatively the configuration of classical basic programmable unit is that a register adds a look-up table.
Wherein, when FPGA being divided into up and down two when regional, described first area piece refers to the delegation of FPGA; About FPGA is divided into two when regional, described first area piece refers to the row of FPGA.
As seen, after FPGA is divided into first area and second area, when the reg in first area and the second area and lut are carried out fault detect, be merely able to detect the row or column that reg or lut fault take place, but the concrete abort situation in the row or column that can not specifically locate, therefore, in the present embodiment, also need further FPGA to be divided into the 3rd zone and the 4th zone, and reg and the lut in the second area piece in the 3rd zone and the 4th zone carried out fault detect, specifically comprise:
Generate input signal at the second area piece in the 3rd zone, this input signal is input to each second area piece in the 3rd zone, output signal behind all reg so that this input signal is flowed through in this second area piece and the lut is judged reg or the lut that whether has fault in this second area piece according to this input signal and output signal;
Generate input signal at the second area piece in the 4th zone, this input signal is input to each second area piece in the 4th zone, output signal behind all reg so that this input signal is flowed through in this second area piece and the lut is judged reg or the lut that whether has fault in this second area piece according to this input signal and output signal.
Here, the 3rd zone and four-range are divided and should be cooperatively interacted with the division of first area and second area, for example, when first area and second area when two zones are divided up and down, the 3rd zone and the 4th zone should according to about two zone divisions, correspondingly, the first area piece refers to the delegation among the FPGA, and the second area piece refers to the row among the FPGA; When first area and second area when two zones are divided up and down, the 3rd zone and the 4th zone should according to about two zone divisions, correspondingly, the first area piece refers to the row among the FPGA, the second area piece refers to the delegation among the FPGA.
In the present embodiment, identical to the fault detection method of each row and the reg of each row and lut, be that example describes with the method that the reg of delegation and lut are detected below.
Referring to Fig. 7, Fig. 7 is that the embodiment of the invention is to the reg of delegation among the FPGA and lut testing process synoptic diagram, as shown in Figure 7, this row reg and lut are together in series, form test line, then, to this row input comprise input predefined or generate at random comprise many bit serial data stream of 0 and 1, this data stream is at reg and the lut superior displacement of this row, and final from afterbody reg or lut output stream from this row, just can determine according to the input and output data stream of this row whether this row exists reg or the lut of fault then.
Here, for a set fpga chip, the stationkeeping of the basic programmable logic cells of each row or each row, the position of reg and lut is also fixing in the basic programmable logic cells, therefore, can be according to the positional information of reg and lut in this row or column, in for detection of the rear end unbound document of FPGA with this row or column in reg and lut be tied on the position to be tested (also be about to the positional information of reg and lut is written in the unbound document of rear end in this row or column), when detecting based on reg and lut the positional information in every row or every row, utilize methods of other series connection reg and lut in the method for series connection reg that fpga chip manufacturer provides and lut or the prior art connect all reg and lut in this row or column, just can carry out fault test by input traffic then.
According to determining the reg of each row and the method for testing of lut:
When the first area piece refers to that the delegation of FPGA, second area piece refer to the row of FPGA, correspondingly,
Input signal is input to each first area piece in first area or the second area, output signal behind all reg so that this input signal is flowed through in this first area piece and the lut, judge that according to this input signal and output signal the reg that whether has fault in this first area piece or the method for lut are specifically as follows: reg and lut in each row in first area or the second area are contacted, input comprises many bit serial data stream of 0 and 1, this data stream is at reg and the lut superior displacement of this row, whether judgement is identical with the data stream of input from the data stream of the afterbody reg of this row or lut output, if it is identical, the reg and the lut that then determine this row are normal, otherwise, determine that there be reg or the lut of fault in this row, record the row number of this fault;
With input signal be input to the 3rd the zone or the 4th zone in each second area piece, output signal behind all reg so that this input signal is flowed through in this second area piece and the lut, judge that according to this input signal and output signal the reg that whether has fault in this second area piece or the method for lut are specifically as follows: reg and lut in each row in the 3rd zone or the 4th zone are contacted, input comprises many bit serial data stream of 0 and 1, this data stream is at reg and the lut superior displacement of these row, whether judgement is identical with the data stream of input from the data stream of the afterbody reg output of these row, if it is identical, the reg and the lut that then determine these row are normal, otherwise, determine that there be reg or the lut of fault in these row, record the row number of this fault.
When the first area piece refers to the row of FPGA, when the second area piece refers to the delegation of FPGA, correspondingly,
Input signal is input to each first area piece in first area or the second area, output signal behind all reg so that this input signal is flowed through in this first area piece and the lut, judge that according to this input signal and output signal the reg that whether has fault in this first area piece or the method for lut are specifically as follows: reg and lut in each row in first area or the second area are contacted, input comprises many bit serial data stream of 0 and 1, this data stream is at reg and the lut superior displacement of these row, whether judgement is identical with the data stream of input from the data stream of the afterbody reg of these row or lut output, if it is identical, the reg and the lut that then determine these row are normal, otherwise, determine that there be reg or the lut of fault in these row, record the row number of this fault;
With input signal be input to the 3rd the zone or the 4th zone in each second area piece, output signal behind all reg so that this input signal is flowed through in this second area piece and the lut, judge that according to this input signal and output signal the reg that whether has fault in this second area piece or the method for lut are specifically as follows: reg and lut in each row in the 3rd zone or the 4th zone are contacted, input comprises many bit serial data stream of 0 and 1, this data stream is at reg and the lut superior displacement of this row, whether judgement is identical with the data stream of input from the data stream of the afterbody reg of this row or lut output, if it is identical, the reg and the lut that then determine this row are normal, otherwise, determine that there be reg or the lut of fault in this row, record the row number of this fault.
By the fault detect to the first area piece in first area and the second area, and to the fault detect of second area piece in the 3rd zone and the 4th zone, the row and column of reg or lut fault can be determined to exist, and then the particular location of reg or lut fault can be accurately determined.
More than method embodiment of the present invention is had been described in detail, the present invention also provides a kind of FPGA failure detector.
Referring to Fig. 8, Fig. 8 is the structural representation of embodiment of the invention FPGA failure detector, and this device comprises: software loading unit 810, fault detection unit 820, fault determining unit 830; Wherein,
Fault determining unit 830 is used for obtaining fpga chip and detects software to the fault detect result of fpga chip, determines the hardware circuit of fault in the fpga chip according to the fpga chip testing result of obtaining.
Described fault detection unit 820 comprises: regional division unit 821, signal input unit 822, signal comparing unit 823; Wherein,
Described other hardware circuit comprises multiplier DSP;
Described signal input unit 822 comprises first data and second data at the input signal that DSP generates;
Described signal input unit 822 is used for each DSP with described first data and second data input first area or second area;
Described signal comparing unit 823, be used for after signal input unit 822 is input to each DSP with described first data and second data, the data of this DSP output and the product of described first data and second data are compared, if it is identical, determine that then this DSP does not break down, if inequality, then determine this DSP fault, record the Position Number of this DSP.
Described other hardware circuit comprises random access memory ram;
Described signal input unit 822 is the 3rd data at the input signal that RAM generates;
Described signal input unit 822 is further used for according to the order of address increment the 3rd data being write full each RAM;
Described signal comparing unit 823, be used for after signal input unit 822 is write the 3rd data according to the order of address increment full each RAM, order sense data from this RAM according to address increment, if there is arbitrary address, the data that are written to this address are inconsistent with the data of reading from this address, then determine this RAM in place, described arbitrary address fault, and record described arbitrary address.
Described other hardware circuit comprises phase-locked loop pll;
Described signal input unit 822 is the pin input clock of this fpga chip at the input signal that PLL generates;
Described signal input unit 822 is further used for the pin input clock of this fpga chip is input to this PLL as the reference clock of each PLL, and the clock that utilizes this PLL to divide to occur frequently drives a counter;
Described signal comparing unit 823, be used for after signal input unit 822 is input to this PLL with the pin input clock of this fpga chip as the reference clock of each PLL, utilize the pin input clock of this fpga chip to drive another counter, the value of the counter that the clock-driven counter that relatively utilizes PLL to divide to occur frequently and the pin input clock that utilizes this fpga chip drive, if it is identical, determine that then this PLL does not break down, if it is inequality, then determine this PLL fault, record the Position Number of this PLL.
Described other hardware circuit comprises BUFFER;
Described signal input unit 822 is the pin input clock of this fpga chip at the input signal that BUFFER generates;
Described signal input unit 822 is further used for the pin input clock of this fpga chip is input to each BUFFER, utilizes the output clock of this BUFFER to drive a counter;
Described signal comparing unit 823, be used for after signal input unit 822 is input to each BUFFER with the pin input clock of this fpga chip, utilize the pin input clock of this fpga chip to drive another counter, relatively utilize the value of the clock-driven counter of output with the counter of the pin input clock driving that utilizes this fpga chip of BUFFER, if it is identical, determine that then this BUFFER does not break down, if it is inequality, then determine this BUFFER fault, record the Position Number of this BUFFER.
Described other hardware circuit comprises SERDES;
Described signal input unit 822 is the 4th data at the input signal that SERDES generates;
Described signal input unit 822 is further used for described the 4th data are input to each SERDES that configures the SERDES loopback mode;
Described signal comparing unit 823, be used for after signal input unit 822 is input to each SERDES that configures the SERDES loopback mode with described the 4th data, data and described the 4th data of this SERDES loopback output are compared, if it is identical, determine that then this SERDES does not break down, if inequality, then determine this SERDES fault, record the Position Number of this SERDES.
Described regional division unit is further used for FPGA is divided into the 3rd zone and the 4th zone;
Described signal input unit 822, be further used for generating input signal at the second area piece in the 3rd zone, this input signal is input to each second area piece in the 3rd zone, output signal behind all reg so that this input signal is flowed through in this second area piece and the lut; Be further used for generating input signal at the second area piece in the 4th zone, this input signal is input to each second area piece in the 4th zone, output signal behind all reg so that this input signal is flowed through in this second area piece and the lut;
Described signal comparing unit 823, the output signal that is further used for being input to according to signal input unit 822 input signal of each second area piece in the 3rd zone and this second area piece is judged reg or the lut that whether has fault in this second area piece; The output signal that is further used for being input to according to signal input unit 822 input signal of each second area piece in the 4th zone and this second area piece is judged reg or the lut that whether has fault in this second area piece.
Described first area piece is the delegation among the FPGA; Described second area piece is the row among the FPGA;
Described first area is that first row of FPGA is capable to x, and described second area is that the x+1 of FPGA is capable of last column, and wherein x is greater than 0, and less than a natural number of total line number of FPGA;
Described the 3rd zone is that first row of FPGA are listed as to y, capable last row to FPGA of the y+1 that described the 4th zone is FPGA; Wherein y is greater than 0, and less than a natural number of total columns of FPGA;
Described signal input unit 822 is at each the first area piece that input signal is input in first area or the second area, behind all reg so that this input signal is flowed through in this first area piece and the lut during output signal, be used for: reg and lut in each row of first area or second area are contacted, input comprises many bit serial data stream of 0 and 1, so that this data stream is at reg and the lut superior displacement of this row, and at afterbody reg or the lut output stream of this row; Each second area piece in input signal being input to the 3rd zone or the 4th zone, behind all reg so that this input signal is flowed through in this second area piece and the lut during output signal, be used for: reg and lut in each row in the 3rd zone or the 4th zone are contacted, input comprises many bit serial data stream of 0 and 1, so that this data stream is at reg and the lut superior displacement of these row, and at afterbody reg or the lut output stream of these row;
When described signal comparing unit 823 is judged the reg that whether there is fault in this first area piece or lut in the output signal of the input signal that is input to each first area piece in first area or the second area according to signal input unit 822 and this first area piece, be used for: judge whether the data stream of exporting from afterbody reg or the lut of each row is identical with the data stream of this row of input, if it is identical, the reg and the lut that then determine this row are normal, otherwise, determine that there be reg or the lut of fault in this row, record the row number of this fault; When the output signal of the input signal of each second area piece and this second area piece is judged the reg that whether there is fault in this first area piece or lut in be input to the 3rd zone or the 4th zone according to signal input unit 822, be used for: judge whether the data stream of exporting from afterbody reg or the lut of each row is identical with the data stream of these row of input, if it is identical, the reg and the lut that then determine these row are normal, otherwise, determine that there be reg or the lut of fault in these row, record the row number of this fault.
Described fault detection unit 820 loads before the fpga chip detection software that generates in advance at software loading unit 810, be further used for: in arbitrary register of FPGA, write preset data by the IOBUS interface earlier, and to the data negate in described arbitrary register, read the data in described arbitrary register again, data and the preset data of reading are compared, if the data of reading are identical with value after the preset data negate, determine that then the IOBUS interface is normal, otherwise, determine the IOBUS interface fault.
The above only is preferred embodiment of the present invention, and is in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, is equal to replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (20)
1. programmable gate array FPGA fault detection method is characterized in that this method comprises:
Load the fpga chip that generates in advance and detect software;
Use described fpga chip to detect software fpga chip is carried out fault detect;
Obtain fpga chip and detect software to the fault detect result of fpga chip, determine the hardware circuit of fault in the fpga chip according to the fpga chip testing result of obtaining.
2. FPGA fault detection method according to claim 1 is characterized in that,
Using described fpga chip detection software that fpga chip is carried out fault detect comprises:
FPGA is divided into first area and second area;
Generate input signal at the first area piece in the first area, this input signal is input to each first area piece in the first area, output signal behind all reg so that this input signal is flowed through in this first area piece and the lut is judged reg or the lut that whether has fault in this first area piece according to input signal and the output signal of first area piece; Generate input signal at other hardware circuit except reg and lut in the second area, this input signal is input to described other hardware circuit, judges whether fault of described other hardware circuit according to the input signal of described other hardware circuit and output signal;
Generate input signal at the first area piece in the second area, this input signal is input to each first area piece in the second area, output signal behind all reg so that this input signal is flowed through in this first area piece and the lut is judged reg or the lut that whether has fault in this first area piece according to input signal and the output signal of first area piece; Generate input signal at other hardware circuit except reg and lut in the first area, this input signal is input to other hardware circuit described in the first area, judges whether fault of described other hardware circuit according to the input signal of described other hardware circuit and output signal.
3. FPGA fault detection method according to claim 2 is characterized in that, described other hardware circuit comprises multiplier DSP;
The input signal that generates at DSP comprises first data and second data;
This input signal is input to other hardware circuit described in first area or the second area, judges according to input signal and the output signal of described other hardware circuit whether fault comprises described other hardware circuit:
With each DSP in described first data and second data input first area or the second area, compare with the data of this DSP output and the product of described first data and second data, if it is identical, determine that then this DSP does not break down, if it is inequality, then determine this DSP fault, record the Position Number of this DSP.
4. FPGA fault detection method according to claim 2 is characterized in that, described other hardware circuit comprises random access memory ram;
The input signal that generates at RAM is the 3rd data;
Order according to address increment is written to each RAM with the 3rd data, after the 3rd data being write full each RAM, order sense data from this RAM according to address increment, if there is arbitrary address, the data that are written to this address are inconsistent with the data of reading from this address, then determine this RAM in place, described arbitrary address fault, and record described arbitrary address.
5. FPGA fault detection method according to claim 2 is characterized in that, described other hardware circuit comprises phase-locked loop pll;
The input signal that generates at PLL is the pin input clock of this fpga chip;
The pin input clock of this FPGA is input to this PLL as the reference clock of each PLL, this PLL divides the clock that occurs frequently, the clock that utilizes the PLL branch to occur frequently drives a counter, utilize the pin input clock of this fpga chip to drive another counter simultaneously, compare the value of two counters, if identical, determine that then this PLL does not break down, if inequality, then determine this PLL fault, record the Position Number of this PLL.
6. FPGA fault detection method according to claim 2 is characterized in that, described other hardware circuit comprises signal driver BUFFER;
The input signal that generates at BUFFER is the pin input clock of this fpga chip;
The pin input clock of this FPGA is input to each BUFFER, utilize the output clock of this BUFFER to drive a counter, utilize the pin input clock of this fpga chip to drive another counter simultaneously, the value that compares two counters, if identical, determine that then this BUFFER does not break down, if inequality, then determine this BUFFER fault, record the Position Number of this BUFFER.
7. FPGA fault detection method according to claim 2 is characterized in that, described other hardware circuit comprises serial transceiver SERDES;
The input signal that generates at SERDES is the 4th data;
Described the 4th data are input to each SERDES that configures the SERDES loopback mode, data and described the 4th data of this SERDES loopback output are compared, if it is identical, determine that then this SERDES does not break down, if it is inequality, then determine this SERDES fault, record the Position Number of this SERDES.
8. FPGA fault detection method according to claim 2 is characterized in that, this method further comprises:
FPGA is divided into the 3rd zone and the 4th zone;
Generate input signal at the second area piece in the 3rd zone, this input signal is input to each second area piece in the 3rd zone, output signal behind all reg so that this input signal is flowed through in this second area piece and the lut is judged reg or the lut that whether has fault in this second area piece according to input signal and the output signal of second area piece;
Generate input signal at the second area piece in the 4th zone, this input signal is input to each second area piece in the 4th zone, output signal behind all reg so that input signal is flowed through in this second area piece and the lut is judged reg or the lut that whether has fault in this second area piece according to input signal and the output signal of second area piece.
9. FPGA fault detection method according to claim 8 is characterized in that,
Described first area piece is the delegation among the FPGA; Described second area piece is the row among the FPGA;
Described first area is that first row of FPGA is capable to x, and described second area is that the x+1 of FPGA is capable of last column, and wherein x is greater than 0, and less than a natural number of total line number of FPGA;
Described the 3rd zone is that first row of FPGA are listed as to y, capable last row to FPGA of the y+1 that described the 4th zone is FPGA; Wherein y is greater than 0, and less than a natural number of total columns of FPGA;
Input signal is input to each first area piece in first area or the second area, output signal behind all reg so that this input signal is flowed through in this first area piece and the lut, judge that according to the input signal of this first area piece and output signal the reg that whether has fault in this first area piece or the method for lut are: reg and lut in each row in first area or the second area are contacted, input comprises many bit serial data stream of 0 and 1, this data stream is at reg and the lut superior displacement of this row, whether judgement is identical with the data stream of input from the data stream of the afterbody reg of this row or lut output, if it is identical, the reg and the lut that then determine this row are normal, otherwise, determine that there be reg or the lut of fault in this row, record the row number of this fault;
With input signal be input to the 3rd the zone or the 4th zone in each second area piece, output signal behind all reg so that this input signal is flowed through in this second area piece and the lut, judge that according to the input signal of this this first area piece and output signal the reg that whether has fault in this second area piece or the method for lut are: reg and lut in each row in the 3rd zone or the 4th zone are contacted, input comprises many bit serial data stream of 0 and 1, this data stream is at reg and the lut superior displacement of these row, whether judgement is identical with the data stream of input from the data stream of the afterbody reg of these row or lut output, if it is identical, the reg and the lut that then determine these row are normal, otherwise, determine that there be reg or the lut of fault in these row, record the row number of this fault.
10. FPGA fault detection method according to claim 1 is characterized in that,
Loading the fpga chip that generates in advance detects before the software, further comprise: the IOBUS interface to FPGA carries out fault detect, be specially: in arbitrary register of FPGA, write preset data by the IOBUS interface earlier, and to the data negate in described arbitrary register, read the data in described arbitrary register again, data and the preset data of reading are compared, if the data of reading are identical with value after the preset data negate, determine that then the IOBUS interface is normal, otherwise, determine the IOBUS interface fault.
11. a programmable gate array FPGA failure detector is characterized in that this device comprises: software loading unit, fault detection unit, fault determining unit;
Described software loading unit is used for loading the fpga chip that generates in advance and detects software;
Described fault detection unit is used for using described fpga chip to detect software fpga chip is carried out fault detect;
Described fault determining unit is used for obtaining fpga chip and detects software to the fault detect result of fpga chip, determines the hardware circuit of fault in the fpga chip according to the fpga chip testing result of obtaining.
12. FPGA failure detector according to claim 11 is characterized in that, described fault detection unit comprises:
The zone division unit is used for FPGA is divided into first area and second area;
Signal input unit is used for generating input signal at the first area piece of first area, and this input signal is input to each first area piece in the first area, output signal behind all reg so that this input signal is flowed through in this first area piece and the lut; Be used for generating input signal at second area other hardware circuit except reg and lut, this input signal be input to other hardware circuit described in the second area, so that described other hardware circuit output signal; Be used for generating input signal at the first area piece of second area, this input signal is input to each first area piece in the second area, output signal behind all reg so that this input signal is flowed through in this first area piece and the lut; Be used for generating input signal at described other hardware circuit of first area, this input signal be input to described other hardware circuit in the first area, so that described other hardware circuit output signal;
The signal comparing unit is judged reg or the lut that whether has fault in this first area piece for the input signal that is input to each first area piece of first area according to signal input unit and the output signal of this first area piece; Be used for judging described other hardware circuit fault whether in the second area according to the output signal that signal input unit is input to the input signal of described other hardware circuit of second area and described other hardware in the second area; Judge reg or the lut that whether has fault in this first area piece for the input signal that is input to each first area piece of second area according to signal input unit and the output signal of this first area piece; Be used for judging described other hardware circuit fault whether in the first area according to the output signal that signal input unit is input to the input signal of described other hardware circuit of first area and described other hardware in the first area.
13. FPGA failure detector according to claim 12 is characterized in that, described other hardware circuit comprises multiplier DSP;
Described signal input unit comprises first data and second data at the input signal that DSP generates;
Described signal input unit is used for each DSP with described first data and second data input first area or second area;
Described signal comparing unit, be used for after signal input unit is input to each DSP with described first data and second data, the data of this DSP output and the product of described first data and second data are compared, if it is identical, determine that then this DSP does not break down, if inequality, then determine this DSP fault, record the Position Number of this DSP.
14. FPGA failure detector according to claim 12 is characterized in that, described other hardware circuit comprises random access memory ram;
Described signal input unit is the 3rd data at the input signal that RAM generates;
Described signal input unit is further used for according to the order of address increment the 3rd data being write full each RAM;
Described signal comparing unit, be used for after signal input unit is write the 3rd data according to the order of address increment full each RAM, order sense data from this RAM according to address increment, if there is arbitrary address, the data that are written to this address are inconsistent with the data of reading from this address, then determine this RAM in place, described arbitrary address fault, and record described arbitrary address.
15. FPGA fault detection method according to claim 12 is characterized in that, described other hardware circuit comprises phase-locked loop pll;
Described signal input unit is the pin input clock of this FPGA at the input signal that PLL generates;
Described signal input unit is further used for the pin input clock of this fpga chip is input to this PLL as the reference clock of each PLL, and the clock that utilizes this PLL to divide to occur frequently drives a counter;
Described signal comparing unit, be used for after signal input unit is input to this PLL with the pin input clock of this fpga chip as the reference clock of each PLL, utilize the pin input clock of this fpga chip to drive another counter, the value of the counter that the clock-driven counter that relatively utilizes PLL to divide to occur frequently and the pin input clock that utilizes this fpga chip drive, if it is identical, determine that then this PLL does not break down, if it is inequality, then determine this PLL fault, record the Position Number of this PLL.
16. FPGA failure detector according to claim 12 is characterized in that, described other hardware circuit comprises signal driver BUFFER;
Described signal input unit is the pin input clock of this FPGA at the input signal that BUFFER generates;
Described signal input unit is further used for the pin input clock of this fpga chip is input to each BUFFER, utilizes the output clock of this BUFFER to drive a counter;
Described signal comparing unit, be used for after signal input unit is input to each BUFFER with the pin input clock of this fpga chip, utilize the pin input clock of this fpga chip to drive another counter, relatively utilize the value of the clock-driven counter of output with the counter of the pin input clock driving that utilizes this fpga chip of BUFFER, if identical, determine that then this BUFFER does not break down, if inequality, then determine this BUFFER fault, record the Position Number of this BUFFER.
17. FPGA failure detector according to claim 12 is characterized in that, described other hardware circuit comprises serial transceiver SERDES;
Described signal input unit is the 4th data at the input signal that SERDES generates;
Described signal input unit is further used for described the 4th data are input to each SERDES that configures the SERDES loopback mode;
Described signal comparing unit, be used for after signal input unit is input to each SERDES that configures the SERDES loopback mode with described the 4th data, data and described the 4th data of this SERDES loopback output are compared, if it is identical, determine that then this SERDES does not break down, if inequality, then determine this SERDES fault, record the Position Number of this SERDES.
18. FPGA failure detector according to claim 12 is characterized in that,
Described regional division unit is further used for FPGA is divided into the 3rd zone and the 4th zone;
Described signal input unit, be further used for generating input signal at the second area piece in the 3rd zone, this input signal is input to each second area piece in the 3rd zone, output signal behind all reg so that this input signal is flowed through in this second area piece and the lut; Be further used for generating input signal at the second area piece in the 4th zone, this input signal is input to each second area piece in the 4th zone, output signal behind all reg so that this input signal is flowed through in this second area piece and the lut;
Described signal comparing unit, the output signal that is further used for being input to according to signal input unit the input signal of each second area piece in the 3rd zone and this second area piece is judged reg or the lut that whether has fault in this second area piece; The output signal that is further used for being input to according to signal input unit the input signal of each second area piece in the 4th zone and this second area piece is judged reg or the lut that whether has fault in this second area piece.
19. FPGA failure detector according to claim 18 is characterized in that,
Described first area piece is the delegation among the FPGA; Described second area piece is the row among the FPGA;
Described first area is that first row of FPGA is capable to x, and described second area is that the x+1 of FPGA is capable of last column, and wherein x is greater than 0, and less than a natural number of total line number of FPGA;
Described the 3rd zone is that first row of FPGA are listed as to y, capable last row to FPGA of the y+1 that described the 4th zone is FPGA; Wherein y is greater than 0, and less than a natural number of total columns of FPGA;
Described signal input unit is at each the first area piece that input signal is input in first area or the second area, behind all reg so that this input signal is flowed through in this first area piece and the lut during output signal, be used for: reg and lut in each row of first area or second area are contacted, input comprises many bit serial data stream of 0 and 1, so that this data stream is at reg and the lut superior displacement of this row, and at afterbody reg or the lut output stream of this row; Each second area piece in input signal being input to the 3rd zone or the 4th zone, behind all reg so that this input signal is flowed through in this second area piece and the lut during output signal, be used for: reg and lut in each row in the 3rd zone or the 4th zone are contacted, input comprises many bit serial data stream of 0 and 1, so that this data stream is at reg and the lut superior displacement of these row, and at afterbody reg or the lut output stream of these row;
When described signal comparing unit is judged the reg that whether there is fault in this first area piece and lut in the output signal of the input signal that is input to each first area piece in first area or the second area according to signal input unit and this first area piece, be used for: judge whether the data stream of exporting from afterbody reg or the lut of each row is identical with the data stream of this row of input, if it is identical, the reg and the lut that then determine this row are normal, otherwise, determine that there be reg or the lut of fault in this row, record the row number of this fault; When the output signal of the input signal of each second area piece and this second area piece is judged the reg that whether there is fault in this first area piece or lut in be input to the 3rd zone or the 4th zone according to signal input unit, be used for: judge whether the data stream of exporting from the afterbody reg of each row is identical with the data stream of these row of input, if it is identical, the reg and the lut that then determine these row are normal, otherwise, determine that there be reg or the lut of fault in these row, record the row number of this fault.
20. FPGA failure detector according to claim 11 is characterized in that,
Described fault detection unit loads before the fpga chip detection software that generates in advance at the software loading unit, is further used for: in arbitrary register of FPGA, write preset data by the IOBUS interface earlier, and to the data negate in described arbitrary register; Read the data in described arbitrary register again, data and the preset data of reading compared, if the data of reading are identical with value after the preset data negate, determine that then the IOBUS interface is normal, otherwise, determine the IOBUS interface fault.
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