CN103227924B - A kind of arithmetic encoder and coded method - Google Patents
A kind of arithmetic encoder and coded method Download PDFInfo
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Abstract
The invention discloses a kind of arithmetic encoder method for designing and realize device, including following four technology: front buffer designs, algorithm structure combined optimization, muti bin treatment technology and mixing context storage mechanism, wherein front buffer design is that binary sequence (bin) number produced after Binary Conversion to solve a macro block can fluctuate in the range of the biggest one, and the binary sequence (bin) that binary arithmetic coding module (BAC) processed within the unit interval counts limited problem；After algorithm structure combined optimization mainly uses time borrowing technology that the process of low assigns into the process of range；Muti bin treatment technology is to utilize the calculating of MPS simply too much compared with LPS, so we can process multiple MPS a clock cycle；The storage method that mixing context storage mechanism is the application-specific for 2bins/cycle throughput of the present invention and invents, the method can carry out quick memory access to these models while storing substantial amounts of context model.The present invention is applicable to the coding of multi-stage pipeline arrangement, is particularly suited for high definition resolution real-time coding.
Description
Technical field
The present invention relates to digital video decoding technical field, particularly relate to a kind of AVS senior
Entropy coder and coded method.
Background technology
Video coding technique and video encoding standard are to include DTV, Internet video, mobile phone
The technical foundation of the audio frequency and video industry such as TV, MP3.Audio frequency and video industry can select at present
Source coding standard has four: MPEG-2, MPEG-4, MPEG-4AVC(are called for short AVC,
Also referred to as JVT, H.264), AVS, wherein AVS(Audio Video coding Standard,
Audio/video encoding standard) it is the abbreviation of " information technology advanced audio/video coding " series standard,
It is China's second filial generation source coding standard of possessing independent intellectual property right, is also that digital audio/video produces
The general character basic standard of industry.A kind of commonly used hybrid coding method of these source coding standard with
Remove the redundancy between huge information source data, such as: spatial redundancy, time redundancy, information
Entropy redundancy.
Entropy code is the requisite key link of video coding system, and it is responsible for utilizing letter
Breath Entropy principle removes comentropy redundancy, has reached the purpose of data compression.Wherein, MPEG-2 adopts
With huffman coding (Huffman Code), H.264 use based on context-adaptive with AVS
Variable-length encoding (CAVLC) and based on context adaptive binary arithmetic coding (CABAC).
CABAC is a kind of novel efficient entropy coding method, its design based on binarization, on
Hereafter 3 steps such as modeling, binary arithmetic coding.CABAC with sheet as code period,
The bin that the syntactic element binarization of whole piece obtains is carried out interval iteration division, thus obtains
To a subinterval, then appoint in this subinterval and take a value and represent this sheet syntactic element,
So, the bit number obtained after average, independent bin value coding may be
Mark, overcome CAVLC coding be necessary for single symbol distribution integer code length code word lack
Point, it is easier to approach limit entropy, it is thus achieved that higher code efficiency, therefore, AVS standard will be adopted
The encoder carrying out encoding with CABAC is referred to as senior entropy coder.But, CABAC's
Computational complexity is apparently higher than CAVLC.
In order to enable real-time coding HD video, it would be desirable to increase the throughput of encoder, with
Shi Bixu takes into account system delay, current arithmetic encoder, mostly pays close attention to throughput, to being
System delay is paid close attention to less.
Summary of the invention
In order to solve problem above, it is an object of the invention to provide one and include:
Front-buffer designs, in algorithm structure combined optimization, muti-bin treatment technology and mixing
The hereafter encoder of memory mechanism and coded method.
In the middle of the design of arithmetic encoder, owing to binary transforming module (binarizer) can
To pass through to process the multiple syntactic element substantial amounts of binary sequence of generation (bin) simultaneously, thus,
The throughput of binary arithmetic coding module (BAC) becomes the bottleneck of design.Gulp down for increasing
Telling rate, reduce and postpone, we use the scheme of macro-block level flowing water, but, due to a macro block
Binary sequence (bin) number produced after Binary Conversion can be in a biggest scope
Interior fluctuation, and the binary system that binary arithmetic coding module (BAC) processed within the unit interval
Sequence (bin) number is limited, and then we enter at binary transforming module (binarizer) and two
Add a buffer between arithmetic coding module processed (BAC) to buffer.Certainly, buffer
The biggest, the input of binary arithmetic coding module (BAC) is the most smooth, and design is got up easier,
The negative effect the most so brought is that the delay of system is the biggest, and chip area also becomes big simultaneously
?.Then, it would be desirable to do a compromise, it be easy to show that, in figure 3, if for appointing
Initial time t of meaning, regular time section T0In, have an input buffer's
Maximum total amount Q0, then buffer only need to be dimensioned to Q by us0, and by buffer
Output be set toBuffer overflow never can be ensured.
The employing of the binary arithmetic coding module (BAC) of present invention structure is fixed
The basic structure of 2bins/cycle throughput.The key of binary arithmetic coding module (BAC)
Path is the calculating of low in LPS in iterative process, thus the difficult point of this design is continuously
Occur how two LPS processed within a clock cycle.By observe it was found that
The iterative computation of range is the most relevant with self, and is far smaller than its operating time to low
Operating time, so, as it is shown in figure 5, we can be at the complete range of first time iterative computation
After, fulfil some calculation procedures of low ahead of schedule, when this just can reduce second time iterative computation
The operating time of low.Additionally, at log-domain, range is come by integer part and fractional part
Representing, when LPS occurs, we carry out renormalization operation to the integer part of range, this
The calculating of low in second time iterative computation can be simplified.By the effective profit to the two feature
With, we have obtained a fixing 2bins/cycle throughput, system delay relatively 1bin/cycle
The basic framework of encoder few 33%.
As shown in Figure 6, we use muti-bin treatment technology to improve throughput further.
This technology is mainly used in the residual error coefficient optimization most to producing bin number.As a example by AVS,
Residual error coefficient is encoded to Level(absLevel and sign by us) and Run number pair, to it
Use a primitive encoding (unary) scheme.The bin indexes absLevel or bin more than 1
The indexes Run more than 0 uses identical context, and we such bins is called SC
bins.Owing to SC bins is made up of several continuous print 0 and one 1, so major part situation
Under, the MPS of SC bins context is 0, and the calculating of MPS is simply too much compared with LPS,
So we can process multiple 0 a clock cycle.
The present invention uses the two-stage being made up of context RAM and local context buffer to deposit
Storage structure, and the handling up of binary arithmetic coding module (BAC) used due to the present invention
Rate is 2bins/cycle, and two bin of continuous print may belong to different syntactic elements (SE),
So mapping to context RAM causes certain difficulty, to this end, we devise
Dual-port RAM and corresponding local buffer.Further look at, it has been found that belong to
The bin index of second bin of two bin of different syntactic elements (SE) is often 0
(that is tending to belong to first bin of a syntactic element), then the present invention proposes
Mixing memory mechanism as shown in Figure 7: all belong to different syntactic element (SE) two
It is inner that the context model of first bin of bin is stored in Parasites Fauna (register group),
Other context model is stored in a dual-port RAM, and so we can be achieved with
The quick storage of context model.
Accompanying drawing explanation
Fig. 1 is present invention location in whole encoder；
Fig. 2 is the major function of the binary arithmetic coder based on context that the present invention uses
Module frame chart；
Fig. 3 is the buffer before the binary arithmetic coding module (BAC) that the present invention proposes
Model；
Fig. 4 is the arithmetic encoder whole design and framework that the present invention proposes；
Fig. 5 top half is the optimization of the worst case to continuous two LPS that the present invention proposes
Method, the latter half is muti-bin illustrative timing diagram；
Fig. 6 is the muti-bin detailed description of the invention that residual error coefficient is taked by the present invention；
Fig. 7 is the mixing storage method that the present invention proposes；
Fig. 8 is the selection gist of front buffer size in the embodiment of the present invention.
Detailed description of the invention
The present embodiment position in whole video coding system is as it is shown in figure 1, use macro-block level
The scheme of flowing water, as shown in Figure 4, wherein A represents Binary Conversion to its concrete module architectures
Module (binarizer), B represents context management module (CM), and C represents binary arithmetic
Coding module (BAC).The technical side separately below present invention proposed in these 3 modules
Case is made example and is illustrated.
Binary sequence (bin) the number meeting produced after Binary Conversion due to a macro block exists
Fluctuate in the range of the biggest one, and binary arithmetic coding module (BAC) is in the unit interval
Binary sequence (bin) number of interior process is limited, and then we are at binary transforming module
And between binary arithmetic coding module (BAC), add a buffer (binarizer)
Buffer.Certainly, buffer is the biggest, the input of binary arithmetic coding module (BAC)
The most smooth, design is got up easier, but the delay that the negative effect so brought is system is got over
Greatly, chip area also becomes greatly simultaneously.Then, it would be desirable to do a compromise, it be easy to show that,
In figure 3, if for arbitrary initial time t, regular time section T0In,
There is maximum total amount Q of an input buffer0, then the size of buffer only need to be set by we
It is set to Q0, and the output of buffer is set toBuffer overflow never can be ensured.
Then, when being embodied as, we are necessary for finding Q0And T0, for this, we test a series of
Video sequence, concrete outcome as shown in Figure 8, it can be seen that the present invention design T0
Using one macro-block line of coding (is 120 for the video sequence that resolution is 1080P
Macro block) needed for time, buffer size Q0100657 bin can be stored the most permissible, for
For the sake of insurance, the buffer that the present invention adopts can store 110000 bin.
2bins/cycle is fixed in the employing of the binary arithmetic coding module (BAC) of present invention structure
The basic structure of throughput.The critical path of binary arithmetic coding module (BAC) is iteration
During the calculating of low in LPS, thus the difficult point of this design is occur two LPS continuously
How to process within a clock cycle.By observing it was found that the iteration of range
Calculate only the most relevant with self, and when its operating time is far smaller than the operation to low
Between, so, as it is shown in figure 5, we can carry after the complete range of first time iterative computation
Before complete some calculation procedures of low, low when this just can reduce second time iterative computation
Operating time.Additionally, at log-domain, range is represented by integer part and fractional part,
When LPS occurs, we carry out renormalization operation to the integer part of range, and this can letter
Change the calculating of low in second time iterative computation.By the effective utilization to the two feature, I
Obtained a fixing 2bins/cycle throughput, the system delay coding compared with 1bin/cycle
The basic framework of device few 33%.
As shown in Figure 6, we use muti-bin treatment technology to improve throughput further.Should
Item technology is mainly used in the residual error coefficient optimization most to producing bin number.As a example by AVS, I
Residual error coefficient is encoded to Level(absLevel and sign) and Run number pair, it is adopted
By a primitive encoding (unary) scheme.The bin indexes absLevel or the bin indexes more than 1
Run more than 0 uses identical context, and we such bins is called SC bins.By
It is made up of several continuous print 0 and one 1 in SC bins, so in most cases, SC bins
The MPS of context is 0, and the calculating of MPS is simply too much compared with LPS, so we are permissible
Multiple 0 is processed a clock cycle.In the present embodiment, it is contemplated that with continuous programming code two
The circuit delay of the worst case of LPS matches, and we use the MPS processing scheme of 4-bin,
3-4 continuous print MPS can be processed within a clock cycle.The present embodiment is adopted
Muti-bin processing scheme averagely can improve the throughput of 15%, due to quantization parameter (QP)
When diminishing, residual error coefficient becomes many, and the bin number of generation increases therewith, so, at quantization parameter
(QP), when diminishing, the throughput that the program can improve is the most obvious.
The present invention uses the two-stage being made up of context RAM and local context buffer to deposit
Storage structure, and the handling up of binary arithmetic coding module (BAC) used due to the present invention
Rate is 2bins/cycle, and two bin of continuous print may belong to different syntactic elements (SE),
So mapping to context RAM causes certain difficulty, to this end, we devise
Dual-port RAM and corresponding local buffer.Further look at, it has been found that belong to
The bin index of second bin of two bin of different syntactic elements (SE) is often 0
(that is tending to belong to first bin of a syntactic element), then the present invention proposes
Mixing storage method as shown in Figure 7: all belong to different syntactic element (SE) two
It is inner that the context model of first bin of bin is stored in Parasites Fauna (register group),
Other context model is stored in a dual-port RAM, and so we can be achieved with
The quick storage of context model.The AVS standard used specific to the present invention, in order to quickly
It is stored in two that belong to different syntactic element (SE) of continuous programming code in a clock cycle
Bin, we are assigned with 5 dual-port RAM and corresponding local buffer.Consider simultaneously
Context weighting technique one bin of coding used in AVS standard may use about two
Literary composition model, and in the coded method of we 2bins/cycle can not continuous programming code two so
Bin, so we use single-port RAM and corresponding local buffer to store this
The context model corresponding for bin of sample, we used 324 context models altogether.
Last it is noted that obvious, above-described embodiment is only for clearly demonstrating the present invention
Example, and not restriction to embodiment.Ordinary skill people for art
For Yuan, change or the change of other multi-form can also be made on the basis of the above description
Dynamic.Here without also cannot all of embodiment be given exhaustive.And thus amplified out
Obviously change or change among still in protection scope of the present invention.
Claims (7)
1. an arithmetic encoder, mainly includes that binary transforming module, binary arithmetic are compiled
Code module and context modeling module, between three, data stream is separate, there is not feedback,
The mode using three class pipeline realizes, it is characterised in that: the work of described binary transforming module
With being that non-binary syntactic element is uniquely mapped as a binary sequence, wherein said
Non-binary syntactic element include motion vector, macro block (mb) type, sub-macroblock type, reference
Residual error data after frame number and change quantization；The effect of described context modeling module is by
Syntax elements encoded sets up probabilistic model, for the coding of current syntax element, completes coding
After, probabilistic model is updated；The effect of described binary arithmetic coding module is by binary system
Sequence and the context model selected for current syntax element carry out arithmetic coding, described binary system
Send together with the probabilistic model that the binary value that modular converter produces provides with context modeling module
Enter binary arithmetic coding module, and the binary value produced according to binary transforming module updates
The context model of context modeling module.
Arithmetic encoder the most according to claim 1, it is characterised in that: described two enter
Modular converter processed can process multiple syntactic element simultaneously, at it with binary arithmetic coding module
Between be provided with a buffer i.e. binary value buffer, for process each macro block produce not
Stable binary sequence number.
A kind of arithmetic encoder the most according to claim 1, it is characterised in that: described
Context modeling module uses a buffer i.e. SE line buffer, stores adjacent syntactic element
Value, selects for context.
A kind of arithmetic encoder the most according to claim 1, it is characterised in that: described
Context modeling module uses two-level memory, including context RAM and local caches, its
Middle local caches is for storing the context that nearest meeting is used, and context RAM is used for
Deposit all of contextual information.
A kind of arithmetic encoder the most according to claim 1, it is characterised in that: described
Binary arithmetic coding module uses the process of many bits, sufficiently utilizes the MPS i.e. maximum can
Can the computation complexity of symbol i.e. minimum far below LPS may symbol computation complexity this
Feature.
A kind of arithmetic encoder the most according to claim 5, it is characterised in that: described
Many bit process are that the processing method for continuous two LPS utilizes the range i.e. calculating of scope
Only rely on self, and the calculating treatmenting time of range be well below the low i.e. feature of lower limit,
After having processed range, the part operation of pretreatment low.
7. an arithmetic coding method, it is characterised in that: comprise the steps
The first step: judge that the syntactic element inputted is non-binary syntactic element, if
It is binary syntactic element, then skips binary transforming module, and non-binary grammer is first
Element then needs to carry out binarization by binary transforming module；
Second step, the string of binary characters that the first step obtains, according to the type selecting of syntactic element
Context, then binary value enters binary arithmetic coding together with the context model of selection
Module；
3rd step, according to the type of syntactic element, determines to be by fast coding, or directly
Enter bypass encoder, encode with fixing probabilistic model, then export encoding code stream,
And update context model according to coded identification.
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| CN103873870B (en) * | 2014-02-28 | 2017-03-29 | 芯原微电子(上海)有限公司 | A kind of AEC decoders of optimization |
| CN105025296B (en) * | 2014-04-30 | 2018-02-23 | 北京大学 | A kind of advanced mathematical encoder and its implementation |
| CN104918049A (en) * | 2015-06-03 | 2015-09-16 | 复旦大学 | Binary arithmetic coding module suitable for HEVC (high efficiency video coding) standards |
| US10142652B2 (en) * | 2016-05-05 | 2018-11-27 | Google Llc | Entropy coding motion vector residuals obtained using reference motion vectors |
| US11265561B2 (en) * | 2017-01-06 | 2022-03-01 | Mediatek Inc. | Method and apparatus for range derivation in context adaptive binary arithmetic coding |
| US10554988B2 (en) * | 2017-03-22 | 2020-02-04 | Qualcomm Incorporated | Binary arithmetic coding with parameterized probability estimation finite state machines |
| CN110915213B (en) | 2017-07-14 | 2021-11-02 | 联发科技股份有限公司 | Method and device for entropy coding and decoding of coding and decoding symbol |
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| CN1589025A (en) * | 2004-07-30 | 2005-03-02 | 联合信源数字音视频技术（北京）有限公司 | Vido decoder based on software and hardware cooperative control |
| CN101753148A (en) * | 2008-11-28 | 2010-06-23 | 索尼株式会社 | Arithmetic decoding apparatus |
| CN102186075A (en) * | 2011-04-28 | 2011-09-14 | 北京大学 | Entropy coder and realization method thereof |
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| CN1589025A (en) * | 2004-07-30 | 2005-03-02 | 联合信源数字音视频技术（北京）有限公司 | Vido decoder based on software and hardware cooperative control |
| CN101753148A (en) * | 2008-11-28 | 2010-06-23 | 索尼株式会社 | Arithmetic decoding apparatus |
| CN102186075A (en) * | 2011-04-28 | 2011-09-14 | 北京大学 | Entropy coder and realization method thereof |
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