CN103220370B - Method and device for achieving single wire protocol (SWP) interface and SWP system - Google Patents
Method and device for achieving single wire protocol (SWP) interface and SWP system Download PDFInfo
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- CN103220370B CN103220370B CN201310068403.5A CN201310068403A CN103220370B CN 103220370 B CN103220370 B CN 103220370B CN 201310068403 A CN201310068403 A CN 201310068403A CN 103220370 B CN103220370 B CN 103220370B
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Abstract
The invention relates to a method and device for achieving a single wire protocol (SWP) interface. The method comprises the steps of connecting a resistor between a first universal input/output port and a second universal input/output port of a universal system chip of common equipment; obtaining the electrical level state of the first universal input/output port and a received signal value; and setting the electrical level state or the working state of the second universal input/output port according to the current electrical level state of the first universal input/output port and received data signals, and sending data signals which respond to a primary device. Only the resistor is connected between the first universal input/output port and the second universal input/output port can the fact that the SWP interface receives and sends the data signals be achieved, the universal system chip does not need to be modified, a specific hardware detection and control module does not need to be added in the chip, and cost is saved.
Description
Technical field
The present invention relates to communication technical field, more particularly, to a kind of method and apparatus realizing SWP interface and SWP system
System.
Background technology
NFC（Near Field Communication, near field communication (NFC)）It is extensive in mobile-payment system
A kind of technology using, SWP（Single Wire Protocol, single wire transmission agreement）It is one kind that SOC is communicated with NFC module
Standard agreement.SOC（System on Chip, SOC(system on a chip)）The common practices of support SWP are in one hardware of core Embedded
Module PHY（The hardware module that physical layer detects and controls）, so support SWP to common equipment, then need to common
The SOC of device is transformed, and redesigns, and increases hardware module PHY, and cost is larger.
Content of the invention
The main object of the present invention is to provide a kind of method and apparatus realizing SWP interface and SWP system it is intended to pass through
The existing chip of the existing equipment mode of software and a small amount of hardware realizes the SWP interface of equipment, cost-effective.
The present invention proposes a kind of method realizing SWP interface it is characterised in that including：
The level state obtaining and identifying the first general I/O port and the data signal receiving；
Level state according to the first general I/O port and the described data signal receiving, setting second is led to
Level state or working condition with I/O port.
Preferably, the described level state obtaining described first general I/O port and the data signal receiving
Step includes：
Constantly obtain the relative pass of the level state of the first general I/O port and high level and low level width
System；
Judge whether the width of described high level is more than described low level width；
If it is determined that described first general I/O port is to receive signal 1；
If not it is determined that described first general I/O port is to receive signal 0.
Preferably, the described level state according to the first general I/O port and the data signal receiving, determines
The step of the level state of the second general I/O port or working condition includes：
If described first general I/O port is currently high level state, judged according to the data signal receiving
Want output response data signal 1 or response data signal 0 or not output response data signal；
If judging to want output response data signal 1, the state arranging described second general I/O port is low level
State or input state；
If the judgement described response data signal 0 of output or not output response data signal, arrange described second general defeated
Enter/state of delivery outlet is high level state.
Preferably, the described level state according to the first general I/O port and the data signal receiving, determines
The described level state of the second general I/O port or the step of working condition also include：
If it is determined that described first general I/O port is low level state, then described second universal input/output is set
The state of mouth is low level state.
The present invention also proposes a kind of device realizing SWP interface it is characterised in that including：
Acquisition module, believes for the level state obtaining and differentiating the first general I/O port and the data receiving
Number；
Processing module, for the level state according to described first general I/O port and the described number receiving
It is believed that number, level state or the working condition of the second general I/O port are set.
Preferably, described acquisition module includes：
Acquiring unit, for constantly obtaining the high level of the first general I/O port and low level level state
And the relativeness of width；
First judging unit, whether the width for judging described high level is more than described low level width；
Processing unit, if for judging that the width of described high level is more than described low level width it is determined that described the
One general I/O port is to receive signal 1；And if judging the width of described high level less than described low level width
Degree, determines that described first general I/O port is to receive signal 0.
Preferably, described processing module includes：
Second judging unit, if being currently high level state for described first general I/O port, judges defeated
Go out response data signal 1 or response data signal 0 or not output response data signal；
Arranging unit, if for judging to want output response data signal 1, arrange described second general I/O port
State be low level state or input state；If judging output response data signal 0 or not output response data signal, set
The state putting described second general I/O port is high level state.
Preferably, if it is currently low level state that described arranging unit is additionally operable to described first general I/O port,
The state arranging described second general I/O port is low level state.
The present invention also proposes a kind of SWP communication system it is characterised in that including SWP main equipment and SWP from equipment, described
SWP comprises a System on Chip/SoC from equipment, is connected the first general I/O port with SWP main equipment, and is connected to described first
Resistance between general I/O port and the second general I/O port；Described System on Chip/SoC is general defeated according to described first
Enter/the data signal that sends of the described SWP main equipment that receives of delivery outlet, and change described the according to data signal to be exported
The level state of two general I/O ports or working condition.By external resistance, the electricity of the second general I/O port
Pressure condition is converted into being sent to the current status of the data signal of SWP main equipment.Described SWP main equipment is according to the response receiving
The current status identification of data signal determines the described response data signal receiving.
Proposed by the invention method and apparatus and the SWP system of realizing SWP interface, by the system in conventional equipment
A resistance is connected between first general I/O port of chip and the second general I/O port, general defeated according to first
Enter/level state of delivery outlet and the data signal that receives determining the state controlling the second general I/O port, only
Realize SWP interface by connecting a resistance between the first general I/O port and the second general I/O port
With transmission data signal it is not necessary to modification general-purpose system chip is it is not necessary to increase specific hardware detection and control in the chips
Module, saves cost.
Brief description
Fig. 1 realizes the schematic flow sheet of the method preferred embodiment of SWP interface for the present invention；
Fig. 2 for the present invention realize in the method for SWP interface using clock sampling or software sentence method for distinguishing obtain first lead to
With the level state of I/O port and the schematic flow sheet of the data signal receiving；
Fig. 3 realizes arranging level state or the work of the second general I/O port in the method for SWP interface for the present invention
The schematic flow sheet of state one embodiment；
Fig. 4 realizes arranging level state or the work of the second general I/O port in the method for SWP interface for the present invention
The schematic flow sheet of another embodiment of state；
Fig. 5 realizes the structural representation of the device preferred embodiment of SWP interface for the present invention；
Fig. 6 realizes the structural representation of acquisition module in the device of SWP interface for the present invention；
Fig. 7 realizes the structural representation of processing module in the device of SWP interface for the present invention；
Fig. 8 is the structural representation of SWP communication system preferred embodiment of the present invention.
The realization of the object of the invention, functional characteristics and advantage will be described further in conjunction with the embodiments referring to the drawings.
Specific embodiment
Below in conjunction with the accompanying drawings and specific embodiment is described further with regard to technical scheme.It should be appreciated that this
The described specific embodiment in place, only in order to explain the present invention, is not intended to limit the present invention.
With reference to Fig. 1, Fig. 1 realizes the schematic flow sheet of the method preferred embodiment of SWP interface for the present invention.
The method that what the present embodiment was proposed realize SWP interface, including：
Step S10, the level state obtaining and identifying the first general I/O port and the data signal receiving；
By hardware or software sentence method for distinguishing all can obtain and identify the first general I/O port level state and
The data signal receiving.General defeated with the lasting sampling first of the mode of hardware clock sampling or software reading register value
Enter/the level state of delivery outlet, each sampled point corresponds to a level value.When the first general I/O port is from high level
It is changed into low level to become high level again or be changed into high level from low level and become the signal that low level is identified as receiving again
A cycle.The relation between number according to sampled point when high level state and low level state differentiates high level and low electricity
The relativeness of flat width, thus the data value signal that identification receives..
Step S20, the level state according to the first general I/O port and the data signal receiving, setting the
The level state of two general I/O ports or working condition.
The level state of the first general I/O port includes high level state and low level state, general according to first
The current level state of I/O port and the data signal receiving determine whether to output response data signal, to second
The level state of general I/O port and working condition are arranged accordingly.
The method that what the present embodiment was proposed realize SWP interface, by the first general I/O port in conventional equipment
With second connect a resistance between general I/O port, System on Chip/SoC is according to the level state of the first general I/O port
And the data signal receiving to determine control the second general I/O port state, only pass through the first universal input/
Connect a resistance between delivery outlet and the second general I/O port to realize SWP interface and to send data signal, be not required to
Change general-purpose system chip it is not necessary to increase specific hardware detection and control module in the chips, save cost.
With reference to Fig. 2, Fig. 2 realizes obtaining the level shape of the first general I/O port in the method for SWP interface for the present invention
The schematic flow sheet of state.
Based on above-described embodiment, step S10 includes：
Step S11, constantly obtains level state and high level and the low level width of the first general I/O port
Relativeness；
With lasting sampling first general I/O port of the mode of hardware clock sampling or software reading register value
Level state, each sampled point corresponds to a level value.When the first general I/O port is changed into low level again from high level
Become high level or be changed into, from low level, a cycle that high level becomes the signal that low level is identified as receiving again.Typically
There are multiple sampled points in a cycle, the more differentiations of sampled point are more accurate.Adopt during according to high level state and low level state
The number of sampling point is determining high level and low level width, and is compared.
Step S12, judges whether the width of high level is more than low level width；
Than higher level and low level width when, can be using comparing in the first general I/O port signal
The number of times of the high level sampling in the cycle and sample low level number of times to realize.
Step S13, if judge high level width be more than low level width it is determined that described first universal input/defeated
Export as receiving signal 1；
Digital signal includes signal 1 and 0 two kinds of signal, if judging, the width of high level more than low level width, that is, is adopted
Sample to high level number of times be more than sample low level number of times, illustrate the first general I/O port high level lasting when
Between long, then judge this first general I/O port for receiving signal 1.
Step S14, if judging, the width of high level is less than low level width it is determined that the first general I/O port
For receiving signal 0.
If judge high level width be less than low level width, that is, sample high level number of times be less than sample low electricity
Flat number of times, illustrates that the first general I/O port low level persistent period is longer, then judge this first universal input/
Delivery outlet is to receive signal 0.
With reference to Fig. 3, Fig. 3 realizes arranging the level shape of the second general I/O port in the method for SWP interface for the present invention
State or the schematic flow sheet of working condition one embodiment.
Based on above-described embodiment, step S20 includes：
Step S21, if described first general I/O port is currently high level state, according to the data receiving
Signal judges to want output response data signal 1 or response data signal 0 or not output response data signal；
Because response data signal is current signal, so when output response data signal 1, this response data signal has
Electric current, when output response data signal 0 or not output response data signal, this response data signal no current.First is general
It is connected with a resistance, if the first general I/O port is detected between I/O port and the second general I/O port
For high level state, because electric current flows to low level by high level, believe to the second general I/O port output response data
Number 1, then the state that can arrange the second general I/O port is low level state or input state can achieve,.
Step S22, if judging to want output response data signal 1, the state arranging the second general I/O port is low
Level state or input state.
If the first general I/O port is detected is high level state, and wants output response data signal 1, due to electricity
Stream flows to low level by high level, and is connected with electricity between the first general I/O port and the second general I/O port
Resistance, then can be set to low level by the second general I/O port, then can be general in the first general I/O port and second
Form loop, then the current signal that has of the second delivery outlet exports between I/O port；Also can be by the second universal input/output
Mouth is set to input state, then also can form loop between the first I/O port and the second general I/O port, then
The current signal that has of the second delivery outlet exports, now output response data signal 1.
Step S23, if judging output response data signal 0 or not output response data signal, setting second is general defeated
Enter/state of delivery outlet is high level state.
It is connected with a resistance, if detecting first between first general I/O port and the second general I/O port
General I/O port for high level state, because electric current flows to low level by high level, due to according to the data receiving
Signal judges output response data signal 0 or not output response data signal, then can be set to the second general I/O port
On high level, the first general I/O port and the second general I/O port, level state is identical, then no current on resistance
Pass through, then the corresponding data signal exporting is response data signal 0 or thinks do not have current signal to export.
With reference to Fig. 4, Fig. 4 realizes arranging the level shape of the second general I/O port in the method for SWP interface for the present invention
State or the schematic flow sheet of working condition another embodiment.
Based on above-described embodiment, S20 of the present invention also includes：
Step S24, if the first general I/O port is currently low level state, arranges the second universal input/output
The state of mouth is low level state.
It is connected with a resistance, if detecting first between first general I/O port and the second general I/O port
General I/O port for low level state, because electric current flows to low level by high level, now by the second universal input/
Delivery outlet is set to low level state, does not have current signal to export.
With reference to Fig. 5, Fig. 5 realizes the structural representation of the device preferred embodiment of SWP interface for the present invention.
What the present embodiment was proposed realizes the device of SWP interface, including：
Acquisition module 10, for the level state obtaining and differentiating the first general I/O port and the data receiving
Signal；
By hardware or software sentence method for distinguishing all can obtain and identify the first general I/O port level state and
The data signal receiving.General defeated with the lasting sampling first of the mode of hardware clock sampling or software reading register value
Enter/the level state of delivery outlet, each sampled point corresponds to a level value.When the first general I/O port is from high level
It is changed into low level to become high level again or be changed into high level from low level and become the signal that low level is identified as receiving again
A cycle.The relation between number according to sampled point when high level state and low level state differentiates high level and low electricity
The relativeness of flat width, thus the data value signal that identification receives..
Processing module 20, for the level state according to the first general I/O port and the first universal input/output
The data signal that mouth receives, the level state of setting the second general I/O port or working condition.
The level state of the first general I/O port includes high level state and low level state, general according to first
The current level state of I/O port and the data signal receiving determine whether to output response data signal, to second
The level state of general I/O port and working condition are arranged accordingly.
The method that what the present embodiment was proposed realize SWP interface, by the first general I/O port in conventional equipment
With second connect a resistance between general I/O port, System on Chip/SoC is according to the level state of the first general I/O port
And the data signal receiving to determine control the second general I/O port state, only pass through the first universal input/
Connect a resistance between delivery outlet and the second general I/O port to realize SWP interface and to send data signal, be not required to
Change general-purpose system chip it is not necessary to increase specific hardware detection and control module in the chips, save cost.
With reference to Fig. 6, Fig. 6 realizes the structural representation of acquisition module in the device of SWP interface for the present invention.
Based on above-described embodiment, acquisition module 10 includes：
Acquiring unit 11, the level state for lasting acquisition first general I/O port and high level and low electricity
Flat width；
With lasting sampling first general I/O port of the mode of hardware clock sampling or software reading register value
Level state, each sampled point corresponds to a level value.When the first general I/O port is changed into low level again from high level
Become high level or be changed into, from low level, a cycle that high level becomes the signal that low level is identified as receiving again.Typically
There are multiple sampled points in a cycle, the more differentiations of sampled point are more accurate.Adopt during according to high level state and low level state
The number of sampling point is determining high level and low level width, and is compared.
First judging unit 12, whether the width for judging described high level is more than low level width；
Than higher level and low level width when, can be using comparing in the first general I/O port signal
The number of times of the high level sampling in the cycle and sample low level number of times to realize.
Processing unit 13, if for judge the width of high level be more than low level width it is determined that the first universal input/
Delivery outlet is to receive signal 1；And if judge high level width be less than low level width, determine the first universal input/
Delivery outlet is to receive signal 0.
Digital signal includes signal 1 and 0 two kinds of signal, if judging, the width of high level more than low level width, that is, is adopted
Sample to high level number of times be more than sample low level number of times, illustrate the first general I/O port high level lasting when
Between long, then judge this first general I/O port for receiving signal 1.If judging, the width of high level is less than low electricity
Flat width, that is, the number of times sampling high level, less than sampling low level number of times, illustrates that the first general I/O port is low
The persistent period of level is longer, then judge this first general I/O port for receiving signal 0.
With reference to Fig. 7, Fig. 7 realizes the structural representation of processing module in the device of SWP interface for the present invention.
Based on above-described embodiment, processing module 20 includes：
Second judging unit 21, if being currently high level state for described first general I/O port, judging will
Output response data signal 1 or response data signal 0 or not output response data signal；
Because response data signal is current signal, so when output response data signal 1, this response data signal has
Electric current, when output response data signal 0 or not output response data signal, this response data signal no current.First is general
It is connected with a resistance, if the first general I/O port is detected between I/O port and the second general I/O port
For high level state, because electric current flows to low level by high level, believe to the second general I/O port output response data
Number 1, then the state that can arrange the second general I/O port is low level state or input state can achieve,.
Arranging unit 22, if for judging to want output response data signal 1, arrange the second general I/O port
State is low level state or input state；If judging to want output response data signal 0 or not output response data signal, set
The state putting the second general I/O port is high level state.
If the first general I/O port is detected is high level state, and wants output response data signal 1, due to electricity
Stream flows to low level by high level, and is connected with electricity between the first general I/O port and the second general I/O port
Resistance, then can be set to low level by the second general I/O port, then can be general in the first general I/O port and second
Form loop, then the current signal that has of the second delivery outlet exports between I/O port；Also can be by the second universal input/output
Mouth is set to input state, then also can form loop between the first I/O port and the second general I/O port, then
The current signal that has of the second delivery outlet exports, i.e. output response data signal 1.
It is connected with a resistance, if detecting first between first general I/O port and the second general I/O port
General I/O port for high level state, because electric current flows to low level by high level, due to according to the data receiving
Signal judges output response data signal 0 or not output response data signal, then can be set to the second general I/O port
On high level, the first general I/O port and the second general I/O port, level state is identical, then no current on resistance
Pass through, then the corresponding data signal exporting is response data signal 0 or thinks do not have current signal to export.
Based on above-described embodiment, if it is currently low level state that arranging unit 22 is additionally operable to the first general I/O port,
The state low level state of the second general I/O port is then set.
It is connected with a resistance, if detecting first between first general I/O port and the second general I/O port
General I/O port for low level state, because electric current flows to low level by high level, now by the second universal input/
Delivery outlet is set to low level state, does not have current signal to export.
With reference to Fig. 8, Fig. 8 is the structural representation of SWP communication system preferred embodiment of the present invention.
The SWP communication system that the present embodiment is proposed includes SWP main equipment 1 and SWP from equipment 2, and SWP comprises from equipment 2
One System on Chip/SoC, the first general I/O port GPIO1 being connected with SWP main equipment, and be connected to the first universal input/
Resistance R between delivery outlet GPIO1 and the second general I/O port GPIO2；System on Chip/SoC is according to the first universal input/defeated
The data signal that the SWP main equipment that outlet GPIO1 receives sends, and response data signal setting second to be exported is general
The level state of I/O port GPIO2 or working condition；By external resistance R, the second general I/O port GPIO2
Voltage status be converted into being sent to the current status of the data signal of SWP main equipment 1；SWP main equipment 1 is according to the sound receiving
The current status answering data signal identify the response data signal receiving.
SWP main equipment can be NFC processor, and SWP is from the SIM that equipment can be mobile phone.First general I/O port
It is connected with a resistance between GPIO1 and the second general I/O port GPIO2, because electric current flows to low level by high level, if
Detect the first general I/O port GPIO1 for high level state, and judge that output rings according to the data signal receiving
Answer data signal 1, then the second general I/O port GPIO2 can be set to low level or input state, first is general defeated
Enter/formed between delivery outlet GPIO1 and the second general I/O port GPIO2 loop, the second general I/O port output
Response data signal 1；If detect the first general I/O port GPIO1 for high level state, and judge output number of responses
It is believed that number 0 or not output response data signal, then the second general I/O port GPIO2 is set to high level；If detecting
First general I/O port GPIO1 for low level state, then the second general I/O port GPIO2 is set to low electricity
Flat, not output response data signal.The data signal receiving is voltage signal, and response data signal is current signal.
The foregoing is only the preferred embodiments of the present invention, not thereby limit the scope of the claims of the present invention, every utilization
The equivalent structure transformation that description of the invention and accompanying drawing content are made, or directly or indirectly it is used in other related technology necks
Domain, is included within the scope of the present invention.
Claims (5)
1. a kind of method realizing single wire transmission agreement SWP interface is it is characterised in that include：
Obtain and the identification level state of the first general I/O port and the data signal receiving, wherein, according to described the
The data value signal that the relativeness determination of the high level of one general I/O port and low level width receives；
Level state according to the first general I/O port and the data signal receiving, setting the second universal input/defeated
The level state of outlet or working condition；
Wherein, described first general I/O port is connected with described second general I/O port by first resistor；
The step of the described level state and the data signal receiving obtaining described first general I/O port includes：
The lasting level state of acquisition first general I/O port and the relativeness of high level and low level width；
Judge whether the width of described high level is more than described low level width；
If it is determined that described first general I/O port is to receive signal 1；
If not it is determined that described first general I/O port is to receive signal 0；
Judge whether the width of described high level includes more than described low level width：Relatively in the first universal input/output
The number of times of the high level sampling in a cycle of message number and the low level number of times of sampling；When sampling in a cycle
High level number of times be more than sampling low level number of times when it is determined that described first general I/O port be receive
Signal 1；
The described level state according to the first general I/O port and the data signal receiving, setting second is general defeated
Enter/level state of delivery outlet or the step of working condition include：
If described first general I/O port is currently high level state, judged according to the data signal having been received by
Want output response data signal 1 or response data signal 0 or not output response data signal；
If judging to want output response data signal 1, the state arranging described second general I/O port is low level state
Or input state；
If judging to want output response data signal 0 or not output response data signal, described second universal input/output is set
The state of mouth is high level state.
2. method according to claim 1 is it is characterised in that the described electricity current according to the first general I/O port
Level state and the data signal receiving, determine that the step of the level state of described second general I/O port also includes：
If it is determined that described first general I/O port is currently low level state, then described second universal input/output is set
Mouth is low level state.
3. a kind of device realizing single wire transmission agreement SWP interface is it is characterised in that include：
Acquisition module, for the level state obtaining and identifying the first general I/O port and the data signal receiving, its
In, the relativeness of high level according to described first general I/O port and low level width determines and receives
Data value signal；
Processing module, for the level state current according to the first general I/O port and the data signal that receives, if
Put level state or the working condition of the second general I/O port；
Wherein, described acquisition module includes：
Acquiring unit, the level state for lasting acquisition first general I/O port and high level and low level width
Degree；
First judging unit, for relatively and judge that whether the width of described high level is more than described low level width；
Processing unit, if for judging that the width of described high level is more than described low level width it is determined that described first is logical
Receive signal 1 with I/O port；And if judging that the width of described high level, less than described low level width, determines
Described first general I/O port receives signal 0；Described processing unit is additionally operable to：Relatively in the first universal input/output
The number of times of the high level sampling in a cycle of message number and the low level number of times of sampling；When sampling in a cycle
High level number of times be more than sampling low level number of times when it is determined that described first general I/O port be receive
Signal 1；
Described processing module includes：
Second judging unit, if being currently high level state for described first general I/O port, judges sound to be exported
Answer data signal 1 or response data signal 0 or not output response data signal；
Arranging unit, if for judging to want output response data signal 1, arrange the shape of described second general I/O port
State is low level state or input state；If judging to want output response data signal 0 or not output response data signal, arrange
The state of described second general I/O port is high level state.
If 4. device according to claim 3 is it is characterised in that described arranging unit is additionally operable to judge that described first is general
I/O port is low level state, then arranging described second general I/O port is low level state.
5. a kind of single wire transmission agreement SWP communication system is it is characterised in that include SWP main equipment and SWP from equipment, described SWP
Comprise a System on Chip/SoC, the second general I/O port, the first universal input being connected with SWP main equipment/output from equipment
Mouthful, and it is connected to the resistance between described first general I/O port and the second general I/O port；Described system
Chip receives according to the high level of described first general I/O port and the relativeness determination of low level width
Data value signal；Change level state or the work of described second general I/O port according to data signal to be exported
State；By external resistance, the voltage status of the second general I/O port are converted into being sent to the data of SWP main equipment
The current status of signal；Described SWP main equipment receives according to the current status identification determination of the response data signal receiving
Described response data signal；
Wherein, described System on Chip/SoC is used for：The lasting level state of acquisition first general I/O port and high level and low
The width of level；Relatively and judge that whether the width of described high level is more than described low level width；If judging described high electricity
Flat width is more than described low level width it is determined that described first general I/O port receives signal 1；And if
Judge that the width of described high level is less than described low level width, determine that described first general I/O port receives letter
Number 0；The number of times of high level relatively sampling in a cycle of the first general I/O port signal and the low electricity of sampling
Flat number of times；When the number of times of the high level sampling in a cycle is more than the low level number of times of sampling it is determined that described
First general I/O port is to receive signal 1；
Described System on Chip/SoC is additionally operable to：If described first general I/O port is currently high level state, judge to export
Response data signal 1 or response data signal 0 or not output response data signal；If judging to want output response data signal 1,
The state arranging described second general I/O port is low level state or input state；If judging to want output response data
Signal 0 or not output response data signal, then the state arranging described second general I/O port is high level state.
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| CN103577976A (en) * | 2013-11-11 | 2014-02-12 | 杭州晟元芯片技术有限公司 | SWP implantation device of security chip |
| CN112118004B (en) * | 2020-11-19 | 2021-04-09 | 四川科道芯国智能技术股份有限公司 | SWP interface circuit and terminal |
| CN112511153B (en) * | 2021-02-02 | 2021-05-18 | 北京紫光青藤微系统有限公司 | SWP main interface circuit and terminal |
| CN115174431B (en) * | 2022-06-30 | 2023-09-05 | 无锡融卡科技有限公司 | Simple SWP full duplex logic signal acquisition device and method |
| CN116701289B (en) * | 2022-09-15 | 2024-04-12 | 荣耀终端有限公司 | Communication method and equipment |
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| CN101753722A (en) * | 2008-12-09 | 2010-06-23 | 上海华虹集成电路有限责任公司 | Interface circuit meeting single wire protocol (SWP) on subscriber identity module (SIM) card chip |
| CN102163273A (en) * | 2011-04-26 | 2011-08-24 | 武汉天喻信息产业股份有限公司 | Card reading equipment supporting SW-protocol-based mobile payment SD card |
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| KR20120103929A (en) * | 2011-03-11 | 2012-09-20 | 삼성전자주식회사 | Apparatus and method for short range communication in mobile terminal |
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| CN101753722A (en) * | 2008-12-09 | 2010-06-23 | 上海华虹集成电路有限责任公司 | Interface circuit meeting single wire protocol (SWP) on subscriber identity module (SIM) card chip |
| CN102163273A (en) * | 2011-04-26 | 2011-08-24 | 武汉天喻信息产业股份有限公司 | Card reading equipment supporting SW-protocol-based mobile payment SD card |
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