CN103208302B - Memory device and method for selecting regional bit line in the memory device - Google Patents
Memory device and method for selecting regional bit line in the memory device Download PDFInfo
- Publication number
- CN103208302B CN103208302B CN201210013865.2A CN201210013865A CN103208302B CN 103208302 B CN103208302 B CN 103208302B CN 201210013865 A CN201210013865 A CN 201210013865A CN 103208302 B CN103208302 B CN 103208302B
- Authority
- CN
- China
- Prior art keywords
- bit line
- serial
- storage unit
- stratum
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention discloses a memory device and method for selecting a regional bit line in the memory device. The memory device comprises memory unit blocks with a plurality of levels; each level comprises a plurality of memory unit bars extending to a first direction between a memory unit block first end and a memory unit block second end; a first bit line structure in each level is positioned on the first end of the memory unit block, and forms serial coupling with first memory unit extending from the first end; a second bit line structure in each level is positioned on the second end of the memory unit block, and forms serial coupling with second memory unit extending from the second end; a plurality of bit line pairs extend to the first direction, each bit line pair comprising an even bit line and an odd bit line; an odd and even bit line connector respectively connects the odd and even bit lines to the second and first bit line structures; and each bit line in a serial connection bit line pair is separated by a bit line in an adjacent bit line pair.
Description
Technical field
Technology of the present invention is about high density memory Set, particularly about a kind of memory storage and the method choosing region bit line in this memory storage.
Background technology
When the critical dimension of the device in integrated circuit is to the limit of usual memory cell technologies, deviser then then the multiple layer stack planar technique of seeking storage unit to reach higher storage density, and the cost that each bit is lower.For example, thin-film transistor technologies has been applied among charge capturing memory, the paper " A multi-Layer StackableThin-Film Transistor (TFT) NAND-Type Flash Memory " as Lai Dengren can be consulted, IEEE Int ' l ElectronDevice Meeting, on Dec 11st ~ 13,2006; And the paper " ThreeDimensionally Stack NAND Flash Memory Technology Using Stacking SingleCrystal Si Layers on ILD and TANOS structure for Beyond 30nm Node " of the people such as Jung, IEEEInt ' l Electron Device Meeting, on Dec 11st ~ 13,2006.
In addition, plotted point array technique has also been applied among antifuse memory, the paper " 512-Mb PROM with a Three Dimensional Array ofDiode/Anti-fuse Memory Cells " as people such as Johnson can be consulted, IEEE J.of Solid-state Circuits, vol.38, no.11, in November, 2003.In the design described by the people such as Johnson, multilayer wordline and bit line are used, and it has memory element in plotted point.This memory element comprises p+ polysilicon anode and is connected with wordline, and n+ polysilicon negative electrode is connected with bit line, and is separated by anti-fuse material between negative electrode and positive electrode.
Summary of the invention
Technology described herein reduces between adjacent integral bit line and the interstructural capacitive couplings load of adjacent bit lines.
First example of memory storage of the present invention comprises storage unit block and has multiple stratum.It is the first direction extended between the first end of storage unit block and the second end that each stratum comprises multiple storage unit rectangular.The first bit line structure in each stratum is the first end being positioned at storage unit block.Each first bit line structure operation couples with the first storage unit extended in a first direction is rectangular.Second line structure in each stratum is the second end being positioned at storage unit block.The operation of each second line structure couples with the second storage unit extended in a second direction is rectangular.Multiple bit line extends on first direction, and it at least comprises first, second and one the 3rd bit line pair of series connection, and each bit line is to comprising an even bitlines and an odd bit lines.Odd bit lines is connected with second line structure by odd bit lines connector, and even bitlines is connected with the first bit line structure by even bitlines connector.Each bit line of one series connection bit line pairs is separated by the bit line adjoining bit line pairs.
The first storage unit in some example, the odd bit lines of the second bit line pairs is between the odd bit lines and even bitlines of the first bit line pairs, the even bitlines of the first bit line pairs is between the odd bit lines and even bitlines of the second bit line pairs, and second the even bitlines of bit line pairs between the even bitlines and the odd bit lines of the 3rd bit line pairs of the first bit line pairs, wherein when odd bit lines pair and even bitlines can be reduced by the capacitive couplings separated between bit line when reading.In some example, the interval odd bit lines connector in a series of odd bit lines connector comprises a horizontal knuckle section, and the interval even bitlines connector in a series of even bitlines connector comprises a horizontal knuckle section.
The first storage unit in some example, this first bit line structure and the operation of this second line structure upper by serial selection change-over switch and this first and this second storage unit serial couple.Some example comprises many wordline and the first serial selection line and the second serial selection line group; Wordline in many wordline is arranged to choose in multiple stratum a corresponding stored unit plane orthogonal with this storage unit serial, this group first serial selection line be arranged to choose serial select change-over switch the storage unit serial of correspondence is connected with the first bit line structure in multiple stratum, this group second serial selection line be arranged to choose serial selection change-over switch the storage unit serial of correspondence is connected with the second line structure in multiple stratum.
Second example of memory storage of the present invention comprises storage unit block and has multiple stratum.It is the first direction extended between the first end of storage unit block and the second end that each stratum comprises multiple storage unit rectangular.Bit line structure in each stratum is the first end and the second end that are positioned at storage unit block.The operation of each line structure is couples rectangular with storage unit.Multiple bit line extends on first direction, its at least comprise series connection one first, second, one the 3rd and 1 the 4th bit line pair.Bit line is to having end points on the first end of storage unit block and the bit line structure of the second end.Bit line connector on this first end of this storage unit block, with by this second and the 4th bit line pair be connected with this first bit line structure; The right bit line connector of this second bit line has a horizontal turn-around zone and roughly extends the right below of this first bit line; And the right bit line connector of the 4th bit line has a horizontal turn-around zone and roughly extends the right below of the 3rd bit line.
The second storage unit in some example, bit line connector in this storage unit block this second end by this first and the 3rd bit line pair be connected with this second line structure.More comprise this second end that the right bit line connector of this first bit line is positioned at this storage unit block in some example there is a horizontal turn-around zone roughly to extend the right below of this second bit line; And the right bit line connector of the 3rd bit line this second end of being positioned at this storage unit block has a horizontal turn-around zone and roughly extends the right below of the 4th bit line.In some example, this second and the right bit line connector of the 4th bit line be connected with this bit line structure at different estate.
Another object of the present invention is about a kind of method choosing region bit line in a memory storage.This region bit line comprises that the operation of one group of even number region bit line is upper to be coupled a first end of the first bit line structure in multiple stratum and this memory storage, and one group of odd number region bit line operates and coupled by one second end of the second line structure in the plurality of stratum and this memory storage.Comprise according to the method and choose an even number region bit line; Choose an odd number region bit line; And these selecting steps carry out in the mode that this region bit line chosen is not adjacent to each other.In some example, this even number region bit line selecting step comprises to be chosen from the even number region bit line at least one of following arrangement: BL0, BL2, BL4, BL6, BL8, BL10, BL12, BL14; This odd number region bit line selecting step comprises to be chosen from the odd number region bit line at least one of following arrangement: BL1, BL3, BL5, BL7, BL9, BL11, BL13, BL15; And those position bit lines arrange with following order: BL0, BL1, BL2, BL3, BL4, BL5, BL6, BL7, BL8, BL9, BL10, BL11, BL12, BL13, BL14, BL15.In some example, these selecting steps choose even number region bit line BL0 and odd number region bit line BL9.
The present invention defined by right.These and other objects, feature, and embodiment, graphic being described of arranging in pairs or groups in the chapters and sections of following embodiments.
Accompanying drawing explanation
Fig. 1 shows the simplification schematic three dimensional views of a three-dimensional memory devices.
Fig. 2 shows the schematic diagram of a structure part in Fig. 1.
Fig. 3 shows the example schematic of a three-dimensional Sheffer stroke gate flash array part, and it has three layers is a representative schematic diagram that can comprise multilayered memory blocks of cells.
Fig. 4 shows an example diagrammatic cross-section along a part for 4-4 line in Fig. 2.
Fig. 5 shows the schematic diagram that is similar to an example three-dimensional storage device part in Fig. 2, and it is to solve the problem of overall bit line capacitive coupled load by the structural modification in Fig. 1.
Fig. 6 shows the schematic diagram that is similar to an example three-dimensional storage device part in Fig. 1, and it is to solve the problem of overall bit line and the load of bit line structure capacitive couplings by the structural modification in Fig. 1.
Fig. 7 shows the schematic diagram of a structure part in Fig. 6.
Fig. 8 display is along the diagrammatic cross-section of the line 8-8 in Fig. 7.
Fig. 9 is that display uses different right adjacent serial to select change-over switch to apply to read the 16 kind different groups of signal to other overall bit lines or the form of mode.
Figure 10 is the form similar with Fig. 9 but serial is wherein selected change-over switch to be not the same with Fig. 8 being adjacent but is very open and reaches the pattern that identical reading signal applies.
Figure 11 shows the alternate embodiment that another kind can solve the three-dimensional memory devices of the capacitive couplings CMBL of overall bit line and the capacitive couplings CPAD of bit line structure simultaneously.
Figure 12 shows the rough schematic view of integrated circuit according to an embodiment of the invention, and it comprises the storage unit block being commonly referred to storage array.
[main element symbol description]
10: three-dimensional memory devices
12: storage unit block
13: storage unit stratum
14: wordline
16: first direction
18: second direction
20: serial selection line
21: change-over switch is selected in serial
22: overall bit line
24,26: first and second bit line structure
28: bit line embolism
30: third direction
32: region bit line
34: source electrode line
36: odd number ground connection selects line
38: even number ground connection selects line
40: wordline
42: overall bit line pair
44: the first (even number) bit line
45: the second (odd number) bit line
175: integrated circuit
160: memory array
161,261: column decoder
162: wordline
166: line decoder
164: overall bit line
163,263: page buffer
164: overall bit line
165: bus
167: data bus
174: other circuit
169,269: programming, erasing and stratum are correlated with the state machine of read operation
168: bias voltage adjustment supply voltage
173: data input/output line
258: group's code translator
200,202,204: perpendicular connectors
210,212,214: string row selecting transistor
220,222,224: storage unit
230,232,234: contact pad
240,242,244: extension line
Embodiment
Some embodiment of the present invention, can to arrange in pairs or groups graphic being described in the chapters and sections of following embodiments, wherein only show some and and the embodiment of not all.But various embodiments of the invention can have different kenels and should not be considered as limiting the present invention; But these embodiments be provided as the requirement making the exposure of this instructions meet Patent Law.
Fig. 1 and Fig. 2 is the schematic diagram of a three-dimensional memory devices 10, and it comprises the block 12 of storage unit, does not demonstrate other storage unit.Three-dimensional memory devices 10 is the similar disclosed by " the Memory Architecture of Third Array withAlternating Memory String Orientation and string Select Structure " of the United States Patent (USP) case 13/078311 of applying for on April 1st, 2011.The block 12 of storage unit comprises in multiple storage unit stratum 13, Fig. 1 and shows 8 stratum 13.Each stratum 13 comprises multiple storage unit serial.Memory storage 10 also comprises a series of wordline 14.These wordline 14 extend abreast on a first direction 16, and storage unit serial extends in a second direction 18.Serial selection line 20 extends and selects change-over switch 21 and selected storage unit serial electric property coupling via the serial being positioned at serial terminal on first direction 16.Serial selection line 20 configuration is select change-over switch 21 lamination to be connected with serial, has a serial to select change-over switch 21, make a serial selection line 20 choose the signal wire lamination of not only in each stratum.Serial selection change-over switch 21 is normally shown in the transistor in Fig. 2.Memory storage 10 also comprises overall bit line 22, some time in icon, be denoted as metal bit line MBL, extend in second direction 18, and coupled in each stratum 13 by bit line embolism 28 with first and second bit line structure 24,26, it is called bit line pad at some time.First and second bit line structure 24,26 is at third direction 30 superimposed layer and be positioned at the two ends of storage unit block 12.Therefore, the storage unit in each stratum 13 has the first bit line structure 24 and is connected with the first end of storage unit, and second line structure 26 is connected with the second end of storage unit.As shown in FIG., 8 overall bit lines 22 are for the bit line structure 24,26 of 8 layer 13.
As shown in Figure 2, memory storage 10 also comprises region bit line 32 in storage unit block 12, and it is also extend in second direction 18.Show each overall bit line 22 in figure and there are 2 region bit line 32.The feature that memory storage 10 also comprises other extends on first direction 16, and the ground connection of such as source electrode line 34, odd number part selects the ground connection of line 36, even segments to select line 38 and wordline 40.
Fig. 3 shows the example schematic of a three-dimensional Sheffer stroke gate flash array part, and it has three layers is a representative schematic diagram that can comprise multilayered memory blocks of cells.
Comprise many wordline extension on first direction 16 abreast of wordline WLn-1, WLn, WLn+1, these wordline and column decoder 261 electric property coupling.These wordline are connected with the grid of storage unit, and its serial arrangement becomes Sheffer stroke gate serial.Wordline WLn is representational wordline.As shown in Figure 2, wordline is connected with the gate vertical of the storage unit under it in each layer plane.
Many region bit line arrange the Sheffer stroke gate serial formed in memory cell array different estate on line direction.As shown in Figure 2, array is included in the region bit line BL31 in third class, the region bit line BL21 in the second stratum, and the region bit line BL11 in the first stratum.Storage unit has dielectric charge catch structure between the wordline and region bit line of correspondence.In this illustrates, for simplicity, in each Sheffer stroke gate serial, only show three storage unit.For example, the Sheffer stroke gate serial be made up of the region bit line BL31 in third class comprises storage unit 220,222,224.In one typically application, a Sheffer stroke gate serial can comprise 16,32 an or more storage unit.
Comprise many serial selection lines and group's code translator 258 (it can be the some of the column decoder 261) electric property coupling of SSLn-1, SSLn, SSLn+1, and carry out the selection of a group of serial.These serial selection lines are connected with the grid of string row selecting transistor, and it is arranged in the first end of these storage unit Sheffer stroke gate serials.As shown in Figure 2, each serial selection line is connected with the gate vertical of string row selecting transistor in each layer plane.For example, serial selection line SSLn+1 is connected with the grid of string row selecting transistor 210,212,214 (21) respectively in three stratum's planes.
Region bit line in a specific stratum is optionally coupled with the extension line in a specific stratum by corresponding selection transistor.For example, the region bit line in third class is optionally coupled with extension line 240 by the selection transistor in this stratum.Similarly, the region bit line in the second stratum optionally couples with extension line 242, and the region bit line in the first stratum optionally couples with extension line 244.
Extension line in each stratum comprises the contact pad of a correspondence, its with and the perpendicular connectors that couples of corresponding overall bit line connect.For example, the extension line 240 in third class couples with overall bit line GBLn-1 via contact pad 230 and perpendicular connectors 200.Extension line 242 in the second stratum couples with overall bit line GBLn via contact pad 232 and perpendicular connectors 202.Extension line 244 in the first stratum couples with overall bit line GBLn+1.
Block (not shown) extra in overall bit line GBLn-1, GBLn and GBLn+1 and array couples and extends to page buffer 263.Three-dimensional decoding network can be set up in this fashion, wherein one be selected storage unit and use a wordline, all or some bit line and a serial selection line SSL to access.
Zone-block selected transistor is arranged in the second end of these storage unit Sheffer stroke gate serials.For example, zone-block selected transistor 260 is arranged in the second end of the Sheffer stroke gate serial be made up of storage unit 220,222,224.Ground connection selects line GSL to be connected with the grid of zone-block selected transistor.Ground connection selects line GSL and column decoder 261 electric property coupling to receive bias voltage when described herein the operation.
Zone-block selected transistor is used to optionally be coupled by the reference voltage on the second end of the Sheffer stroke gate serial in this block together source line CSL.This common source line CSL is to receive bias voltage when the operation described herein.When some operates, this common source line CSL is biased to the online higher reference voltage in a position compared with this Sheffer stroke gate serial opposite side, instead of as traditional " source electrode " role ground connection or closely current potential.
The shortcoming of the main bit-line load problem of some three-dimensional storage device of the device 10 of such as Fig. 1, Fig. 2 is shown in Fig. 4.That is, main bit-line load is from adjacent overall bit line and adjacent both bit line pads.Storage unit from adjacent overall bit line 22 causes overall bit line capacitive to be coupled, and is denoted as CMBL in Fig. 4, and the capacitive couplings of bit line structure (some time be called bit line pad), be denoted as CPAD in Fig. 4.Estimate that the capacitive couplings load of in the example shown in Fig. 1, Fig. 2 about 2/3 is from adjacent overall bit line 22, and the capacitive couplings load of about 1/3 is from contiguous bits line structure 24,26 (bit line pad).Coupling so can cause reading interference.
The shortcoming of the three-dimensional storage structure of conventional art is because need adjacent bit line coupling effect covered and reduce reading rate.When reading each time, need to read odd number or the overall bit line of even number.Adjacent overall bit line is then as the use of shielding.In memory construction so, the bit line of 1/4 is only had to be accessed when a read operation.
Fig. 5 shows the schematic diagram of example three-dimensional storage device 10 part, and it is used for reducing the capacitive couplings load that has and produce in Fig. 1, Fig. 2 and Fig. 4 structure and improves reading rate.The bit line of 1/2 can be had to be accessed when a read operation.Similar element then uses similar reference number.
There is the region bit line of 16 laminations in this example, so there are 16 region bit line 32, be denoted as BL0-BL15 in Figure 5.In addition have 8 layers corresponding with 8 bit line embolisms 28.First bit line structure 24 is top layer bit line structures; Show 8 top layer bit line structures in figure, every one deck has one.Each bit line embolism 28 is connected with the first bit line structure 24 at the first end of different layers.Similarly, each bit line embolism 28 is connected with second line structure 26 at the second end of different layers.
Three-dimensional storage device 10 in example shown in Fig. 5 and Fig. 1, Fig. 2 and Fig. 4 is similar, but have 16 overall bit lines instead of as shown in Figure 1, Figure 2 and Fig. 4 generally there are 8 overall bit lines.In this example, have 8 to 42 overall bit line 22.Should be noted that the series in an ad hoc structure, the overall bit line 22 of such as 8 couple 42 herein, continuous print integer the such as the 42.1st can be denoted as to, 42.2 equities.In order to reduce capacitive couplings, in every one deck, use a pair 42 overall bit lines 22.Two overall bit lines are denoted as MBL 1O (the odd number bar of metal/overall bit line 1), MBL 1E (the even number bar of metal/overall bit line 1), MBL 2O, MBL 2E etc. in the drawings, and can be called as the first bit line (even number) 44 and the second bit line (odd number) 45.This first bit line 44 is connected with the first bit line structure 24 by bit line embolism 28, and because its be denoted as SSL0, the serial switching selection switch 21 of even number of SSL2 to SSL14 is connected and is called as even number.Similarly, the second bit line 45 is connected with second line structure 26, and because its be denoted as SSL1, the serial switching selection switch 21 of odd number of SSL3 to SSL15 is connected and is called as odd number.Although this structure can solve the serious capacitive couplings CMBL problem of overall bit line, the capacitive couplings CPAD of bit line pad (bit line structure) cannot be reduced.
In order to improve reading efficiency and shield the coupling effect from adjacent bit line and adjacent both bit line pads, a kind of new three-dimensional storage structure is proposed.Three-dimensional storage device 10 in example shown in Fig. 6, Fig. 7 and Fig. 8 and Fig. 1, Fig. 2 and Fig. 4 is similar, but have 16 overall bit lines instead of as shown in Figure 1, Figure 2 and Fig. 4 generally there are 8 overall bit lines, and the capacitive couplings CMBL of overall bit line and the capacitive couplings CPAD of bit line structure can be solved simultaneously.As shown in the example in Fig. 5, each bit line is connected with second line structure 26 the overall bit line 45 of odd number of 42, and each bit line to 42 the overall bit line 44 of even number be connected with the first bit line structure 24, and the first bit line structure 24 is at identical layer with second line structure 26.But, each bit line to 42 the overall bit line 45 of odd number and the overall bit line 44 of even number by adjacent bit line to 42 a bit line separate.For example, the first bit line to 42.1 the overall bit line 45.1 of odd number and the overall bit line 44.1 of even number by the second bit line to 42.2 odd bit lines 45.2 separate; Second bit line to 42.2 the overall bit line 45.2 of odd number and the overall bit line 44.2 of even number by the first bit line to 42.1 even bitlines 44.1 separate etc.
Fig. 8 display is along the diagrammatic cross-section of the line 8-8 in Fig. 7.Suppose in this figure the second bit line to the 42.2, the 4th bit line to the 42.4, the 6th bit line to 42.6 and the 8th bit line to 42.8 quilts, roughly side by side, read abreast and access, by figure shown in dotted line.So read in parallel ability, page read mode can be imagined as, can reach and read the time very fast.Bit line can also interlock to second line structure 26 level accessed and be denoted as second line structure 26.2,26.4,26.6 and 26.8 thus.Should be noted that each bit line structure 26 can be accessed by odd number or even bitlines 45,44.But, each bit line to 42 the overall bit line 45 of odd number and the overall bit line 44 of even number by adjacent bit line to 42 a bit line separate and can help to reduce bit line coupling effect and effectively allow to be accessed in other bit line structures in each bit line structure lamination simultaneously.Similarly, other bit line structures be accessed in each bit line structure lamination allow the staggered to reduce capacitive couplings effect of bit line structure.
Fig. 9 is that display uses different right adjacent serial to select change-over switch to apply to read the 16 kind different groups of signal to other overall bit lines or the form of mode.In fig .9, R represents " reading state ", and it has electric current and flows in wire so its state is opened, and S representative " shielding status ", it does not have electric current to flow in wire so its state is closed.For example, group 1 uses the serial selection line 21 that SSL0 and SSL1 is even number and odd number; The serial selection line 21 that group 3 uses SSL2 and SSL3 to be even number and odd number; Etc..The result of group such as group 1 and the group 3 of odd number like this is identical and result that is group's example of even number is also identical, but can be contrary with the result of another kind of group.Figure 10 is the form similar with Fig. 9 but serial is wherein selected change-over switch to be not the same with Fig. 8 being adjacent but is very open and reaches the pattern that identical reading signal applies.
The form of Fig. 9 and Figure 10 is specific to be used for selecting the serial selection line SSL of row and the Logic application mode of level decoding.Different serial is used to select the right ability of change-over switch 21 to give the elasticity of the topological design of the code translator 161,166 can discussed in following Figure 12.This elasticity can by the optimal representation of helping a specific three dimensional layout.In the example of Figure 10, this decoding makes not have adjacent serial and selects SSL transistor stack to be selected in time reading in parallel.Line decoder block 166 in Figure 12 is preferably arranged to the elasticity having and allow the example serial selection line SSL in a big way of the example of Fig. 9 and Figure 10 in this way.
Figure 11 shows the alternate embodiment that another kind can solve the capacitive couplings CMBL of overall bit line and the capacitive couplings CPAD of bit line structure simultaneously.Example in fig. 11 and Fig. 6, Fig. 7 and Fig. 8's is similar, but having bit line embolism 28 directly extends downward bit line structure 24,26 and extra conductive layer 50 is positioned under overall bit line 22 to be used for as each bit line is laterally forwarded to one of two bit line embolisms 28 to 42.
In the example shown in Figure 11, a top bit line embolism 28A directly extends downward even bitlines 44.1, its with turn to extra conductive layer 50A section intersection.And a below turns to the extra conductive layer 50A section of bit line embolism 28C section low damage to be connected with the first bit line structure 24.1 directly to downward-extension.This is turned right turning to bit line embolism 28C section to the below of odd bit lines 45.2 by the lateral excursion turning to section 50A to provide.Similarly, top turns to bit line embolism 28A section, turns to section 50A and turns to bit line embolism 28C section to extend from even bitlines 44.3,44.5,44.7.A top bit line embolism 28B directly extends downward even bitlines 44.2 to be connected with the extra conductive layer 50B section aimed at.The bit line embolism 28D section direct autoregistration conductive layer 50B section of an aligned beneath is connected to downward-extension with second line structure 24.2.Similar top turns to bit line embolism 28D section, aims at section 50A and extend from even bitlines 44.4,44.6,44.8 level line embolism 28D section.Similar arrangement is aimed at and is turned to embolism structure to extend to the other end of structure from odd bit lines 45.
Arrangement in Figure 11 make use of odd/even arrangement and the advantage of bit line embolism on bit line structure intervening portion.That is, the first bit line structure 24 is extended to be diverted to the below of adjacent odd bit lines 45 at one end bit line embolism of this structure from the even bitlines 44 at interval.So allow the larger interlayer hole of use when building lower position line embolism 28C, 28D or between interlayer hole larger distance or both.Similarly, extend to second line structure 26 at the other end bit line embolism of this structure from the odd bit lines 45 at interval and obtain identical advantage to be diverted to the below of adjacent even bitlines 44.
As shown in Figure 8, its be hypothesis second bit line to the 42.2, the 4th bit line to the 42.4, the 6th bit line to the 42.6, the 8th bit line to 42.8 quilts, roughly side by side, read abreast and access, by figure shown in dotted line.But different from the example in Fig. 5, the example in Figure 11, not only reduces the capacitive couplings CMBL of overall bit line, also can reduce the capacitive couplings CPAD of bit line structure simultaneously.
Figure 12 shows the rough schematic view of integrated circuit according to an embodiment of the invention.Wherein integrated circuit 175 comprises the storage unit block 12 being commonly referred to storage array 160, and it has function described herein.As above-mentioned, an array 160 comprises multi-level storage unit.One column decoder 161 couples with many wordline 162 (14) arranged along storage array 160 (row) first direction 16.Line decoder in square 166 couples through data bus 167 and one group of page buffer 163 in this example.Overall bit line 164 (22) couples with the region bit line (not shown) that it is storage array 160 second direction 18 arranges along line direction.Address is supplied to line decoder (square 166) and column decoder (square 161) by bus 165.Data are supplied to Data In-Line 173 by other circuit 174 (this example comprises input/output end port) on integrated circuit, integrated circuit 175 can be such as general object processor or specific purposes application circuit, or block combiner is to provide the system single chip supported by memory array 160 function.Data, via DOL Data Output Line 173, are provided to other data terminals of input/output terminal or integrated circuit 175 inner/outer.
Controller used in the present embodiment is the use of state machine 169, provides control signal to control the application of the bias voltage adjustment supply voltage being produced by voltage source of supply or square 168 or provide, to carry out many operations described herein.These operations can comprise each stratum in erasing, programming and array 160 and have the relevant read operation of the stratum of different reading conditions.This controller can utilize specific purposes logical circuit and apply, as haveing the knack of known by this those skilled in the art.In alternative embodiments, this controller includes general object processor, and it can make in same integrated circuit, to perform the operation of a computer program and control device.In another embodiment, this controller is combined by specific purposes logical circuit and general object processor.
For purposes of clarity, this noun " programming " is used to the operation that expression one increases storage unit critical voltage.The data be stored in memory cells can be represented by logic " 0 " or logic " 1 ".This noun " erasing " is used to the operation that expression one reduces storage unit critical voltage.The data be stored in eraseable memory unit can by the anti-phase representative of programming state, such as logic " 1 " or logic " 0 ".In addition, multi-level cell memory can be programmed to many different critical levels, and is erased to a single the highest or minimum critical level according to design.In addition, this noun " write " is used to the operation that expression one changes storage unit critical voltage, can be used to represent programming or erasing.
Preferred embodiment of the present invention and example disclose as above in detail, but are to be appreciated that above-mentioned example is only as example, are not used to the scope limiting patent.With regard to the people knowing skill, from modifying and combination to correlation technique according to appended claims easily.
Claims (20)
1. a memory storage, comprises:
One storage unit block comprises multiple stratum, and it is rectangular that each stratum comprises multiple storage unit, and each serial comprises a serial and selects change-over switch;
First and second bit line structure is positioned at each stratum, this first and second bit line structure is positioned over the end opposite of corresponding stratum respectively, and this first bit line structure is even bit line architecture, this second line structure is odd bit lines structure, this serial of an even number serial wherein in this stratum is selected change-over switch to be arranged to this serial to be connected with this first bit line structure of this stratum, and this serial selection change-over switch of another odd number serial in this stratum is arranged to and this serial is connected with this second line structure of this stratum;
Multiple bit line pair, each bit line is to comprising one first bit line and one second bit line, each bit line connects being arranged to stratum corresponding to of the plurality of stratum, this first bit line structure in this first bit line stratum corresponding to this of a bit line pairs connects, and this second line structure in this second bit line stratum corresponding to this of a bit line pairs connects;
Wherein this bit line is to being placed to staggered mode, make this first bit line and this second bit line in each bit line pairs separate by this one of the first bit line and this second bit line in different bit line pairs.
2. memory storage according to claim 1, comprising:
Many wordline, these many wordline are arranged to chooses vertical with a plurality of storage unit serial corresponding storage unit plane in the plurality of stratum;
One first group of serial selection line is arranged to chooses serial selection change-over switch the serial of the correspondence in the plurality of storage unit serial to be connected with this first bit line structure in the plurality of stratum;
One second group of serial selection line is arranged to chooses serial selection change-over switch the serial of the correspondence in the plurality of storage unit serial to be connected with this second line structure in the plurality of stratum.
3. memory storage according to claim 2, comprising:
Decoding scheme, be arranged to a storage unit of the every one deck being chosen at parallel the plurality of stratum, choose wordline by applying signal in these many wordline, choose the first serial selection line in this first group of serial selection line, choose the second serial selection line in this second group of serial selection line and to this first bit line of the right staggered bit line pairs of the plurality of bit line and this second bit line, this staggered bit line to for odd number to or even-even.
4. memory storage according to claim 3, wherein:
This bit line to be connected with first, second, third, fourth bit line structure respectively to comprising first, second, third, fourth bit line to sequential; And
This decoding scheme be arranged to optionally choose this first and the 3rd bit line pair;
Wherein when choose this first and the 3rd bit line pair time, this second and the 4th bit line to provide between this first and the 3rd shielding between bit line pair and this second line structure provides between this first and the 3rd shielding between bit line structure, to reduce any capacitive couplings effect.
5. memory storage according to claim 3, wherein this first serial selection line chosen and this second serial selection line chosen are chosen serial for adjacent serial and are selected change-over switch.
6. memory storage according to claim 3, wherein this first serial selection line chosen and this second serial selection line chosen are that serial selection change-over switch is chosen in non-adjacent serial.
7. a memory storage, comprises:
One storage unit block comprises multiple stratum, and each stratum comprises that multiple storage unit is rectangular to be extended in the second direction between a first end and one second end of this storage unit block;
One first bit line structure is positioned at this first end of this storage unit block of each stratum, and the upper one first storage unit serial with extending from this first end of each the first bit line structure operation couples;
One second line structure is positioned at this second end of this storage unit block of each stratum, and the upper one second storage unit serial with extending from this second end of each second line structure operation couples;
Multiple bit line extends in this second direction, at least comprises first, second, third bit line pair, and each bit line is to comprising an odd bit lines and an even bitlines;
This odd bit lines is connected with this second line structure by odd bit lines connector;
This even bitlines is connected with this first bit line structure by even bitlines connector; And
Each bit line of a series of bit line pairs is separated by a bit line of adjacent bit line pairs, wherein when odd bit lines and even bitlines separate read time bit line between capacitive couplings can reduce.
8. memory storage according to claim 7, wherein:
Right this odd bit lines of this second bit line is between right this odd bit lines of this first bit line and this even bitlines;
Right this even bitlines of this first bit line is between right this odd bit lines of this second bit line and this even bitlines; And
Right this even bitlines of this second bit line is between right this even bitlines of this first bit line and right this odd bit lines of the 3rd bit line.
9. memory storage according to claim 8, this even bitlines connector of this even bitlines that this even bitlines connector of this even bitlines that wherein this first bit line is right is right with this second bit line is connected with this first bit line structure at different estate.
10. memory storage according to claim 9, wherein this different estate is adjacent stratum.
11. memory storages according to claim 8, this second line structure be wherein connected with this odd bit lines connector, this first bit line structure being and be connected with this even bitlines connector is arranged in different estate alternately, wherein when odd bit lines and even bitlines separate read time bit line structure between capacitive couplings can reduce.
12. memory storages according to claim 7, interval odd bit lines connector wherein in a series of odd bit lines connector comprises a horizontal knuckle section, and the interval even bitlines connector in a series of even bitlines connector comprises a horizontal knuckle section.
13. memory storages according to claim 7, wherein this first bit line structure and the operation of this second line structure upper by serial selection change-over switch and this first and this second storage unit serial couple.
14. 1 kinds of memory storages, comprise:
One storage unit block comprises multiple stratum, and each stratum comprises multiple storage unit serial and extends in the second direction between a first end and one second end of this storage unit block;
Bit line structure is positioned at this first end and this second end of this storage unit block of each stratum, and the operation of each line structure is upper to be coupled with a storage unit serial;
Multiple bit line extends in this second direction, at least comprises first, second, third and the 4th bit line pair of a series connection;
This bit line is to having end points, and this end points is on this first end of this storage unit block and this bit line structure of this second end;
Bit line connector on this first end of this storage unit block, with by this second and the 4th bit line pair be connected with this first bit line structure;
The right bit line connector of this second bit line has a horizontal turn-around zone and extends the right below of this first bit line; And
The right bit line connector of 4th bit line has a horizontal turn-around zone and extends the right below of the 3rd bit line.
15. memory storages according to claim 14, more comprise bit line connector in this storage unit block this second end by this first and the 3rd bit line pair be connected with this bit line structure.
16. memory storages according to claim 14, more comprise:
This second end that the right bit line connector of this first bit line is positioned at this storage unit block has a horizontal turn-around zone and extends the right below of this second bit line; And
This second end that the right bit line connector of 3rd bit line is positioned at this storage unit block has a horizontal turn-around zone and extends the right below of the 4th bit line.
17. memory storages according to claim 14, wherein this second and the right bit line connector of the 4th bit line be connected with this bit line structure at different estate.
18. 1 kinds of methods choosing region bit line in a memory storage, this region bit line comprises in the operation of one group of even number region bit line and is coupled by a first end of the first bit line structure in multiple stratum and this memory storage, and one second end of the second line structure in the plurality of stratum and this memory storage couples by one group of odd number region bit line operation, the method comprises:
Choose an even number region bit line;
Choose an odd number region bit line; And
Above-mentioned selecting step carries out in the mode that this region bit line chosen is not adjacent to each other.
19. methods according to claim 18, wherein
This even number region bit line selecting step comprises to be chosen from the even number region bit line at least one of following arrangement: BL0, BL2, BL4, BL6, BL8, BL10, BL12, BL14;
This odd number region bit line selecting step comprises to be chosen from the odd number region bit line at least one of following arrangement: BL1, BL3, BL5, BL7, BL9, BL11, BL13, BL15; And
Those region bit line arrange with following order: BL0, BL1, BL2, BL3, BL4, BL5, BL6, BL7, BL8, BL9, BL10, BL11, BL12, BL13, BL14, BL15.
20. methods according to claim 19, wherein these selecting steps choose even number region bit line BL0 and odd number region bit line BL9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210013865.2A CN103208302B (en) | 2012-01-17 | 2012-01-17 | Memory device and method for selecting regional bit line in the memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210013865.2A CN103208302B (en) | 2012-01-17 | 2012-01-17 | Memory device and method for selecting regional bit line in the memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103208302A CN103208302A (en) | 2013-07-17 |
| CN103208302B true CN103208302B (en) | 2015-07-15 |
Family
ID=48755501
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210013865.2A Active CN103208302B (en) | 2012-01-17 | 2012-01-17 | Memory device and method for selecting regional bit line in the memory device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103208302B (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105513628A (en) * | 2014-09-23 | 2016-04-20 | 北京兆易创新科技股份有限公司 | Bit line lead-out circuit in memory array and memory |
| CN105469827B (en) * | 2014-09-25 | 2019-12-31 | 旺宏电子股份有限公司 | Sensing method for flash memory and memory element thereof |
| US9530503B2 (en) * | 2015-02-19 | 2016-12-27 | Macronix International Co., Ltd. | And-type SGVC architecture for 3D NAND flash |
| KR102451156B1 (en) * | 2015-12-09 | 2022-10-06 | 삼성전자주식회사 | Semiconductor memory device having rank interleaving operation in memory module |
| TWI603460B (en) * | 2016-06-06 | 2017-10-21 | 旺宏電子股份有限公司 | Three-dimensional semiconductor device |
| JP6545649B2 (en) * | 2016-09-16 | 2019-07-17 | 東芝メモリ株式会社 | Memory device |
| JP2018148071A (en) * | 2017-03-07 | 2018-09-20 | 東芝メモリ株式会社 | Storage device |
| CN112349313B (en) * | 2020-11-30 | 2021-12-03 | 福建省晋华集成电路有限公司 | Semiconductor memory device with a plurality of memory cells |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101013598A (en) * | 2006-02-01 | 2007-08-08 | 三星电子株式会社 | Three-level nonvolatile semiconductor memory device and associated method of operation |
| CN102194821A (en) * | 2010-01-25 | 2011-09-21 | 旺宏电子股份有限公司 | Three-dimensional storing array with improved serial selection line and bit line contact distribution |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8013389B2 (en) * | 2008-11-06 | 2011-09-06 | Samsung Electronics Co., Ltd. | Three-dimensional nonvolatile memory devices having sub-divided active bars and methods of manufacturing such devices |
| KR101635504B1 (en) * | 2009-06-19 | 2016-07-04 | 삼성전자주식회사 | Program method of non-volatile memory device with three-dimentional vertical channel structure |
-
2012
- 2012-01-17 CN CN201210013865.2A patent/CN103208302B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101013598A (en) * | 2006-02-01 | 2007-08-08 | 三星电子株式会社 | Three-level nonvolatile semiconductor memory device and associated method of operation |
| CN102194821A (en) * | 2010-01-25 | 2011-09-21 | 旺宏电子股份有限公司 | Three-dimensional storing array with improved serial selection line and bit line contact distribution |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103208302A (en) | 2013-07-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103208302B (en) | Memory device and method for selecting regional bit line in the memory device | |
| US20140056072A1 (en) | 3d memory array with read bit line shielding | |
| US9911750B2 (en) | Semiconductor memory devices including asymmetric word line pads | |
| US9064576B2 (en) | Apparatuses and methods for transposing select gates | |
| CN102386188B (en) | Memory architecture of 3D array with diode in memory string | |
| CN102610260B (en) | Integrated circuit device | |
| JP4580787B2 (en) | Semiconductor memory device and method for forming the same | |
| CN102194821B (en) | Three-dimensional storing array with improved serial selection line and bit line contact distribution | |
| WO2015027233A1 (en) | Three-dimensional nand non-volatile memory devices with buried word line selectors | |
| CN102820047A (en) | Semiconductor memory device | |
| CN105762135A (en) | Stacked Metal Layers With Different Thicknesses | |
| CN105074923A (en) | Interconnections for 3d memory | |
| CN105789210B (en) | A kind of memory component and its manufacturing method | |
| CN101626023A (en) | Non-volatile memory device and method of fabricating the same | |
| CN106206593A (en) | Semiconductor storage unit including thin structure | |
| CN108630254A (en) | The non-volatile memory device of the data linear load reduced is provided | |
| CN104979002A (en) | Nonvolatile Memory Device Having Page Buffer Units Under A Cell | |
| CN108461097B (en) | Semiconductor memory device having power grid structure | |
| CN102810333B (en) | Semiconductor storage | |
| TWI489464B (en) | 3d memory array with read bit line shielding | |
| US9123396B2 (en) | Semiconductor apparatus | |
| JP3577057B2 (en) | Semiconductor storage device | |
| TWI820761B (en) | Semiconductor device | |
| JP2009302425A (en) | Semiconductor storage device | |
| US9087589B2 (en) | Flash memory device reducing layout area |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |