CN103200127B - Serial communication system and method between a kind of plate - Google Patents
Serial communication system and method between a kind of plate Download PDFInfo
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- CN103200127B CN103200127B CN201310065305.6A CN201310065305A CN103200127B CN 103200127 B CN103200127 B CN 103200127B CN 201310065305 A CN201310065305 A CN 201310065305A CN 103200127 B CN103200127 B CN 103200127B
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Abstract
Serial communication system between a kind of plate, it includes that sending module and receiver module, described sending module are connected with described receiver module signal；Described sending module includes sending data buffering module and sending data coding module, and described transmission data buffering module is connected with described transmission data coding module signal；Described receiver module includes receiving data dynamic sampling module, receiving data decoder module and receive data buffering module, described reception data dynamic sampling module is connected with described reception data decoder module signal, and described reception data decoder module is connected with described reception data buffering module by signal；Described transmission data buffering module includes buffer queue module and sends controlled state machine.The present invention designs simply, and communication reliability is high, and communication efficiency is high, without sequential pressure.
Description
Technical field
The present invention relates to a kind of serial communication system and method between plate, particularly to a kind of without with road clock
Serial communication system and method between plate.
Background technology
Current most of larger communication equipment (as transmit net equipment, wireless base station device, equipment of the core network,
Controlling apparatus of electric power system etc.) all contain the mainboard of difference in functionality, business board, dispatching board etc., each veneer
Between carry out data communication by backboard cabling.
In some scenarios, need between veneer, to carry out speed data communication faster, in order to transmit configuration or
Other data of person and the information of control.Specifically, such as transmitting in net equipment, mainboard FPGA and business
Need between plate FPGA to carry out DCN data communication.
In prior art, some employing ethernet communication modes, some employing spi bus modes, use relatively
Many is to use directly with road clock serial communication mode.In this several ways, ethernet communication mode needs
Want more backboard cabling, improve the pressure to backboard wiring；SPI communication efficiency is inadequate；And directly with
Road clock serial communication mode is high to timing requirements, and especially when service board is in different slots position, sequential can be sent out
Raw great changes, during design, communication reliability is difficult to ensure, needs to travel through various form during reliability testing
Frame and each groove position, bring complexity to design.Additionally, when source exists active and standby plate, receiving terminal may
Need to select with road clock, and then introduce gated clock, reduce further system reliability.
Therefore it is necessary to design between a plate serial communication system and method to solve drawbacks described above.
Summary of the invention
The present invention proposes a kind of serial communication system and method between plate, solves communication reliability in prior art
The highest, that design is complicated defect；The present invention designs simply, and communication reliability is high, and communication efficiency is high.
The technical scheme is that and be achieved in that:
Serial communication system between a kind of plate, it includes sending module and receiver module, described sending module and institute
State receiver module signal to connect；
Described sending module includes sending data buffering module and sending data coding module, described transmission data
Buffer module is connected with described transmission data coding module signal；
Described receiver module includes receiving data dynamic sampling module, receiving data decoder module and receive data
Buffer module, described reception data dynamic sampling module is connected with described reception data decoder module signal, institute
State reception data decoder module to be connected with described reception data buffering module by signal；
Described transmission data buffering module is used for caching transmission data, and it includes buffer queue module and sends control
State machine processed, described transmission controlled state machine is used for controlling to send data and synchronous mark field；Described transmission
Data coding module is for encoding and CRC CRC check data, and sends out serial
Data；The serial data that described reception data dynamic sampling module is used for receiving is sampled, and according to institute
State synchronous mark field and sampling phase is carried out dynamic synchronization；Described reception data decoder module is for reception
Decoding data, and carry out CRC check；Described reception data buffering module is used for caching reception data,
Data buffer storage i.e. uses after receiving queue；
Described reception data dynamic sampling module includes four sampling modules, coupling search module and Selecting phasing
Module, only needs a data lines can complete data communication between plate between described plate, described four sampling modules with
Described coupling search module signal connects, and described coupling search module is with described Selecting phasing module by signal even
Connect；The serial data received is sampled by described four sampling modules, the serial data that each bit receives
Obtaining four sampling number evidences, four sampling numbers evidences after displacement are synchronized by described coupling search module
The coupling search of attribute field, four sampling numbers evidences after coupling search are carried out by described Selecting phasing module
Select.
Further, described transmission data coding module is with described reception data dynamic sampling module by signal even
Connect.
Further, described transmission data coding module uses High-Level Data Link Control HDLC coding.
Further, described four sampling modules are connected with described transmission data coding module signal.
Serial communication method between a kind of plate, only needs a data lines can complete data between plate and leads between described plate
Letter, it comprises the steps:
(1) send data to send data coding module by transmission data buffering module；
(2) by described transmission data coding module, data are processed, data are encoded, simultaneously
Plus CRC check, changed into serial data；
(3) serial number of described transmission data coding module coding is received by receiving data dynamic sampling module
According to, transmit it to receive data decoder module；
(4) receive data dynamic sampling module and receive above-mentioned serial data, and it is sampled, according to same
Step attribute field carries out dynamic synchronization to sampling phase；The sampling clock receiving data dynamic sampling module is string
4 times of row data clock；Described reception data dynamic sampling module includes four sampling modules, coupling search
Module and Selecting phasing module, described four sampling modules are connected with described coupling search module signal, described
Coupling search module is connected with described Selecting phasing module by signal；The serial to receiving of the described four sampling modules
Data are sampled, and the serial data that each bit receives obtains four sampling number evidences, described coupling search mould
Four sampling numbers after displacement are searched for by block according to the coupling carrying out synchronous mark field, described Selecting phasing mould
Four sampling numbers evidences after coupling search are selected by block；
(5) by reception data decoder module, the serial data received is decoded, and carries out CRC school
Test；
(6) by receiving data buffering module caching reception data, data buffer storage makes for rear class in receiving queue
With.
Further, described transmission data coding module uses High-Level Data Link Control HDLC coding.
Further, state HDLC coding to force to send synchronous mark field after frame length reaches maximum.
The present invention provides between a kind of communication device board without the serial data communication method with road clock, it is possible to
Under the least encoding overhead, reliably realize data transmission by a data lines.The advantage of the method is:
1) traffic rate is high.In the situation that the clock of 4 times of serial data transmission frequency can be processed by FPGA
Under, serial data rate is up to more than 50Mbps.
2) physics cabling reduces.Carry out between the veneer of data communication, having only to a data lines and can complete data
Transmission.So can greatly alleviate backboard cabling pressure, FPGA pin resource can also be saved simultaneously,
Alleviate veneer wiring pressure.
3) without sequential pressure.Method does not has any phase at receiving terminal FPGA to receiving data as described above
Position requirement, such veneer sequential difference in different slots position on system stability without impact, more without big measuring tank
Position traversal test.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to enforcement
In example or description of the prior art, the required accompanying drawing used is briefly described, it should be apparent that, describe below
In accompanying drawing be only some embodiments of the present invention, for those of ordinary skill in the art, do not paying
On the premise of going out creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the structural representation of serial communication system between plate of the present invention；
Fig. 2 is the structural representation that the present invention receives dynamic sampling module；
Fig. 3 is the state transfer schematic diagram that the present invention sends controlled state machine；
Fig. 4 is the sampling schematic diagram that the present invention receives dynamic sampling module.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clearly
Chu, be fully described by, it is clear that described embodiment be only a part of embodiment of the present invention rather than
Whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not making creation
The every other embodiment obtained under property work premise, broadly falls into the scope of protection of the invention.
Referring to figs. 1 through Fig. 4, serial communication system 1 between a kind of plate, it includes sending module 2 and receiver module
3, described sending module 2 is connected with described receiver module 3 signal；Described sending module includes that sending data delays
Die block and transmission data coding module, described transmission data buffering module and described transmission data coding module
Signal connects；Described receiver module includes receiving data dynamic sampling module, receiving data decoder module and connect
Receiving data buffering module, described reception data dynamic sampling module is with described reception data decoder module signal even
Connecing, described reception data decoder module is connected with described reception data buffering module by signal；Described transmission data
Buffer module is used for caching transmission data, and it includes buffer queue module and sends controlled state machine, described
Send controlled state machine for controlling transmission data and synchronous mark field；Described transmission data coding module is used for
Data are encoded and CRC CRC check, and send out serial data；Described reception number
According to dynamic sampling module for the serial data received is sampled, and according to described synchronous mark field pair
Sampling phase carries out dynamic synchronization；Described reception data decoder module is used for receiving decoding data, and
Carry out CRC check；Described reception data buffering module is used for caching reception data, and data buffer storage is in receiving team
I.e. use after row.
Further, described transmission data coding module is connected with described reception data dynamic sampling module by signal.
Further, described transmission data coding module uses High-Level Data Link Control HDLC coding.
Further, described reception data dynamic sampling module include four sampling modules, coupling search module and
Selecting phasing module, described four sampling modules are connected with described coupling search module signal, and described coupling is searched
Rope module is connected with described Selecting phasing module by signal.
Further, described four sampling modules are connected with described transmission data coding module signal.
CRC i.e. CRC (Cyclic Redundancy Check): be in data communication field
Conventional a kind of error check code, is characterized in that the length of information field and check field can be arbitrarily selected.
HDLC i.e. High-Level Data Link Control (High-Level Data Link Control): be one in Synchronization Network
Transmitting data, bit-oriented data link layer protocol, it is by International Organization for Standardization (ISO) basis
SDLC (Synchronous Data Link Control) the protocol extension exploitation of IBM Corporation.
Serial communication method between a kind of plate, it comprises the steps: that (1) will by sending data buffering module
Data are transmitted to sending data coding module；(2) by described transmission data coding module to data at
Data are encoded by reason, simultaneously plus CRC check, are changed into serial data；(3) by connecing
Receive data dynamic sampling module and receive the serial data of described transmission data coding module coding, transmit it to
Receive data decoder module；(4) receive data dynamic sampling module and receive above-mentioned serial data, and it is entered
Row sampling, carries out dynamic synchronization according to synchronous mark field to sampling phase；(5) by receiving data decoding
The serial data received is decoded by module, and carries out CRC check；(6) by receiving data buffering
Module caching receive data, data buffer storage in receiving queue for rear class.
Further, serial data communication is completed by single bus between system board.Heretofore described serial
Data wire need not with road clock.
Further, described transmission data coding module uses High-Level Data Link Control HDLC coding.
Further, described HDLC coding is forced to send synchronous mark field after frame length reaches maximum.
The present invention provides a kind of source that need not to send the serial communication method with road clock, at transmitting terminal logarithm
After doing suitable coding, between veneer, only need a data lines can complete data communication between plate.In this example
Serial communication method FPGA interior-excess between plate is existing, specifically:
1) send data buffering module to be used for caching transmission data, contain buffer queue and send controlled state
Machine.Data buffer storage, among queue, sends controlled state machine and is responsible for controlling to send data and synchronous mark word
Section.
2) send data coding module to encode for data carry out specific (class HDLC coding), add simultaneously
Upper CRC check.
3) data dynamic sampling module is received, for the serial data received being sampled and according to synchronizing mark
Will field carries out dynamic synchronization to sampling phase.
4) receive data decoder module to be used for receiving decoding data, and carry out CRC check.
5) receiving data buffering module to be used for caching reception data, data buffer storage makes for rear class in receiving queue
With.
Firstly the need of explanation serial data frame format, serial data controls HDLC protocol based on High Level Link and becomes
Changing, it includes synchronous mark field F and data field D, specifically:
Synchronous mark field F: attribute field is the bit pattern of 01111110, initiateing and front in order to marker frames
The termination of one frame, attribute field can also be as filling character between frame and frame simultaneously.
Data field D: in addition to attribute field.At transmitting terminal, occur when being found to have continuous 5 " 1 "
Time, add one " 0 " behind, then proceed to the bit stream sent thereafter；At receiving terminal, when sending out continuously
After existing 5 " 1 " occurs, if its latter bit " 0 ", it is automatically deleted it, to recover original bit stream.
Data field includes check field.
Illustrate quantitatively, carry out instantiation explanation with a set of typical parameter.Definition serial data tranmitting data register
For 25MHz, speed is 25Mbps；Definition synchronous mark field largest interval is 60us.With 2 synchronizations
Between attribute field, data are a frame, and so every interframe can have up to 1500 25MHz clock cycle,
Transmittable 1500 bit data in the case of Duo.
Sending in data buffering module, data buffer storage to be sent in FIFO, is sent and controls shape by buffer queue
State machine controls transmission state.When buffer queue has data, then take Data Concurrent in FIFO and send；Work as transmission
When data encoding unit continuously transmits 1500 cycles, send controlled state machine and control to send synchronous mark by force
Field, sends the state transfer schematic diagram of controlled state machine as shown in Figure 3.
Sending the coding of data coding module complete paired data field, coded system is retouched by data field above
The mode stated.Serial bit stream is sent with clock 25MHz after coding.
Receive dynamic sampling module to complete, to sampling and the Phase synchronization receiving serial data, to realize for the present invention
Main contents.Itself particularly as follows: receiving terminal in this locality with the 100MHz of 4 times of transmitting terminal 25MHz clocks
Clock is sampled to receiving data.The most no matter receiving terminal clock phase whether with receive data syn-chronization, often
Individual bit receives data can obtain 4 sampling number evidences, as shown in Figure 4.
Analyze from sequential, these 4 sampled points must have at least 3 and stablize sampled point.Four sampling numbers
According to the coupling search carrying out sync id field F after displacement.After coupling search, four phase points are selected
Selecting, specifically chosen mode is, when continuous 3 sampled points all mate with synchronous mark word, selects second
The phase place of sampled point is as the sampling phase of this frame subsequent data.Receive data dynamic sampling lock unit structure
Figure is as shown in Figure 2.
Receiving data decoder module and complete the decoding to serial data stream, decoding process is according to data field D institute
The method described is decoded.Receive data cache module serial bit circulation is changed to byte stream, is carried out
CRC check is also stored in buffer queue.
The present invention requirement to clock frequency deviation: in above-mentioned canonical parameter instantiation illustrates, when transmitting terminal sends
Clock and receiving terminal receive clock can not homology, but both frequency deviation differences must not exceed 166.7PPM.Big in frequency deviation
Occasion can reduce synchronous mark interfield every.
The present invention provides between a kind of communication device board without the serial data communication method with road clock, it is possible to
Under the least encoding overhead, reliably realize data transmission by a data lines.The advantage of the method is:
1) traffic rate is high.In the situation that the clock of 4 times of serial data transmission frequency can be processed by FPGA
Under, serial data rate is up to more than 50Mbps.
2) physics cabling reduces.Carry out between the veneer of data communication, having only to a data lines and can complete data
Transmission.So can greatly alleviate backboard cabling pressure, FPGA pin resource can also be saved simultaneously,
Alleviate veneer wiring pressure.
3) without sequential pressure.Method does not has any phase at receiving terminal FPGA to receiving data as described above
Position requirement, such veneer sequential difference in different slots position on system stability without impact, more without big measuring tank
Position traversal test.
From technique scheme and it can be seen that between some high speeds, low cost, plate simple, reliable number
According to communication situation, the method can complete demand well.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all at this
Within bright spirit and principle, any modification, equivalent substitution and improvement etc. made, should be included in this
Within bright protection domain.
Claims (7)
1. serial communication system between a plate, it is characterised in that it includes sending module and receiver module,
Described sending module is connected with described receiver module signal；
Described sending module includes sending data buffering module and sending data coding module, described transmission data
Buffer module is connected with described transmission data coding module signal；
Described receiver module includes receiving data dynamic sampling module, receiving data decoder module and receive data
Buffer module, described reception data dynamic sampling module is connected with described reception data decoder module signal, institute
State reception data decoder module to be connected with described reception data buffering module by signal；
Described transmission data buffering module is used for caching transmission data, and it includes buffer queue module and sends control
State machine processed, described transmission controlled state machine is used for controlling to send data and synchronous mark field；Described transmission
Data coding module is for encoding and CRC CRC check data, and sends out serial
Data；The serial data that described reception data dynamic sampling module is used for receiving is sampled, and according to institute
State synchronous mark field and sampling phase is carried out dynamic synchronization；Described reception data decoder module is for reception
Decoding data, and carry out CRC check；Described reception data buffering module is used for caching reception data,
Data buffer storage i.e. uses after receiving queue；
Described reception data dynamic sampling module includes four sampling modules, coupling search module and Selecting phasing
Module, only needs a data lines can complete data communication between plate between described plate, described four sampling modules with
Described coupling search module signal connects, and described coupling search module is with described Selecting phasing module by signal even
Connect；The serial data received is sampled by described four sampling modules, the serial data that each bit receives
Obtaining four sampling number evidences, four sampling numbers evidences after displacement are synchronized by described coupling search module
The coupling search of attribute field, four sampling numbers evidences after coupling search are carried out by described Selecting phasing module
Select.
2. serial communication system between plate as claimed in claim 1, it is characterised in that described transmission data are compiled
Code module is connected with described reception data dynamic sampling module by signal.
3. serial communication system between plate as claimed in claim 2, it is characterised in that described transmission data are compiled
Code module uses High-Level Data Link Control HDLC coding.
4. serial communication system between plate as claimed in claim 1, it is characterised in that described four sampling moulds
Block is connected with described transmission data coding module signal.
5. serial communication method between a plate, it is characterised in that only need a data lines between described plate
Completing data communication between plate, it comprises the steps:
(1) send data to send data coding module by transmission data buffering module；
(2) by described transmission data coding module, data are processed, data are encoded, simultaneously
Plus CRC check, changed into serial data；
(3) serial number of described transmission data coding module coding is received by receiving data dynamic sampling module
According to, transmit it to receive data decoder module；
(4) receive data dynamic sampling module and receive above-mentioned serial data, and it is sampled, according to same
Step attribute field carries out dynamic synchronization to sampling phase；The sampling clock receiving data dynamic sampling module is string
4 times of row data clock；Described reception data dynamic sampling module includes four sampling modules, coupling search
Module and Selecting phasing module, described four sampling modules are connected with described coupling search module signal, described
Coupling search module is connected with described Selecting phasing module by signal；The serial to receiving of the described four sampling modules
Data are sampled, and the serial data that each bit receives obtains four sampling number evidences, described coupling search mould
Four sampling numbers after displacement are searched for by block according to the coupling carrying out synchronous mark field, described Selecting phasing mould
Four sampling numbers evidences after coupling search are selected by block；
(5) by reception data decoder module, the serial data received is decoded, and carries out CRC school
Test；
(6) by receiving data buffering module caching reception data, data buffer storage makes for rear class in receiving queue
With.
6. serial communication method between plate as claimed in claim 5, it is characterised in that described transmission data are compiled
Code module uses High-Level Data Link Control HDLC coding.
7. serial communication method between plate as claimed in claim 6, it is characterised in that described HDLC encodes
Force to send synchronous mark field after frame length reaches maximum.
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104378174B (en) * | 2014-10-31 | 2020-08-11 | 台州宝诚科技服务有限公司 | Communication data packet checking method based on grinder system |
| CN104767590A (en) * | 2015-04-08 | 2015-07-08 | 江苏飞尚安全监测咨询有限公司 | Reliable data transmission and control method for serial communication |
| CN105353189A (en) * | 2015-11-18 | 2016-02-24 | 李大军 | Intelligent mutual inductor capable of carrying out wireless communication |
| CN106230536B (en) * | 2016-07-12 | 2018-08-03 | 上海交通大学 | A kind of real-time Communication for Power for power electronics distributed AC servo system and synchronous transmission system |
| CN108390751B (en) * | 2018-05-02 | 2023-12-22 | 基石酷联微电子技术（北京）有限公司 | Full duplex clock data transmission system and method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2938595Y (en) * | 2006-02-20 | 2007-08-22 | 上海欣泰通信技术有限公司 | High speed series interface device for plate communication |
| CN101296066A (en) * | 2008-06-30 | 2008-10-29 | 杭州华三通信技术有限公司 | Real time clock synchronization method of distributed system, master control board and cable fastener plate |
| EP2259471A2 (en) * | 2002-10-17 | 2010-12-08 | Qualcomm Incorporated | Method and apparatus for transmitting and receiving a block of data in a communication system |
| CN102158400A (en) * | 2011-03-03 | 2011-08-17 | 北京航空航天大学 | Communication interface of space-based route switching system and space-based route switching system |
| CN102497240A (en) * | 2011-12-20 | 2012-06-13 | 北京泰美世纪科技有限公司 | Sampling synchronous device and sampling synchronous method of digital broadcasting system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102902646B (en) * | 2012-09-17 | 2015-12-09 | 大唐移动通信设备有限公司 | The loading method of board communication means and board, FPGA and system |
-
2013
- 2013-02-28 CN CN201310065305.6A patent/CN103200127B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2259471A2 (en) * | 2002-10-17 | 2010-12-08 | Qualcomm Incorporated | Method and apparatus for transmitting and receiving a block of data in a communication system |
| CN2938595Y (en) * | 2006-02-20 | 2007-08-22 | 上海欣泰通信技术有限公司 | High speed series interface device for plate communication |
| CN101296066A (en) * | 2008-06-30 | 2008-10-29 | 杭州华三通信技术有限公司 | Real time clock synchronization method of distributed system, master control board and cable fastener plate |
| CN102158400A (en) * | 2011-03-03 | 2011-08-17 | 北京航空航天大学 | Communication interface of space-based route switching system and space-based route switching system |
| CN102497240A (en) * | 2011-12-20 | 2012-06-13 | 北京泰美世纪科技有限公司 | Sampling synchronous device and sampling synchronous method of digital broadcasting system |
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Denomination of invention: Inter-plate serial communication system and inter-plate serial communication method Effective date of registration: 20191230 Granted publication date: 20160810 Pledgee: Guanggu Branch of Wuhan Rural Commercial Bank Co., Ltd. Pledgor: Wuhan Zhongruantong Technology Co., Ltd. Registration number: Y2019420000044 |
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Date of cancellation: 20210121 Granted publication date: 20160810 Pledgee: Guanggu Branch of Wuhan Rural Commercial Bank Co.,Ltd. Pledgor: WUHAN ZHONGRUANTONG TECHNOLOGY Co.,Ltd. Registration number: Y2019420000044 |