CN103186360A - Fast arithmetic multi-bit serial pulse dual-base binary finite field multiplier - Google Patents

Abstract

The invention relates to a fast arithmetic multi-bit serial pulse dual-base binary finite field multiplier, comprising an input end B, k PE modules, an FRRP module and an R3 module. The k PE modules are connected in series, the k PE modules pass through k cycles, in the first cycle, the input of A is that B is directly input, and the calculation result is restored and input into a temporary register C through the FRRP module; in the second cycle, the input of A is that B is input through the R3 module, the calculation result is also restored through the FRRP module, and is added to the calculation result of the first cycle and stored in the temporary register C; so, in the k cycle, the input of A is that B is input after passing through the R3 module for (k-1) times, the calculation result is restored through the FRRP module, added to the accumulation result of the previous (k-1) times and stored in the temporary register C, and the temporary register C outputs the result.

Description

Scale-of-two Galois field multiplier at the bottom of the first series connection pulsation of the quick computing multidigit double-basis

Technical field

The present invention relates to a kind of scale-of-two Galois field multiplier, relate in particular to scale-of-two Galois field multiplier at the bottom of a kind of quick computing multidigit unit series connection pulsation double-basis.

Background technology

In recent years, Elliptic Curve Cryptography (ECC, Elliptic curve cryptography) [1], [2] are connected with cryptographic research.Along with the appearance of Elliptic Curve Cryptography in common key cryptosystem, some hard-wired problems have been carried in the application of ECC.NIST has recommended 5 two bit fields, and GF (2 ¹⁶³), GF (2 ²³³), GF (2 ²⁸³), GF (2 ⁴⁰⁹), and GF (2 ⁵⁷¹).In the cipher protocol based on the ECC substrate, it is the requisite element that calculation level becomes that on-the-spot multiplication is arranged.The common influence area of the validity of cryptographic system hardware, energy consumption, and performance performance.

For the realization of high speed lsi (VLSI, very-large-scale integration), the heart contraction array structure is better selection.In two bit fields of expansion, multiple effective heart contraction array multiplier has been designed and can be classified as bit parallel and has been serial mechanism.Effectively bit parallel heart contraction multiplier adopts the preferential or MSB priority algorithm of LSB usually.The major advantage of bit parallel heart contraction multiplier is the connectivity in the whole computation process.Yet these structures need O (m to the polynomial expression based on two bit fields ²) XOR, O (m ²) AND, O (m ²) one latch and the delay complexity of O (m).For minimizing time and space complexity, LEE[8], [9], [13] algorithm has been showed has on-the-spot multiplication for some special polynomial expressions, a full polynomial expression for example, five polynomial expressions, three polynomial expressions, can use Toeplitz matrix-vector multiplication (TMVP, Toeplitz matrix-vector product) to remove to set up the full parallel heart contraction multiplier that is.Bit serial heart contraction array multiplier needs the space complexity of O (m), but they have caused longer computing relay.

For a compromise of time complexity and space complexity, be side by side and be that digital tandem heart contraction multiplier is disclosed between the series connection multiplier.Multiplier at the bottom of the numeral tandem conversion polynomial basis is numeral based on inside, and the outside is that the structure that walks abreast is suggested in [20].In such multiplier, the m position can be divided into again during element fields was long

The son section that individual d position is long.In each clock period, the word string of d position is calculated and the multiplication of a m position has calculated.The parallel Hunk vector matrix of an intrinsic d*d position of an extendible and systaltic multiplier use is in [15], and the delay that [16] put forward it is

The individual clock period.The multidigit unit different structure of the series connection pulsation inside and outside use of multiplier presents in the literature.The delay of these multipliers is Clock period.As previously mentioned, the design of the heart contraction Galois field multiplier of low complex degree is fixed against the selection of irreducible function and the selection of performance substrate, and these numeral series connection multipliers need high time-delay to go to realize that multiplication calculates.

Summary of the invention

The technical matters that the present invention solves is: make up scale-of-two Galois field multiplier at the bottom of a kind of quick computing multidigit unit series connection pulsation double-basis, overcoming existing multiplier needs high time-delay to go the technical matters that realizes that multiplication calculates.

Technical scheme of the present invention is: make up scale-of-two Galois field multiplier at the bottom of a kind of quick computing multidigit unit series connection pulsation double-basis, comprise input end B, k PE module, FRRP module, R3 module, described k PE module series connection, described k PE module is through k cycle, and the input of the 1st cycle A is A ₀, A ₁..., A _K-1, B directly imports, and result of calculation is input among the working storage C through described FRRP module reduction; The input A of the 2nd cycle A _k, A _K+1..., A _2k-1, B is through described R3 module input, and result of calculation also through the reduction of FRRP module, with the result of calculation addition in the 1st cycle, is kept among the working storage C; So, in k cycle, the input of A is B imports through after (k-1) inferior described R3 module, and result of calculation, is saved among the working storage C with described (k-1) inferior accumulation result addition through described FRRP module reduction, and by working storage C output result, described R3 module realizes Bx again ^KdThe calculating of modF (x), described PE module comprise R1 module, CMP module, CVP module, PWM module,

Individual XOR gate and Individual latch, described R3 module output to described R1 module and carry out the coefficient conversion by described CMP module, and the coefficient conversion that described CVP module is carried out the segmentation of A is imported in the segmentation of A, and the result of calculation of CMP module and CVP module all is input to the PWM module, realizes B _InCalculate process with A segmentation product

Individual XOR gate adds up, and the result is kept at In the individual latch, by

Latch output result

Wherein, A is by three polynomial expression F (x)=1+x ⁿ+ x ^m, be expressed as A=a ₀+ a ₁X+...+a _M-1x ^M-1, total m coefficient, i.e. (a ₀, a ₁..., a _M-1).Use the segmentation patterning method, the A of m position is cut into

Every section d position, always total k ²Therefore individual segmentation has

B can be expressed as B=b at the bottom of by double-basis ₀β ₀+ b ₁β ₁+ ...+b _M-1β _M-1, as another input of multiplier; C is the output result.

Further technical scheme of the present invention is: described FRRP module comprises FR module, R2 module, and described R2 module realizes Cmod (x ^m+ 1) calculating, the input of described FR module are the result of calculation of k series connection PE module, and the result is reduced, and output to the R2 module.

Further technical scheme of the present invention is: described CMP module comprises XOR gate XOR_1 and XOR_2, described XOR gate XOR_1 and XOR_2 parallel connection.

Further technical scheme of the present invention is: described CVP module is XOR gate XOR_3.

Further technical scheme of the present invention is: described PWM module comprise three parallel connections with door AND_1, AND_2 and AND_3.The result of described CMP module and the output of described CVP module is carried out point-to-point multiplying each other.

Further technical scheme of the present invention is: described FR module comprises XOR gate XOR_4 and the XOR_5 of two parallel connections.

Technique effect of the present invention is: make up scale-of-two Galois field multiplier at the bottom of a kind of quick computing multidigit unit series connection pulsation double-basis, comprise input end B, k PE module, FRRP module, R3 module, described k PE module series connection, described k PE module is through k cycle, and the input of the 1st cycle A is (A ₀, A ₁... A _K-1), B directly imports, and result of calculation is input among the working storage C through described FRRP module reduction; Input (the A of the 2nd cycle A _k, A _K+1..., A _2k-1), B is through described R3 module input, and result of calculation also through the reduction of FRRP module, with the result of calculation addition in the 1st cycle, is kept among the working storage C; So, in k cycle, the input of A is

B imports through after (k-1) inferior described R3 module, result of calculation, is saved among the working storage C with front (k-1) inferior accumulation result addition through described FRRP module reduction, again by working storage C output result, the present invention in conjunction with polynomial basis at the bottom of and MPB remove to set up multiplication at the bottom of the double-basis.Some have on-the-spot multiplication can access in the parallel organization in place to obtain by inferior subspace TMVP.At two bit field GF (2 ^m), undecomposable three polynomial expressions and five polynomial expressions are widely used in the password field, and are long bigger usually at such field meta.By multiplier is by using time secondary TMVP formula at the bottom of a kind of new numeral series connection new website contraction double-basis, in case the Toeplitz multiplication of a d*d has been selected, it is low-down that the structure that is suggested can be gone among the present invention

Clock period.

Description of drawings

Fig. 1 is structural representation of the present invention.

Fig. 2 is the multidigit series connection pulsation multiplier architecture figure of unit of the present invention.

Fig. 3 is the structural drawing of processing unit PE of the present invention.

Fig. 4 is the physical circuit figure of PE module of the present invention.

Embodiment

Below in conjunction with specific embodiment, technical solution of the present invention is further specified.

As shown in Figure 2, the specific embodiment of the present invention is: make up scale-of-two Galois field multiplier at the bottom of a kind of quick computing multidigit unit series connection pulsation double-basis, comprise input end B, k PE module, FRRP module, R3 module, described k PE module series connection, described k PE module is through k cycle, and the input of the 1st cycle A is A ₀, A ₁..., A _K-1, B directly imports, and result of calculation is input among the working storage C through described FRRP module reduction; The input A of the 2nd cycle A _k, A _K+1..., A _2k-1, B is through described R3 module input, and result of calculation also through the reduction of FRRP module, with the result of calculation addition in the 1st cycle, is kept among the working storage C; So, in k cycle, the input of A is

B imports through after (k-1) inferior described R3 module, and result of calculation, is saved among the working storage C with described (k-1) inferior accumulation result addition through described FRRP module reduction, and by working storage C output result, described R3 module realizes Bx again ^KdThe calculating of modF (x), described PE module comprise R1 module, CMP module, CVP module, PWM module,

Individual XOR gate and Individual latch, described R3 module output to described R1 module and carry out the coefficient conversion by described CMP module, and the coefficient conversion that described CVP module is carried out the segmentation of A is imported in the segmentation of A, and the result of calculation of CMP module and CVP module all is input to the PWM module, realizes B _InCalculate process with A segmentation product

Individual XOR gate adds up, and the result is kept at

In the individual latch, by

Latch output result

Wherein, A is by three polynomial expression F (x)=1+x ⁿ+ x ^m, be expressed as A=a ₀+ a ₁X+...+a _M-1x ^M-1, total m coefficient, i.e. (a ₀, a ₁..., a _M-1).Use the segmentation patterning method, the A of m position is cut into

Every section d position, always total k ²Therefore individual segmentation has

B can be expressed as B=b at the bottom of by double-basis ₀β ₀+ b ₁β ₁+ ...+b _M-1β _M-1, as another input of multiplier; C is the output result.

Preferred implementation of the present invention is: described FRRP module comprises FR module, R2 module, and described R2 module realizes Cmod (x ^m+ 1) calculating, the input of described FR module are the result of calculation of k series connection PE module, and the result is reduced, and output to the R2 module.

The input of CMP module and CVP module is respectively B _InWith

Its output result is as the input of PWM module, and the output of PWM module is passed through Individual XOR gate and

Individual latch, the output result

The input of R1 module is B _In, its output is through m latch, and output is B as a result _OutThe input of CMP module is Bx ^{Dk (i+1)+jd}, output is [B ^(p+q), B ( ^P+q+1)..., B ^(p+q+d-1)], the input of CVP module is A _Ik+j, output be [a _q, a _Q+1..., a _Q+d-1] ^T, wherein

Expression

Be arranged in line number and the columns of matrix, i, j=0,1 ..., k-1, the i of i representing matrix is capable, the j row of j representing matrix, p represents dk (i+1)+jd, and q represents (ik+j) d, and T represents [a _q, a _Q+1..., a _Q+d-1] transpose of a matrix.The result of its output result and a last FRRP module adds up, and outputs to next FRRP module.

The structure of having showed multiplication at the bottom of the whole double-basis at the bottom of Fig. 1 systolic arrays double-basis in the multiplier architecture, A, B, C be three at GF (2 ^m) in element, by undecomposable three polynomial expression F (x)=1+x ⁿ+ x ^mForm, wherein, n≤m/2.Elements A is represented that by the polynomial basis radix notation B and C represent that with the double-basis radix notation whole multiplier is realized C=ABmodF (x) function, and wherein A, B are as input, and C is the output result.A is by three polynomial expression F (x)=1+x ⁿ+ x ^m, be expressed as A=a ₀+ a ₁X+...+a _M-1x ^M-1, total m coefficient, i.e. (a ₀, a ₁..., a _M-1).Use the segmentation patterning method, the A of m position is cut into Every section d position, always total k ²Therefore individual segmentation has Each segmentation Ai can be expressed as A _i=a _Id+ a _Id+1X+ ... + a _Id+d-1x ^D-1, all segmentations

Replace A as the input of whole multiplier.B can be expressed as B=b at the bottom of by double-basis ₀β ₀+ b ₁β ₁+ ...+b _M-1β _M-1, as another input of multiplier.C is calculated by C=ABmodF (x) for the output result, i.e. the function of whole multiplier realization.

Because A is divided into So A can be expressed as $A=A_0+A_1{x}^d+...+A_{k^2-1}{x}^{(k^2-1)d}.$ Therefore A among the C=ABmodF (x) is launched and can obtain:

Wherein $\begin{array}{c}C=\mathrm{AB}\mathrm{mod}F\left(x\right)\\ =B(A_0+A_1{x}^d+\&CenterDot;\&CenterDot;\&CenterDot;{+A}_{k^2-1}{x}^{(k^2-1)d})\mathrm{mod}F\left(x\right)\\ =\left(B(A_0+A_1{x}^d+\&CenterDot;\&CenterDot;\&CenterDot;+A_{k-1}{x}^{(k-1)d}\right)+\\ {\mathrm{Bx}}^{\mathrm{dk}}(A_k+A_{k+1}{x}^d+\&CenterDot;\&CenterDot;\&CenterDot;+A_{2k-1}{x}^{(k-1)d})+\\ \&CenterDot;\&CenterDot;\&CenterDot;+\\ {\mathrm{Bx}}^{\mathrm{dk}(k-1)}(A_{k(k-1)}+A_{k(k-1)+1}{x}^d+\&CenterDot;\&CenterDot;\&CenterDot;+A_{k^2-1}{x}^{(k-1)d}))\mathrm{mod}F\left(x\right)\\ =({\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="130403102318.png"\; state="\{\{state\}\}">C</figure-callout>}}_0+{\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="130403102318.png,130403102327.png"\; state="\{\{state\}\}">C</figure-callout>}}_1+\&CenterDot;\&CenterDot;\&CenterDot;+C_{k-1})\mathrm{mod}F\left(x\right)\\ {\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="130403102318.png"\; state="\{\{state\}\}">C</figure-callout>}}_0=B(A_0+A_1{x}^d+\&CenterDot;\&CenterDot;\&CenterDot;+A_{k-1}{x}^{(k-1)d})\\ {\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="130403102318.png,130403102327.png"\; state="\{\{state\}\}">C</figure-callout>}}_1={\mathrm{Bx}}^{\mathrm{dk}}(A_k+A_{k+1}{x}^d+\&CenterDot;\&CenterDot;\&CenterDot;+A_{2k-1}{x}^{(k-1)d})\\ \&CenterDot;\&CenterDot;\&CenterDot;\\ C_{k-1}={\mathrm{Bx}}^{\mathrm{dk}(k-1)}(A_{k(k-1)}+A_{k(k-1+1)}{x}^d+\&CenterDot;\&CenterDot;\&CenterDot;+A_{k^2-1}{x}^{(k-1)d})\end{array}$

In the whole multiplier architecture of Fig. 1, that the 1st row calculates is C ₀=B (A ₀+ A ₁x ^d+ ... + A _K-1x ^{(k-1) d}), its 1st processing unit PE _0,0Calculate BA ₀Result of product, the 2nd processing unit PE _0,1Calculate BA ₁x ^dResult of product, by that analogy, k processing unit PE _{0, k-1}Calculate BA _K-1x ^{(k-1) d}Result of product.Whole k processing unit result of calculation adds up and finally obtains C ₀, be input to the 1st FRRP (Final Reconstruction-Reduction-Polynomial) module.That similarly, the 2nd of whole multiplier architecture the row calculates is C ₁=Bx ^Dk(A _k+ A _K+1x ^d+ ... + A _2k-1x ^{(k-1) d}), the R3 modular of increase calculates Bx ^DkModF (x), its input is B.Its 1st processing unit PE _1,0Calculate Bx ^DxA ₀Result of product, follow-up similar with the 1st row, calculate gained C as a result ₁, be input to the 2nd FRRP module, adding up with the 1st FRRP module obtains (C ₀+ C ₁) modF (x).Similar calculating is carried out in every provisional capital of whole multiplier, and to calculate k capable always, and the output result of its R3 module is Bx ^{Dk (k-1)}ModF (x), k FRRP module is input as C _K-1, be output as (C ₀+ C ₁+ ... + C _K-1) modF (x), be whole multiplier operation result C=(C ₀+ C ₁+ ... + C _K-1) modF (x).

Each processing unit PEi, the detailed circuit of j are used for calculating Bx as shown in Figure 2 ^{Dk (i+1)+jd}A _Ik+jResult of product.A _In, B _InWith

As input, B _OutWith As output.The 1st processing unit PE to every row _{I, 0}, its A _InThat import is A _Ik, B _InBe the output by i+1 R3 module, be Bx ^{Dk (i+1)}ModF (x), and

Be initialized as 0.B _OutAs the output of R1, also be the 2nd processing unit PE _{I, 1}Input, the result of output is Bx ^{Dk (i+1)+d}ModF (x).

What export is

The result, namely calculate Bx ^{Dk (i+1)}A _IkResult of product.The 2nd processing unit PE of every row _{I, 1}, its A _InThat import is A _Ik+1, B _InThat import is Bx ^{Dk (i+1)+d}ModF (x),

That import is the 1st processing unit PE _{I, 0}Result of calculation is Bx ^{Dk (i+1)}A _Ik, as the 3rd processing unit PE _{I, 1}Input

B _OutThat export is Bx ^{Dk (i+1)+2d}ModF (x) result of calculation is as the 3rd processing unit PE _{I, 1}Input B _In,

That export is Bx ^{Dk (i+1)+d}A _Ik+1Result of product.By that analogy, j+1 processing unit PE of every row _{I, j}That calculate is Bx ^{Dk (i+1)+jd}A _Ik+jResult of product, its A _InThat import is A _Ik+j, B _InThat import is Bx ^{Dk (i+1)+jd}ModF (x),

What import is j module

The output result is Bx ^{Dk (i+1)+(j-1) d}A _{Ik+ (j-1)}, B _OutThat export is Bx ^{Dk (i+1)+(j+1) d}ModF (x) result of calculation,

That export is Bx ^{Dk (i+1)+jd}A _Ik+jResult of product.

With Bx ^{Dk (i+1)+jd}And A _Ik+jLaunch respectively, i.e. Bx ^{Dk (i+1)+jd}=(b ₀β ₀+ b ₁β ₁+ ... + b _M-1β _M-1) x ^{Dk (i+1)+jd}, A _Ik+j=a _{(ik+j) d}+ a _{(ik+j) d+1}X+ ... + a _{(ik+j) d+d-1}x ^D-1 _,According to multiplication rule at the bottom of the double-basis, then can obtain:

Bx ^dk(i+1)+jdA _ik+j

=(b ₀β ₀+b ₁β ₁+…+b _m-1β _m-1)x ^dk(i+1)+jdA _ik+j

=(b ₀ ^(p)β ₀+b ₁ ^(p)β ₁+…b _m-1 ^(p)β _m-1)A _ik+j

=(a _(ik+j)d+a _(ik+j)d+1x+…+a _(ik+j)d+d-1x ^d-1)B ^(p)

=a _qB ^(p)+a _q+1xB ^(p)+…+a _q+d-1x ^d-1B ^(p)

=a _qB ^(p+q)+a _q+1B( ^p+q+1)+…+a _q+d-1B ^(p+q+d-1)

=[B ^(p+q),B ^(p+q+1),...,B ^(p+q+d-1)][a _q,a _q+1,...,a _q+d-1] ^T

p=dk(i+1)+jd

Wherein, q=(ik+j) d

B ^(p)=b ₀ ^(p)β ₀+b ₁ ^(p)β ₁+…+b _m-1 ^(p)β _m-1

Fig. 3 processing unit PE _{I, j}Detailed circuit in, the input of CMP module is Bx ^{Dk (i+1)+jd}, output is [B ^(p+q), B ^(p+q+1)..., B ^(p+q+d-1)], the input of CVP module is A _Ik+j, output be [a _q, a _Q+1..., a _Q+d-1] ^T, the PWM module is used for calculating [B ^(p+q), B ^(p+q+1)..., B ^(p+q+d-1)] [a _q, a _Q+1..., a _Q+d-1] ^TResult of product, again with

Addition, the result is input among the working storage L, exports from working storage L again The input of R1 module is B _In, realize x ^dB _InModF (x) computing, the result is saved among the working storage L, again from working storage L as B _OutOutput.

Calculating [B ^(p+q), B ^(p+q+1)..., B ^(p+q+d-1)] [a _q, a _Q+1..., a _Q+d-1] ^T, owing to be Toeplitz matrix-vector product, be divided into $\left[\begin{array}{cc}{t}_1& t_2\\ t_0& t_1\end{array}\right]\left[\begin{array}{c}{v}_0\\ {\mathrm{<figure-callout\; id="1"\; label="v"\; filenames="130403102318.png,130403102327.png"\; state="\{\{state\}\}">v</figure-callout>}}_1\end{array}\right],$ ( $\left[\begin{array}{cc}{t}_1& t_2\\ t_0& {\mathrm{<figure-callout\; id="1"\; label="t"\; filenames="130403102318.png,130403102327.png"\; state="\{\{state\}\}">t</figure-callout>}}_1\end{array}\right]$ Expression is with Toeplitz matrix [B ^(p+q), B ^(p+q+1)..., B ^(p+q+d-1)] be divided into four, wherein two is the same t that is ₁, two is t in addition ₀And t ₂, $\left[\begin{array}{c}{v}_0\\ {\mathrm{<figure-callout\; id="1"\; label="v"\; filenames="130403102318.png,130403102327.png"\; state="\{\{state\}\}">v</figure-callout>}}_1\end{array}\right]$ With vector [a _q, a _Q+1..., a _Q+d-1] ^TBe divided into two sections, T representing matrix transposition wherein can obtain

$=[B^{(p+q)},B^{(p+q+1)},...,B^{(p+q+d-1)}][a_q,a_{q+1},...,a_{q+d-1}{]}^T$

$=\left[\begin{array}{cc}{t}_1& t_2\\ t_0& t_1\end{array}\right]\left[\begin{array}{c}{v}_0\\ v_1\end{array}\right]=\left[\begin{array}{c}{t}_1(v_0+v_1)+v_1(t_2+t_1)\\ t_1(v_0+v_1)+v_0({\mathrm{<figure-callout\; id="0"\; label="t"\; filenames="130403102318.png"\; state="\{\{state\}\}">t</figure-callout>}}_0+t_1)\end{array}\right]$

$=\left[\begin{array}{c}{c}_0\\ {\mathrm{<figure-callout\; id="1"\; label="c"\; filenames="130403102318.png,130403102327.png"\; state="\{\{state\}\}">c</figure-callout>}}_1\end{array}\right]$

Fig. 4 has shown the CMP of processing unit PE, CVP and PWM physical circuit.The input of CMP module is (t ₀, t ₁, t ₂), through XOR gate XOR_1 and XOR_2, input (t ₀+ t ₁, t ₁, t ₁+ t ₂); That the CVP module is imported is (v ₀, v ₁), through XOR gate XOR_3, input (v ₀, v ₀+ v ₁, v ₁); The PWM module is that the result with the output of CMP module and CVP module carries out point-to-point multiplying each other, through 3 with door AND_1, AND_2 and AND_3, output (v ₀(t ₀+ t ₁), t ₁(v ₀+ v ₁), v ₁(t ₂+ t ₁)); The FR recovery module is utilized 2 XOR gate XOR_4 and XOR_5, calculates c ₀=t ₁(v ₀+ v ₁)+v ₁(t ₂+ t ₁) and c ₁=t ₁(v ₀+ v ₁)+v ₀(t ₀+ t ₁), output (c ₀, c ₁).

Fig. 2 has provided the multidigit unit series connection pulsation multiplier architecture that the present invention proposes, and is the structure that Fig. 1 provides to be folded obtain.Used k among Fig. 1 ²Individual arithmetic element PE, and the 26S Proteasome Structure and Function of every capable k arithmetic element PE is the same, so can substitute remaining k arithmetic element PE with k arithmetic element PE of the 1st row, needs k cycle like this.The input of the 1st cycle A is (A ₀, A ₁..., A _K-1), B directly imports, and result of calculation is input among the working storage C through the FRRP recovery module; Input (the A of the 2nd cycle A _k, A _K+1..., A _2k-1), B is through the input of R3 module, and result of calculation is also passed through the FRRP recovery module, with the result of calculation addition in the 1st cycle, is kept among the working storage C; So, know k cycle, the input of A is

B imports through after (k-1) inferior R3 module, and result of calculation, is saved among the working storage C with front (k-1) inferior accumulation result addition through the FRRP recovery module, by working storage C output result, is C=ABmodF (x) again.

Above content be in conjunction with concrete preferred implementation to further describing that the present invention does, can not assert that concrete enforcement of the present invention is confined to these explanations.For the general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, can also make some simple deduction or replace, all should be considered as belonging to protection scope of the present invention.

Claims (6)

1. scale-of-two Galois field multiplier at the bottom of the quick computing multidigit unit series connection pulsation double-basis is characterized in that, comprises input end B, kIndividual PE module, FRRP module, R3 module, described kIndividual PE module series connection, described kIndividual PE module warp kThe individual cycle, the 1st cycle AInput be

, B directly imports, and result of calculation is input to working storage through described FRRP module reduction CIn; The 2nd cycle AInput , BThrough described R3 module input, also through the reduction of FRRP module, the result of calculation addition with the 1st cycle is kept at working storage to result of calculation CIn; So, kThe individual cycle, AInput be

, BThrough ( k-1) import after the inferior described R3 module, result of calculation is through the reduction of described FRRP module, with described ( k-1) inferior accumulation result addition is saved in working storage CIn, again by working storage CThe output result, described R3 module realizes

Calculating, described PE module comprise R1 module, CMP module, CVP module, PWM module, Individual XOR gate and Individual latch, described R3 module output to described R1 module and carry out the coefficient conversion by described CMP module, and the coefficient conversion that described CVP module is carried out the segmentation of A is imported in the segmentation of A, and the result of calculation of CMP module and CVP module all is input to the PWM module, realizes

With AThe segmentation product calculates, process

Individual XOR gate adds up, and the result is kept at

In the individual latch, by

Latch output result

Wherein, ABy three polynomial expressions

, be expressed as

, total mIndividual coefficient, namely

,

Use the segmentation patterning method, will mThe position ACut into

, every section dThe position, total total k ² Therefore individual segmentation has

BBy being expressed as at the bottom of the double-basis

, as another input of multiplier; CBe the output result.

2. according to scale-of-two Galois field multiplier at the bottom of the first series connection pulsation of the described quick computing multidigit of claim 1 double-basis, it is characterized in that described FRRP module comprises FR module, R2 module, described R2 module realizes

Calculating, the input of described FR module is the result of calculation of k series connection PE module, and the result is reduced, and outputs to the R2 module.

3. according to scale-of-two Galois field multiplier at the bottom of the first series connection pulsation of the described quick computing multidigit of claim 1 double-basis, it is characterized in that described CMP module comprises XOR gate XOR_1 and XOR_2, described XOR gate XOR_1 and XOR_2 parallel connection.

4. according to scale-of-two Galois field multiplier at the bottom of the first series connection pulsation of the described quick computing multidigit of claim 1 double-basis, it is characterized in that described CVP module is XOR gate XOR_3.

5. according to scale-of-two Galois field multiplier at the bottom of the first series connection pulsation of the described quick computing multidigit of claim 1 double-basis, it is characterized in that, described PWM module comprise three parallel connections with door AND_1, AND_2 and AND_3, the result of described CMP module and the output of described CVP module is carried out point-to-point multiplying each other.

6. according to scale-of-two Galois field multiplier at the bottom of the first series connection pulsation of the described quick computing multidigit of claim 1 double-basis, it is characterized in that described FR module comprises XOR gate XOR_4 and the XOR_5 of two parallel connections.

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