CN103166648A - Low density parity check (LDPC) decoder and implementation method thereof - Google Patents

Abstract

The invention discloses a low density parity check (LDPC) decoder and an implementation method thereof. The LDPC decoder comprises an input buffer cell, a state control and address generation module, a check node processing module, a variable node processing module and a decision codon storage unit. The input buffer cell comprises an H matrix array unit, a V matrix array unit and an initial information storage unit. Storage of results of row matrix and column matrix is carried out on only 57 ransom access memory (RAM), the number of the RAM is reduced by nearly 50%, and storage space in an implementation process of the LDPC decoder is reduced. At the same time, check node operation is carried out on an arithmetic unit of 5 CNU nodes, variable node operation is carried out on an arithmetic unit of 9 VNU nodes, a needed arithmetic unit in the implementation process of the LDPC decoder is reduced, and the goal of saving chip resources is achieved.

Description

A kind of LDPC decoder and its implementation

Technical field

The present invention relates to a kind of LDPC decoder and its implementation, particularly relate to LDPC decoder and its implementation of a kind of CMMB of meeting standard.

Background technology

In Modern Communication System, error correcting code is to improve the important means of transmission reliability and power utilization, LDPC code (Low Density Parity Check Code, low density parity check code) be a class error correcting code of approaching shannon limit most at present, be widely used at present the fields such as deep space communication, optical fiber communication, satellite digital video and audio broadcasting.

At China Mobile multimedia broadcasting digital system (CMMB, china mobile multimedia broadcasting), adopted RS code (Reed-solomon codes, inner code) and the cascade of LDPC code as the error correcting code of channel.The requirement code length is 9216bit, supports 1/2,3/4 two kind of code check, and the throughput of data requires to reach 10Mbit/s.

In the CMMB system, the LDPC code is a regular LDPC code, and its H matrix column degree is all 3.The H row matrix degree of 1/2 code check is that the H row matrix degree of 6,3/4 code checks is 12.Further analysis can be found out:

In the CMMB system, the H matrix of LDPC code is to be expanded by a basic code word matrix.Can be obtained by the dual mode expansion row extended mode, row extended mode.

(1) go extended mode:

The H matrix of 1/2 code check is expanded by front 18 row exactly, and concrete extended method is: later any m of delegation is corresponding i capable (i=m%18) 0≤i≤256, and cyclic shift j (j=[m/18] * 36) 0≤j≤256 obtain to the right.% represents modulo operation.M is except 18 rounding operations in [m/18] expression.

The H matrix of 3/4 code check is expanded by front 9 row exactly, and concrete extended method is: later any m of delegation is corresponding i capable (i=m%9), and cyclic shift j (j=[m/9] * 36) obtains to the right.% represents modulo operation.M is except 9 rounding operations in [m/9] expression.

(2) row extended mode:

1/2 code check H matrix is by a 4608*36 matrix, obtains through expansion.The t row obtain to bottom offset t*18,0≤t≤256

3/4 code check H matrix is by a 2304*36 matrix, obtains through expansion.The t row obtain to bottom offset t*9,0≤t≤256

Can find out as long as memory can be preserved nonzero element each submatrix from the CMMB check matrix, and can allow these elements accurately call in needs to get final product.And the row degree of two kinds of code checks is all to be 3, and the row degree is also the multiple relation, and variable node unit fully can be multiplexing like this, and check node unit needs only the reasonable arrangement scheduling, also fully can be multiplexing.

In general, traditional LDPC decoding algorithm comprises the following steps:

Step 1, the BP on log-domain (belief-propagation, belief propagation) algorithm.For ease of arthmetic statement, at first defined following variable:

Fn is the initial log-likelihood ratio information of the initial input of n bit;

Lmn is the log-likelihood ratio information that m check-node is sent to n information node;

Zmn is the log-likelihood ratio information that n information node is sent to m check-node;

Zn is the rear log-likelihood ratio information that the n bit obtains after each interative computation;

N (m) is the set of all information nodes of being connected with m check-node;

N (m) n corresponding for removing the information node set after information node n in N (m);

M (n) is the set of all check-nodes of being connected with n information node;

M (n) m corresponding for removing the check-node set after check-node m in M (n);

The decode procedure of BP algorithm is as follows:

(1) initialization

For all n and mi ∈ M (n), make Zmin=Fn;

(2) check-node upgrades.For each check-node m and all bit node ni of being attached thereto, namely ni ∈ N (m), be handled as follows

${\mathrm{Tmn}}_i=\underset{n^{\′}\∈N\left(m\right)\backslash \mathrm{ni}}{\mathrm{\Π}}\frac{1-\exp \left(z_{{\mathrm{mn}}^{\′}}\right)}{1+\exp \left(z_{{\mathrm{mn}}^{\′}}\right)}$

${\mathrm{Lmn}}_i=\ln \frac{1-\mathrm{<figure-callout\; id="1"\; label="Tmni"\; filenames="HDA0000120116830000021.png,HDA0000120116830000022.png"\; state="\{\{state\}\}">Tmni</figure-callout>}}{1+\mathrm{Tmni}}$

(3) bit node upgrades.For each bit node n and all check-node mi of being attached thereto, namely mi ∈ M (n), be handled as follows

$Z{m}_{i}n=\mathrm{Fn}+\underset{m\&Element;M\left(n\right)\backslash \mathrm{mi}}{\mathrm{\&Sigma;}}\mathrm{Lmn}$

$\mathrm{Zn}=\mathrm{Fn}+\underset{m\&Element;M\left(n\right)}{\mathrm{\&Sigma;}}\mathrm{Lmn}$

(4) complete iteration one time, carry out hard decision, generate hard decision vector

Zn＞0 wherein,

Otherwise,

And utilize check matrix to judge following formula:

$H{\hat{x}}_n=0\mathrm{<figure-callout\; id="2"\; label="mod"\; filenames="HDA0000120116830000021.png,HDA0000120116830000022.png"\; state="\{\{state\}\}">mod</figure-callout>}2$

If set up, expression has obtained correct decode results.Decoding finishes, and x is legal-code; If be false, finish this iterative process.Repeating step 2-4 is until maximum iteration time.This formula does not satisfy all the time if iterations has surpassed the maximum iteration time that sets, and finishes this decoding, the declaration decoding failure.

Step 2, normalized minimum-sum algorithm.

In the check-node of BP algorithm (2) upgrades, carried out following simplification and processed

$L_{\mathrm{mn}}=\mathrm{\&alpha;}{(-1)}^{\stackrel{\&OverBar;}{\mathrm{\&sigma;m}\&CirclePlus;\mathrm{\&sigma;mn}}}\underset{n^{\&prime;}\&Element;N\left(m\right)\backslash n}{\min }\left|Z_{{\mathrm{mn}}^{\&prime;}}\right|$

Wherein, Zmn＞0, σ mn=1, otherwise σ mn=0;

α is normalization factor.

As seen, in the check-node renewal process, only related data is found the solution minimum value except itself, then should be worth the combined symbol position as feedback information.This shortcut calculation has reduced index, logarithmic function and has found the solution the high amount of calculation of bringing.

Usually will take advantage of the operation of α to be placed on the calculating of variable processing unit.Check-node is updated to like this:

$L_{\mathrm{mn}}={(-1)}^{\stackrel{\&OverBar;}{\mathrm{\&sigma;m}\&CirclePlus;\mathrm{\&sigma;mn}}}\underset{n^{\&prime;}\&Element;N\left(m\right)\backslash n}{\min }\left|Z_{{\mathrm{mn}}^{\&prime;}}\right|$

Variable node is updated to:

$Z{m}_{i}n=\mathrm{Fn}+\mathrm{\&alpha;}\underset{m\&Element;M\left(n\right)\backslash \mathrm{mi}}{\mathrm{\&Sigma;}}\mathrm{Lmn}$

Yet but there is following shortcoming in above-mentioned traditional LDPC decoding algorithm: (1) needs 108 block RAMs to carry out row matrix, the storage of column matrix result of calculation, and required memory space is larger; (2) because it adopts full parallel mode, therefore need the arithmetic element of 18 CNU (check-node) node, the arithmetic element of 36 VNU (variable node) node, arithmetic element used is more.

In sum, there is the problem of the larger waste resources of chip of required memory space in traditional LDPC decoding algorithm of prior art as can be known, therefore is necessary to propose improved technological means in fact, solves this problem.

Summary of the invention

The deficiency that exists for overcoming above-mentioned prior art, main purpose of the present invention is to provide a kind of LDPC decoder and its implementation, and it not only can save the memory space of chip, and satisfies simultaneously the requirement of CMMB systematic function, supports 1/2,3/4 two kind of code check.

For reaching above-mentioned and other purpose, the invention provides a kind of LDPC decoder, comprise at least:

Input buffer cell comprises H matrix array elements, V matrix array elements and initial information memory cell, after the input data after this input buffer cell reception initialization, and it is write this H matrix array elements and this initial information memory cell;

State is controlled and address generating module, the address information the processing stage of being used for realizing the control function of whole decoder and producing code check node processing module and variable node processing module;

The code check node processing module, comprise 5 code check node processing unit, under this state control and address generating module control, read the data of this H matrix array elements and complete all check-nodes to the renewal of variable node, and last time the check-node of iteration was stored in this V matrix array elements to the information of bit node;

The variable node processing module, be connected in this V matrix array elements and this initial information memory cell, it comprises 9 variable node processing units, be used for completing all variable nodes to the renewal of check-node, and the hard decision result that simultaneously current variable node is obtained in iterative process last time exports to and adjudicates the code word memory cell; And

Judgement code word memory cell is exported the information code word that decoding finishes.

Further, this LDPC decoder also comprises LMN register group and ZMN register group, and this LMN register group is used for storing check-node that this code check node processing module arithmetic completes to the information of variable node; This ZMN register group is used for variable node that this variable node processing module computing of storage completes to the information of check-node.

Further, this LDPC decoder also comprises an index table stores unit, be used for storing the index of different code checks, and after decoding was completed, the output information code word is to adjudicating the code word memory cell.

Further, working simultaneously in 5 code check node processing unit of this code check node processing module, through 4 cycles, completes the computing of 18 check-nodes, completes once all check-nodes to the renewal of variable node through 256*4 cycle.

Further, the hard decision that this code check node processing module is utilized last iteration cycle relevant variable node is substitution check matrix judgment formula as a result, obtains corresponding information and whether satisfies current verification, and when all information all satisfied the verification formula, iteration finished; When perhaps reaching maximum iteration time, decoding finishes.

Further, this code check node processing module adopts the pipelining design, and processing unit is divided into multistage stream treatment.

Further, this code check node processing module adopts 9 stage pipeline structure designs.

Further, 9 variable node processing units of this variable node processing module are completed the computing of 36 VNU nodes through 4 cycles, complete once all variable nodes to the renewal of check-node through 256*4 all after date.

Further, this variable node processing module adopts the pipelining design, and processing unit is divided into multistage stream treatment.

Further, this variable node processing module adopts 7 stage pipeline structure designs.

Further, this H matrix array elements is comprised of the RAM of 30 9 bit data width, and what its highest order was stored is last iteration decoding output, and least-significant byte is that the bit node of last iteration is to the information of check-node.

Further, this V matrix array elements is comprised of the RAM of 27 8 bit data width, 8 storages be that the check-node of this iteration is to the information of bit node.

Further, this judgement code word memory cell memory that is one 9 bit widths, 1024 degree of depth.

Further, this index table stores unit is used for storing 9216*2 concordance list, the 0-9215 storage be the index of 1/2 code check, the 9216-18431 storage be the index of 3/4 code check, after decoding is completed, according to the order of this index table stores unit, 9216 code words are rearranged.

Further, this LMN register group comprises two groups of register arrays, and each group is the register array of 27*4; This ZMN register group also comprises two groups of register arrays, and each group is the register array of 30*4.

Further, this LDPC decoder adopts the VLSI hardware structure.

Further, this state is controlled and address generating module is controlled this LDPC decoder and dispatched between idle condition, init state, check-node compute mode and variable node compute mode.

For reaching above-mentioned and other purpose, the present invention also proposes a kind of implementation method of LDPC decoder, and it comprises the steps:

System initialization, channel information write H matrix array elements and initial information memory cell;

The check-node module adopts 5 code check node processing unit to complete all check-nodes to the renewal of variable node, and last time the check-node of iteration was stored in the V matrix array elements to the information of bit node; And

The variable node processing module utilizes 9 all variable nodes of variable node processing unit to the renewal of check-node, and the hard decision result that simultaneously current variable node is obtained in iterative process last time exports judgement code word memory cell to.

Further, this check-node module and this variable node processing module adopt the pipelining design, and processing unit is divided into multistage stream treatment to carry out the renewal of check-node and variable node.

Further, the code word of last decoding judgement is exported when system initialization.

Compared with prior art, a kind of LDPC decoder of the present invention and its implementation be by only carrying out the storage of row matrix, column matrix result of calculation with 57 block RAMs, nearly reduced the quantity of 50% RAM.Reduced needed memory space in the LDPC decoder implementation procedure that meets the CMMB standard; Simultaneously, the present invention only carries out the variable node computing with the arithmetic element that the arithmetic element of 5 CNU nodes is carried out check-node computing, 9 VNU nodes, reduce needed arithmetic element in the LDPC decoder implementation procedure that meets the CMMB standard, reached the purpose of saving resources of chip.

Description of drawings

Fig. 1 is the structural representation of a kind of LDPC decoder of the present invention;

Fig. 2 is the structural representation of the preferred embodiment of a kind of LDPC decoder of the present invention;

Fig. 3 is the system state diagram that the present invention's state is controlled and address generating module 12 is controlled;

Fig. 4 and Fig. 5 be respectively under 1/2 code check with 3/4 code check under the scheduling schematic diagram of CNU stage system resource;

Fig. 6 is that the present invention's VNU arithmetic element realizes schematic diagram;

Fig. 7 is that the present invention's CNU arithmetic element realizes schematic diagram.

Embodiment

Below by specific instantiation and accompanying drawings embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by content disclosed in the present specification.The present invention also can be implemented or be used by other different instantiation, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications and change under spirit of the present invention not deviating from.

Fig. 1 is the structural representation of a kind of LDPC decoder of the present invention.As shown in Figure 1, a kind of LDPC decoder of the present invention comprises input buffer cell 11 at least, state controls and address generating module 12, code check node processing module 13, variable node processing module 14 and judgement code word memory cell 15.

Wherein input buffer cell 11 comprises H matrix array elements 16, V matrix array elements 17 and initial information memory cell 18, after input data after this input buffer cell reception initialization, it is write this H matrix array elements and this initial information memory cell; State is controlled and address generating module 12, and the address information the processing stage of being used for realizing the control function of whole decoder and producing code check node processing module and variable node processing module is namely controlled data flow, and produced CNU, the address ram in VNU stage; Code check node processing module 13 comprises 5 code check node processing unit, it is under this state control and address generating module control, obtain the data of this H matrix array elements and complete all check-nodes to the renewal of variable node, and last time the check-node of iteration was stored in this V matrix array elements to the information of bit node, simultaneously, the code check node processing module 13 hard decision substitution formula as a result that also utilizes last iteration cycle relevant variable node

Obtain corresponding information and whether satisfy current verification, when all information all satisfied the verification formula, iteration finished, and when perhaps reaching maximum iteration time, decoding finishes; Variable node processing module 14 is connected in this V matrix array elements and this initial information memory cell, it comprises 9 variable node processing units, be used for completing all variable nodes to the renewal of check-node, and the hard decision result that simultaneously current variable node is obtained in iterative process last time exports to and adjudicates the code word memory cell; Judgement code word memory cell 15 is used for the last time judgement code word of iteration variable node processing module 14 judgements of storage, with the information code word output of decoding end.

Better, the present invention's LDPC decoder also comprises LMN register group 19, ZMN register group 20 and index table stores unit 21, and wherein LMN register group 19 is used for storing check-node that 13 computings of code check node processing module complete to the information of variable node; ZMN register group 20 is used for variable node that 14 computings of storage of variables node processing module complete to the information of check-node.Index table stores unit 21 is used for storing the index of different code checks, and after decoding was completed, the output information code word was to adjudicating the code word memory cell.

Fig. 2 is the structural representation of the preferred embodiment of a kind of LDPC decoder of the present invention.The present invention's preferred embodiment is that a kind of VLSI design of LDPC decoder realizes, but the present invention is not as limit.Below will coordinate Fig. 2 to further illustrate the structure of LDPC decoder of the present invention by the present invention's preferred embodiment.As shown in Figure 2, the VLSI implementation structure of a kind of LDPC decoder of the present invention is described as follows:

(1) input buffer cell: the data of input are directly done initialization, write H matrix array 16, it is the RAM_H array, data with input are stored in initial information memory cell 18 simultaneously, be RAM_in0, RAM_in1, in RAM_in2 so that VNU (variable node processing unit) stage participate in the decoding computing;

(2) code check node processing module (CNU): formed by 5 CNU basic processing units.5 CNU work simultaneously, through 4 cycles, complete the computing of 18 CNU nodes.256*4 cycle of process completed once all check-nodes to the renewal of variable node.The hard decision that utilizes simultaneously last iteration cycle relevant variable node is substitution check matrix discrimination formula as a result, obtains corresponding information and whether satisfies current verification.When all information all satisfied the verification formula, iteration finished, and when perhaps reaching maximum iteration time, decoding finishes.At this, the check matrix discrimination formula is

Wherein Be hard decision vector;

(3) variable node processing module 14 (VNU): formed by 9 VNU basic processing units, through 4 cycles, complete the computing of 36 VNU nodes.Complete once all variable nodes to the renewal of check-node through 256*4 all after date.According to the symbol of Zn, obtain the hard decision result that current variable node obtains in this iterative process simultaneously;

(4) state is controlled and address generating module 12: the major control data flow, and produce CNU, the address ram in VNU stage;

(5) H matrix array elements 16 is single port RAM_H array, is comprised of the RAM of 30 9 bit data width.What the highest order of RAM_H was stored is last iteration decoding output, and least-significant byte is that the bit node of last iteration is to the LLR information of check-node.RAM is divided into 5 row, and 6 RAM of every row are numbered RAM No. 0-29 simultaneously.0-17 RAM is 1024 degree of depth.Every 256 degree of depth are a bank, totally 4 bank.18-29 RAM is 768 degree of depth.Every 256 degree of depth are a bank, totally 3 bank;

(6) V matrix array elements 17 is single port RAM_V array, formed by the RAM of 27 8 bit data width, 8 storages be that the check-node of this iteration is to the LLR information of bit node.RAM is divided into 9 row, and 3 RAM of every row are numbered RAM No. 0-26 simultaneously.All RAM are 1024 degree of depth.Every 256 degree of depth are a bank, and totally 4 bank, be bank0, bank1, bank2, bank3;

(7) judgement code word memory cell 15 is judgement code word RAM, and this judgement code word RAM only stores the judgement code word of current iteration VNU unit judges, is 9 bit widths, the memory of 1024 degree of depth;

(8) the index table stores unit 21: i.e. ROM_index is a ROM, is used for storing 9216*2 index table.That 0-9215 stores is the index of 1/2 code check, and that 9216-18431 stores is the index of 3/4 code check.After decoding is completed, according to the order of rom_index, 9216 code words are rearranged, then the output information code word;

(9) LMN register group 19: i.e. REG_V register group, comprise two groups of reg_v array Reg0_v, reg1_v, each is the register array of 27*4.Be used for storing check-node that the CNU computing completes to the information Lmn of variable node.Through 4 cycle, all 27 reg0_v array delegation write full.Then, reg0_v is displaced to reg1_v.At next 4 cycle, the value in reg1_v0-3 is write respectively 27 RAM_V0-26;

(10) ZMN register group 20: i.e. REG_H register group, comprise two groups of reg_H array Reg0_H, reg1_H, each is the register array of 30*4.Be used for storing variable node that the VNU computing completes to the information Zmn of check-node.Through 4 cycle, all 30 reg0_v array delegation write full.Then, reg0_h is displaced to reg1_h.At next 4 cycle, the value in reg1_h0-3 is write respectively 30 RAM_H0-26.

Fig. 3 is the system state diagram that the present invention's state is controlled and address generating module 12 is controlled.Below will coordinate the scheduling of the LDPC decoder of Fig. 3 key diagram 2.In preferred embodiment of the present invention, system mode comprises idle condition, init state, check-node compute mode and variable node compute mode, is respectively described below:

(1) idle condition (IDLE): during system reset, be in the IDLE state.When system's decoding finishes, also can get back to the IDLE state;

(2) init state: in system initialisation phase, channel information writes the RAM_H array, and the RAM in the RAM_H array is realized initialization.Under this state, the code word of last decoding judgement can be exported simultaneously;

(3) check-node computing (CNU) stage: i.e. check-node update stage.Calculate in this stage check-node arithmetic element (CNU unit).5 CNU unit calculate simultaneously.In preferred embodiment of the present invention, adopt 9 stage pipeline structure, namely, read RAM_H address (1), RAM_H data reading (1), CNU computing (2), write REG0 register group (4), the REG1 content of registers is write RAM_V matrix (1).Through 1032 cycles, complete all check-nodes and upgrade.Whether the code word of this stage verification simultaneously last iteration meets check equations.If meet, decoding finishes.In the CNU stage, each CNU unit (i) each cycle (t) reads data participation calculating in 6 RAM of RAM_H matrix (J row).Read in the order of RAM: address A is since 0, and each cycle adds 1.After calculating is completed, data are write the RAM_V matrix array.Write the order of array ram: address A from

Beginning, each cycle adds 1;

(4) variable node computing (VNU) stage, i.e. bit node update stage.Calculate in this stage variable node arithmetic element (VNU unit).9 CNU unit calculate simultaneously, in preferred embodiment of the present invention, adopt 7 stage pipeline structure, that is, read RAM_V address (1), RAM_V data reading+CNU computing (1), write REG0 register group (4), the REG1 content of registers is write RAM_H matrix (1)).Through 1030 cycles, complete all bit nodes and upgrade.This stage is adjudicated code word simultaneously, obtains the code word of this iteration.In the VNU stage, each VNU unit (j) each cycle (t) reads data participation calculating in 3 RAM of RAM_V (J row), and read in order: address A is since 0, and each cycle adds 1.After calculating was completed, the data after calculating write the RAM_H matrix array.Write the order of array ram: address A from

Beginning, each cycle adds 1.

Fig. 4 and Fig. 5 be respectively under 1/2 code check with 3/4 code check under the scheduling schematic diagram of CNU stage system resource, below will coordinate Fig. 4 and Fig. 5 to describe the CNU cell scheduling of preferred embodiment of the present invention in detail.

Under 1/2 code check, specifically dispatch as Fig. 4, the 1st CYCLE calculates 0-4, and the 2nd CYCLE calculates 5-9, and the 3rd CYCLE calculates 10-14, and the 4th CYCLE calculates 15-17.Through 4 CYCLE, all 18 elementary cells are calculated and are completed.Through 256*4 CYCLE, all 4608 check-nodes all calculate to be completed.

Under 3/4 code check, specifically dispatch as Fig. 5, the 1st CYCLE calculates 0-1, and the 2nd CYCLE calculates 2-4, and the 3rd CYCLE calculates 5-6, and the 4th CYCLE calculates 7-8.Through 4 CYCLE, all 9 elementary cells are calculated and are completed.Through 256*4 CYCLE, all 2304 check-nodes all calculate to be completed.

In addition, in preferred embodiment of the present invention, for the VNU cell scheduling, first computing CYCLE calculates 0-8, and computing CYCLE calculates 9-17 for the second time, and the 3rd computing CYCLE calculates 18-26, and computing CYCLE calculates 27-35 for the second time.Through 4 CYCLE, all 36 elementary cells are calculated and are completed.Through 256*4 CYCLE, all 9216 check-nodes all calculate to be completed.

Fig. 6 is that the present invention's VNU arithmetic element realizes schematic diagram.Below will coordinate Fig. 6 that the specific implementation of the present invention's VNU arithmetic element is described.As shown in Figure 6, P1/P2/P3 is the data of taking out from RAM, adopts pipeline organization, 9 VNU unit.The hard decision word (1BIT) that Fn_out is judged deposits output RAM in.Once deposit 9BIT, can deposit 9216 all hard decision words in through 4*256 all after date.

Fig. 7 is that the present invention's CNU arithmetic element realizes schematic diagram.Below will coordinate Fig. 7 to illustrate the realization of the present invention's CNU arithmetic element., to reduce resource as purpose this algorithm is analyzed at this, found that output numerical value only has two in fact, minimum value and sub-minimum in all input numbers.When the input data were the minimum input of the overall situation, its correspondence was output as sub-minimum, and the corresponding minimum value that is output as of other input data.Hence one can see that, obtains minimum value and the sub-minimum of all data, reaches the position of input data corresponding to minimum value, can obtain all output.

3/4 code check adopts the data of 12 inputs, 4 grades of flowing water.

1/2 code check adopts the data of 6 inputs, 3 grades of flowing water.As long as with upper figure D2_1, D2_2 ..., the data of D2_6 add a selector, if 1/2 code check is, the data of D2_n are directly obtained by the input data.

First order flowing water: compare in twos, obtain minimum value (be placed on top D1_1, D1_3 ...., D1_11), sub-minimum (be placed on following square frame D1_2, D1_4 ..., D1_12), the position L1_1～11_6 (bit wide 1bit) of minimum value.

Second level flowing water: D1_1 and D1_3 are compared, obtain minimum value D2_1, be the minimum value of Data1～Data4.The position of simultaneously, leaving minimum value with register L2_1 (bit wide 2bit).In like manner, can obtain the minimum value of Data5～Data8, and minimum value position L2_2, the minimum value of Data9～Data12, and minimum value position L2_3.

Ask the method for sub-minimum: if D1_1＜D1_3, the size of D1_2 and D1_3 relatively, general wherein smaller value delivers to D2_2.Otherwise, if if D1_1＞D1_3, the size of D1_1 and D1_4 relatively, general wherein smaller value delivers to D2_2.

Third level flowing water: D2_1 and D2_3 are compared, obtain minimum value D3_1, be the minimum value of Data1～Data8.The position of simultaneously, leaving minimum value with register L3_1 (bit wide 3bit).And the minimum value of Data9～Data12 is d2_5, and it is directly delivered to D3_3.The position of leaving minimum value with register L3_2 (bit wide 3bit).

Ask the method for sub-minimum: if D2_1＜D2_3, the size of D2_2 and D2_3 relatively, general wherein smaller value delivers to D3_2.Otherwise, if if D2_1＞D2_3, the size of D2_1 and D2_4 relatively, general wherein smaller value delivers to D3-2.

Fourth stage flowing water: D3_1 and D3_3 are compared, obtain minimum value D4_1 (MIN), be the minimum value of Data1～Data12.The position of simultaneously, leaving minimum value with register L4_1 (bit wide 4bit).

Ask the method for sub-minimum: if D3_1＜D3_3, the size of D3_2 and D3_3 relatively, general wherein smaller value delivers to D4_2.Otherwise, if D3_1＞D3_3, the size of D3_1 and D3_4 relatively, general wherein smaller value delivers to D4_2 (2nd_min).

In sum, the VLSI implementation structure of the present invention's LDPC decoder is compared with the LDPC algorithm of prior art, the present invention's advantage is mainly manifested in the following aspects:

1, memory space

The LDPC algorithm of prior art needs 108 block RAMs to carry out the storage of row matrix, column matrix result of calculation.And the present invention has only used 57 block RAMs to carry out the storage of row matrix, column matrix result of calculation.Nearly reduced the quantity of 50% RAM.Therefore, the present invention has reduced needed memory space in the LDPC decoder implementation procedure that meets the CMMB standard.

2, arithmetic element

The LDPC algorithm of prior art adopts full parallel mode, needs the arithmetic element of 18 CNU nodes, the arithmetic element of 36 VNU nodes.The present invention has only used the arithmetic element of 5 CNU nodes, the arithmetic element of 9 VNU nodes.Therefore, the present invention has reduced needed arithmetic element in the LDPC decoder implementation procedure that meets the CMMB standard.

Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not is used for restriction the present invention.Any those skilled in the art all can under spirit of the present invention and category, modify and change above-described embodiment.Therefore, the scope of the present invention should be as listed in claims.

Claims (20)

1. LDPC decoder comprises at least:

Input buffer cell comprises H matrix array elements, V matrix array elements and initial information memory cell, after the input data after this input buffer cell reception initialization, and it is write this H matrix array elements and this initial information memory cell;

State is controlled and address generating module, the address information the processing stage of being used for realizing the control function of whole decoder and producing code check node processing module and variable node processing module;

The code check node processing module, comprise 5 code check node processing unit, under this state control and address generating module control, read the data of this H matrix array elements and complete all check-nodes to the renewal of variable node, and last time the check-node of iteration was stored in this V matrix array elements to the information of bit node;

The variable node processing module, be connected in this V matrix array elements and this initial information memory cell, it comprises 9 variable node processing units, be used for completing all variable nodes to the renewal of check-node, and the hard decision result that simultaneously current variable node is obtained in iterative process last time exports to and adjudicates the code word memory cell; And

Judgement code word memory cell is exported the information code word that decoding finishes.

2. LDPC decoder as claimed in claim 1, it is characterized in that: this LDPC decoder also comprises LMN register group and ZMN register group, and this LMN register group is used for storing check-node that this code check node processing module arithmetic completes to the information of variable node; This ZMN register group is used for variable node that this variable node processing module computing of storage completes to the information of check-node.

3. LDPC decoder as claimed in claim 2 is characterized in that: this LDPC decoder also comprises an index table stores unit, be used for storing the index of different code checks, and after decoding was completed, the output information code word is to adjudicating the code word memory cell.

4. LDPC decoder as claimed in claim 1, it is characterized in that: work simultaneously in 5 code check node processing unit of this code check node processing module, through 4 cycles, complete the computing of 18 check-nodes, 256*4 cycle of process completed once all check-nodes to the renewal of variable node.

5. LDPC decoder as claimed in claim 4, it is characterized in that: the hard decision that this code check node processing module is utilized last iteration cycle relevant variable node is substitution check matrix judgment formula as a result, obtain corresponding information and whether satisfy current verification, when all information all satisfied the verification formula, iteration finished; When perhaps reaching maximum iteration time, decoding finishes.

6. LDPC decoder as claimed in claim 5 is characterized in that: this code check node processing module adopts pipelining design, and processing unit is divided into multistage stream treatment.

7. LDPC decoder as claimed in claim 6, is characterized in that: these code check node processing module employing 9 stage pipeline structure designs.

8. LDPC decoder as claimed in claim 1, it is characterized in that: 9 variable node processing units of this variable node processing module are through 4 cycles, complete the computing of 36 VNU nodes, complete once all variable nodes to the renewal of check-node through 256*4 all after date.

9. LDPC decoder as claimed in claim 8 is characterized in that: this variable node processing module adopts pipelining design, and processing unit is divided into multistage stream treatment.

10. LDPC decoder as claimed in claim 9, is characterized in that: these variable node processing module employing 7 stage pipeline structure designs.

11. LDPC decoder as claimed in claim 1, it is characterized in that: this H matrix array elements is comprised of the RAM of 30 9 bit data width, what its highest order was stored is last iteration decoding output, and least-significant byte is that the bit node of last iteration is to the information of check-node.

12. LDPC decoder as claimed in claim 1 is characterized in that: this V matrix array elements is comprised of the RAM of 27 8 bit data width, 8 storages be that the check-node of this iteration is to the information of bit node.

13. LDPC decoder as claimed in claim 1 is characterized in that: this judgement code word memory cell is the memory of one 9 bit widths, 1024 degree of depth.

14. LDPC decoder as claimed in claim 3, it is characterized in that: this index table stores unit is used for storing 9216*2 concordance list, what 0-9215 stored is the index of 1/2 code check, what 9216-18431 stored is the index of 3/4 code check, after decoding is completed, according to the order of this index table stores unit, 9216 code words are rearranged.

15. LDPC decoder as claimed in claim 2 is characterized in that: this LMN register group comprises two groups of register arrays, and each group is the register array of 27*4; This ZMN register group also comprises two groups of register arrays, and each group is the register array of 30*4.

16. LDPC decoder as claimed in claim 2 is characterized in that: this LDPC decoder adopts the VLSI hardware structure.

17. LDPC decoder as claimed in claim 2 is characterized in that: this state control and address generating module are controlled this LDPC decoder dispatches between idle condition, init state, check-node compute mode and variable node compute mode.

18. the implementation method of a LDPC decoder comprises the steps:

System initialization, channel information write H matrix array elements and initial information memory cell;

The check-node module adopts 5 code check node processing unit to complete all check-nodes to the renewal of variable node, and last time the check-node of iteration was stored in the V matrix array elements to the information of bit node; And

The variable node processing module utilizes 9 all variable nodes of variable node processing unit to the renewal of check-node, and the hard decision result that simultaneously current variable node is obtained in iterative process last time exports judgement code word memory cell to.

19. the implementation method of LDPC decoder as claimed in claim 18, it is characterized in that: this check-node module and this variable node processing module adopt the pipelining design, and processing unit is divided into multistage stream treatment to carry out the renewal of check-node and variable node.

20. the implementation method of LDPC decoder as claimed in claim 18 is characterized in that: in the time of system initialization, the code word of last decoding judgement is exported.

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