CN103152062B - Generation method of real-time signal and device - Google Patents

Abstract

The invention discloses a generation method of a real-time signal and a device. The method includes that a base band signal data point is read by each work clock of a signal processor. Each read base band signal data point is parallely divided into an n-way base band signal. N data points of a low frequency sine signal and a low frequency cosine signal with the sampling frequency of the work clock are respectively produced by the signal processor. An n-way base band and an n-way low frequency signal are modulated in an orthogonal mode by the signal processor. An n-way modulating signal is stored in the buffer according to a timing sequence after the parallel n-way modulating signal is obtained. A group of n-way modulating signals outputs are read by each work clock according to the principle of first in-first out. According to the scheme of the generation method of the real-time signal and the device, hardware equipment cost of a signal producing system is reduced. The fact that a high frequency signal which is not produced by the present processor according to the Nyquist law is produced in real time is achieved.

Description

A kind of generation method and device of live signal

Technical field

The present invention relates to Digital Signal Processing and software wireless electrical domain, relate in particular to a kind of live signal generation method and device.

Background technology

Along with the communication technology constantly changes from simulation-to-digitalization, the more and more software radio equipment that uses of modern signal generation system is realized, and a large amount of signal of software radio equipment is processed and all realized in numeric field by high performance processor.At present, use the signal creating method of digital processing unit to mainly contain two kinds, one is at signal highest frequency hour, completes the generation of live signal with the processor that meets Nyquist law, and the work clock of processor is greater than 2 times of signal highest frequency.One is in the time that signal highest frequency is larger, on low rate processor, by pre-stored the waveform of signal, carry out settling signal generate by the mode of quick broadcasting.

When using first method to generate when signal, signal frequency is higher, requires the work clock of signal processor higher, and price is also higher simultaneously, and unrestrictedly height of signal processor work clock on market.In the time using second method to generate signal, requiring, in multiple signals parallel generation situation, will to produce very large time delay, cannot meet real-time response requirement.

It is that the baseband signal of certain bandwidth is generated near bandwidth signal upper frequency by quadrature modulation that conventional live signal generates, and modulated carrier frequency is far longer than signal bandwidth.Due to the DDS(Direct Digital Synthesizer of signal processor) unit generate local frequency can only be less than 1/2nd of work clock, therefore along with the increase of carrier frequency, can greatly increase processor cost, and the raw signal of highest frequency higher than work clock that do not become.

Summary of the invention

In view of the above problems, the present invention has been proposed to a kind of overcome the problems referred to above or the live signal generation method addressing the above problem at least in part and device are provided.

According to one aspect of the present invention, a kind of live signal generation method is provided, comprising:

The each work clock of signal processor reads the data point of a baseband signal taking work clock as sample rate, and by parallel the each baseband signal data point the reading n roadbed band signal data that are divided into;

The each work clock of signal processor can form the data point of a carrier signal and the Low Frequency Sine Signals taking work clock as sample rate and the data point of low frequency cosine signal after generating respectively n combination; Wherein, the frequency f of each road low frequency signal data point _z'=f _z-kf _o' 2, in formula, k gets and meets 0≤f _z'≤f _o' 2 positive integer, f _o' be work clock, f _zfor the value of setting is greater than the centre frequency of the signal to be generated of signal processor maximum functional clock, wherein, in the time that the value of k is odd number, n taking work clock as sample rate Low Frequency Sine Signals data point and n low frequency cosine signal data point need to, every a work clock, be done sign-inverted one time;

Described n roadbed band signal and n Low Frequency Sine Signals data point, a n low frequency cosine signal data point are carried out quadrature modulation by signal processor, obtain after parallel n road modulation signal, deposit chronologically described n road modulation signal in buffer memory, and according to first-in first-out principle, each work clock reads one group of n road modulation signal output.

Further, in the method for the invention, according to signal bandwidth, work clock and along separate routes number n generate prototype FIR filter, and prototype FIR filter is divided into n branching filter, the FIR of first branch filter is from first value of prototype FIR filter, get a value every n point, until ending, in like manner n branching filter starts value from n value of prototype filter, get one every n value, until ending.Described signal processor utilizes the FIR of branch filter, read a baseband signal data point at each work clock, use respectively n the FIR of branch filter to be divided into n way strong point by parallel the each described baseband signal data point reading, thereby complete the parallel baseband signal of n road taking work clock as sample rate that be divided into of the baseband signal of Jiang Yi road taking work clock as sample rate.

Wherein, prototype FIR filter is low pass filter, and need meet sample rate is nf _o', cut-off frequecy of passband is more than or equal to baseband signal bandwidth, is less than or equal to work clock.

Further, in the method for the invention, described signal processor is followed successively by θ, 2 π f by the first phase of n Low Frequency Sine Signals data point is set _z/ nf _o'+θ ..., 2 π (n-1) f _z/ nf _o'+θ, realizes a sinusoidal pattern carrier signal of n the rear formation of Low Frequency Sine Signals data point combination; By being set, the first phase of n low frequency cosine signal data point is followed successively by θ, 2 π f _z/ nf _o'+θ ..., 2 π (n-1) f _z/ nf _o'+θ, realizes a longitudinal cosine type carrier signal of n the rear formation of low frequency cosine signal data point combination; Wherein, θ is freely worth.

Further, in the method for the invention, described signal processor is f by the frequency that n DDS is set _z', first phase is respectively 2 π (i-1) f _z/ nf _o'+θ, i=1,2 ..., n, realizes in the time that each work clock arrives, and utilizes n DDS to generate respectively the individual Low Frequency Sine Signals data point taking work clock as sample rate of n and the data point of low frequency cosine signal.

According to another aspect of the present invention, a kind of live signal generating apparatus is provided, comprising:

The parallel processing unit along separate routes of baseband signal, reads the data point of a baseband signal taking work clock as sample rate, and the each baseband signal data point reading is walked abreast and is divided into n roadbed band signal data for each work clock;

Carrier signal parallel generation unit can form a carrier signal and the data point of the low frequency sinusoidal signal taking work clock as sample rate and the data point of low frequency cosine signal after generating respectively n combination; Wherein, the frequency f of each low frequency signal data point _z'=f _z-kf _o' 2, in formula, k gets and meets 0≤f _z'≤f _o' 2 positive integer, f _o' be work clock, f _zfor set value be greater than the centre frequency of the signal to be generated of signal processor maximum functional clock, wherein, in the time that the value of k is odd number, n taking work clock as sample rate Low Frequency Sine Signals data point and n low frequency cosine signal data point need to, every a work clock, be done sign-inverted one time;

Signal modulating unit, for described n roadbed band signal and n Low Frequency Sine Signals data point, a n low frequency cosine signal data point are carried out to quadrature modulation, obtains parallel n road modulation signal;

Signal buffer unit, for depositing chronologically described n road modulation signal in buffer memory, and according to first-in first-out principle, each work clock reads one group of n road modulation signal output.

Further, in signal processor of the present invention, the parallel processing unit along separate routes of described baseband signal, specifically comprises:

Filter arranges subelement, and for according to the signal bandwidth of the signal to be generated of work clock, along separate routes number n and setting, generation sample rate is nf _o', cut-off frequecy of passband is more than or equal to the prototype FIR filter that baseband signal bandwidth is less than or equal to work clock, and described prototype FIR filter is divided into n branching filter; Wherein, i the FIR of branch filter, from i value of prototype FIR filter, got a value every n point, until ending, i=1,2 ..., n;

Subelement is processed in parallel shunt, for utilizing the FIR of branch filter, reads a baseband signal data point at each work clock, uses respectively n the FIR of branch filter by parallel the each described baseband signal data point the reading n roadbed band signal data point that is divided into.

Further, in signal processor of the present invention, described carrier signal parallel generation unit is followed successively by θ, 2 π f by the first phase of n Low Frequency Sine Signals data point is set _z/ nf _o'+θ ..., 2 π (n-1) f _z/ nf _o'+θ, realizes a sinusoidal pattern carrier signal of n the rear formation of Low Frequency Sine Signals data point combination; By being set, the first phase of n low frequency cosine signal data point is followed successively by θ, 2 π f _z/ nf _o'+θ ..., 2 π (n-1) f _z/ nf _o'+θ, realizes a longitudinal cosine type carrier signal of n the rear formation of low frequency cosine signal data point combination; Wherein, θ is freely worth.

Further, in signal processor of the present invention, described carrier signal parallel generation unit, is f specifically for the frequency that n DDS is set _z', first phase is respectively 2 π (i-1) f _z/ nf _o'+θ, i=1,2 ..., n, and in the time that each work clock arrives, generates respectively n Low Frequency Sine Signals data point taking work clock as sample rate and the data point of low frequency cosine signal.

Beneficial effect of the present invention is as follows:

The method of the invention and device, realize and utilized n low frequency sine and cosine signal combination producing high-frequency carrier signal, realize under lower working clock frequency, complete the generative process of higher frequency signals, not only reduce the hardware device cost of signal generating system, but also realized the high-frequency signal that the current processor of real-time generation does not become according to the life of Nyquist law.

Brief description of the drawings

In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.

The flow chart of the live signal generation method that Fig. 1 provides for the embodiment of the present invention;

The flow chart of the another live signal generation method that Fig. 2 provides for the embodiment of the present invention;

The structural representation of the signal processor that Fig. 3 provides for the embodiment of the present invention.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiment.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.

High in order to solve in prior art the required hardware cost of live signal generating mode, and cannot generate the problem of highest frequency higher than the signal of work clock, the embodiment of the present invention provides a kind of live signal generation method and device, it is by parallel account form along separate routes, use the sine of n lower frequency and the carrier signal of cosine signal combination producing upper frequency, and baseband signal and carrier signal are completed to quadrature modulation in low clock frequency, well realize with low frequency work clock processor generation high-frequency signal.Just by several specific embodiments, technical scheme of the present invention is elaborated below.

Embodiment mono-

As shown in Figure 1, the embodiment of the present invention provides a kind of live signal generation method, comprising:

Step S101, the each work clock of signal processor reads the data point of a baseband signal taking work clock as sample rate, and by parallel the each baseband signal data point the reading n roadbed band signal data that are divided into;

In this step, the work clock f of signal processor _o' meet following condition: f _o'≤f _oand f _s=nf _o', f in formula _ofor the maximum functional clock frequency of signal processor, f _sfor the speed of signal processor output signal;

Preferably, the implementation of this step is as follows:

According to signal bandwidth, work clock and along separate routes number n generate prototype FIR filter, prototype FIR filter is divided into n branching filter, the FIR of first branch filter is from first value of prototype FIR filter, get a value every n point, until ending, in like manner n branching filter starts value from n value of prototype filter, get one every n value, until ending.Described signal processor utilizes the FIR of branch filter, read a baseband signal data point at each work clock, use respectively n the FIR of branch filter to be divided into n way strong point by parallel the each described baseband signal data point reading, thereby complete the parallel baseband signal of n road taking work clock as sample rate that be divided into of the baseband signal of Jiang Yi road taking work clock as sample rate.

Wherein, prototype FIR filter is low pass filter, and need meet sample rate is nf _o', cut-off frequecy of passband is more than or equal to baseband signal bandwidth, is less than or equal to work clock.

Certainly, those skilled in the art also can utilize existing other parallel modes along separate routes to carry out shunt and process, and about parallel mode along separate routes, the present invention does not do unique restriction.

Step S102, the each work clock of signal processor can form the data point of a carrier signal and the Low Frequency Sine Signals taking work clock as sample rate and the data point of low frequency cosine signal after generating respectively n combination;

Wherein, the frequency f of each low frequency signal data point _z'=f _z-kf _o' 2, in formula, k gets and meets 0≤f _z'≤f _o' 2 positive integer, f _o' be work clock, f _zfor the value of setting is greater than the centre frequency of the signal to be generated of signal processor maximum functional clock, wherein, in the time that the value of k is odd number, n taking work clock as sample rate Low Frequency Sine Signals data point and n low frequency cosine signal data point need to, every a work clock, be done sign-inverted one time.

Preferably, in this step, described signal processor is followed successively by θ, 2 π f by the first phase of n Low Frequency Sine Signals data point is set _z/ nf _o'+θ ..., 2 π (n-1) f _z/ nf _o'+θ, realizes a sinusoidal pattern carrier signal of n the rear formation of Low Frequency Sine Signals data point combination; By being set, the first phase of n low frequency cosine signal data point is followed successively by θ, 2 π f _z/ nf _o'+θ ..., 2 π (n-1) f _z/ nf _o'+θ, realizes a longitudinal cosine type carrier signal of n the rear formation of low frequency cosine signal data point combination; Wherein, θ is freely worth.

Preferably, the specific implementation of this step is: the frequency that described signal processor arranges n DDS is f _z', first phase is respectively 2 π (i-1) f _z/ nf _o'+θ, i=1,2 ..., n, and in the time that each work clock arrives, utilizes n DDS to generate respectively the individual Low Frequency Sine Signals data point taking work clock as sample rate of n and the data point of low frequency cosine signal.

It should be noted that, in this step, low frequency is with respect to centre frequency f _z.

Step S103, described n roadbed band signal and n Low Frequency Sine Signals data point, a n low frequency cosine signal data point are carried out quadrature modulation by signal processor, obtain after parallel n road modulation signal, deposit chronologically described n road modulation signal in buffer memory, and according to first-in first-out principle, each work clock reads one group of n road modulation signal output.

Embodiment bis-

The embodiment of the present invention provides a kind of live signal generation method, identical with square ratio juris described in embodiment mono-, and it is in conjunction with concrete implementation detail further elaborating method described in embodiment mono-.

In the present embodiment, the maximum functional clock frequency of supposing signal processor is f _o, the bandwidth that generate signal is B _s, centre frequency is f _z, meet f _z> > B _s, f _o> > B _s, and f _z>f _o.

Concrete, the present embodiment provides a kind of live signal generation method, and as shown in Figure 2, described method specifically comprises the steps: the signal product process schematic diagram of the method

Steps A: baseband signal is done to parallel processing along separate routes, obtain n roadbed band signal;

Step B: generate n Low Frequency Sine Signals data point and cosine signal data point, generate high-frequency carrier signal in order to subsequent combination;

Step C: modulating baseband signal output on parallel basis along separate routes.

About steps A, specific implementation process is as follows:

Steps A 1: according to the work clock of equipment index signalization processor.

Generate equipment index according to signal, determine the speed f of signal from the FIFO buffer unit input D/A processor of signal processor _s, need to meet: f _s>2f _zthereby, the work clock f of definite signal processor _o', meet f _o'≤f _o, and, f _s=nf _o', n is positive integer.

Steps A 2: prototype FIR filter.

Generate prototype low-pass FIR filter: meet passband interior decay is not more than 0.1dB, stopband interior decay is not less than 60dB, the length that wherein l is filter.

Steps A 3: by the parallel baseband signal n road signal that is divided into.

Prototype low-pass FIR filter is divided into n the FIR of branch filter

Raw baseband signal is shown in Fig. 2, every through a clock, once, the each FIR of branch filter reads a baseband signal to buffer shifts simultaneously, produces n new data.Corresponding to each input baseband signal s _in(i), an equal parallel output n data:

Input successively baseband signal according to said process just can complete the parallel n roadbed band signal that is divided into of a roadbed band signal

About step B, specific implementation process is as follows:

Due to base band signal process and the same signal processor of carrier signal generation use, the working clock frequency of the each unit of signal processor is consistent, and therefore carrier signal is used n road signal combination to represent equally.If longitudinal cosine type carrier signal is intuitively used to n road signal indication:

$\left[\begin{array}{c}{\mathrm{sig}}_{I_1}\left(i\right)=\cos (2\mathrm{\π}{f}_z\mathrm{ni}/f_s+\mathrm{\θ})=\cos (2\mathrm{\π}{f}_{z}i/{f_o}^{\′}+\mathrm{\θ})\\ \mathrm{si}{g}_{I_2}\left(i\right)=\cos (2\mathrm{\π}{f}_z\mathrm{ni}/f_s+2\mathrm{\π}{f}_z/f_s+\mathrm{\θ})=\cos (2\mathrm{\π}{f}_{z}i/{f_o}^{\′}+2\mathrm{\π}{f}_z/{{\mathrm{nf}}_o}^{\′}+\mathrm{\θ})\\ ......\\ {\mathrm{sig}}_{I_n}=\cos (2\mathrm{\π}{f}_z\mathrm{ni}/f_s+2\mathrm{\π}{f}_z(n-1)n/f_s+\mathrm{\θ})=\cos (2\mathrm{\π}{f}_{z}i/{f_o}^{\′}+2\mathrm{\π}{f}_z(n-1)/{{\mathrm{nf}}_o}^{\′}+\mathrm{\θ})\end{array}\right]$

Due to f _z>f _o', utilize the signal processor of work on hand clock frequency to complete, so need to be to f _zconvert order k is positive integer, and wherein the value of k meets:

In the time that k is odd number:

$\left\{\begin{array}{c}{\mathrm{sig}}_{I_1}\left(i\right)={(-1)}^i\·\cos (2\mathrm{\π}{f_z}^{\′}i/{f_o}^{\′}+\mathrm{\θ})\\ {\mathrm{sig}}_{I_2}\left(i\right)={(-1)}^i\·\cos (2\mathrm{\π}{f_z}^{\′}i/{f_o}^{\′}+2\mathrm{\π}{f}_z/{{\mathrm{nf}}_o}^{\′}+\mathrm{\θ})\\ ......\\ {\mathrm{sig}}_{I_n}\left(i\right)={(-1)}^i\·\cos (2\mathrm{\π}{f_z}^{\′}i/{f_o}^{\′}+2\mathrm{\π}{f}_z(n-1)/{{\mathrm{nf}}_o}^{\′}+\mathrm{\θ})\end{array}\right.$

In the time that k is even number:

$\left\{\begin{array}{c}{\mathrm{sig}}_{I_1}\left(i\right)=\cos (2\mathrm{\π}{f_z}^{\′}i/{f_o}^{\′}+\mathrm{\θ})\\ {\mathrm{sig}}_{I_2}\left(i\right)=\cos (2\mathrm{\π}{f_z}^{\′}i/{f_o}^{\′}+2\mathrm{\π}{f}_z/{{\mathrm{nf}}_o}^{\′}+\mathrm{\θ})\\ ......\\ {\mathrm{sig}}_{I_n}\left(i\right)=\cos (2\mathrm{\π}{f_z}^{\′}i/{f_o}^{\′}+2\mathrm{\π}{f}_z(n-1)/{{\mathrm{nf}}_o}^{\′}+\mathrm{\θ})\end{array}\right.$

By above-mentioned formula, can find out, when frequency of utilization is f _z', the first phase of n road signal is respectively the cosine signal combination of (wherein θ is freely worth), just can complete the generation of longitudinal cosine type carrier signal, wherein, can find out from above-mentioned formula, in the time that k is odd number, by the cosine signal generating, every a work clock, does sign-inverted one time.In like manner can be by parallel n road sinusoidal signal combination producing sinusoidal pattern carrier signal.

In the time that k is odd number:

$\left\{\begin{array}{c}{\mathrm{sig}}_{Q_1}\left(i\right)={(-1)}^i\·\sin (2\mathrm{\π}{f_z}^{\′}i/{f_o}^{\′}+\mathrm{\θ})\\ {\mathrm{sig}}_{Q_2}\left(i\right)={(-1)}^i\·\sin (2\mathrm{\π}{f_z}^{\′}i/{f_o}^{\′}+2\mathrm{\π}{f}_z/{{\mathrm{nf}}_o}^{\′}+\mathrm{\θ})\\ ......\\ {\mathrm{sig}}_{Q_n}\left(i\right)={(-1)}^i\·\sin (2\mathrm{\π}{f_z}^{\′}i/{f_o}^{\′}+2\mathrm{\π}{f}_z(n-1)/{{\mathrm{nf}}_o}^{\′}+\mathrm{\θ})\end{array}\right.$

In the time that k is even number:

$\left\{\begin{array}{c}{\mathrm{sig}}_{Q_1}\left(i\right)=\sin (2\mathrm{\π}{f_z}^{\′}i/{f_o}^{\′}+\mathrm{\θ})\\ {\mathrm{sig}}_{Q_2}\left(i\right)=\sin (2\mathrm{\π}{f_z}^{\′}i/{f_o}^{\′}+2\mathrm{\π}{f}_z/{{\mathrm{nf}}_o}^{\′}+\mathrm{\θ})\\ ......\\ {\mathrm{sig}}_{Q_n}\left(i\right)=\sin (2\mathrm{\π}{f_z}^{\′}i/{f_o}^{\′}+2\mathrm{\π}{f}_z(n-1)/{{\mathrm{nf}}_o}^{\′}+\mathrm{\θ})\end{array}\right.$

By above-mentioned formula, can find out, when frequency of utilization is f _z', the first phase of n road signal is respectively θ, 2, π f _z/ nf _o'+θ ..., 2 π (n-1) f _z/ nf _othe sinusoidal signal combination that the DDS of '+θ (wherein θ is freely worth) generates, just can complete the generation of sinusoidal pattern carrier signal, wherein, can find out from above-mentioned formula, in the time that k is odd number, by the cosine signal generating, every a work clock, do sign-inverted one time.

So the frequency that the present invention configures n DDS is f _z' be respectively 2 π (i-1) f with first phase _z/ nf _o'+θ, i=1,2 ..., n, generates one group of n road low frequency sinusoidal signal data point and cosine signal data point at each work clock; This group low-frequency signals, by the modulation of step C and output chronologically, has been realized the high-frequency carrier signal of combination producing.

About step C, specific implementation process is as follows:

Step C1: as shown in Figure 2, be f by sinusoidal the low frequency of the baseband signal of parallel shunt and DDS generation and cosine signal at working clock frequency _o' signal processor on carry out quadrature modulation, the parallel modulation signal in the n road of generation is wherein:

$\left\{\begin{array}{c}{y}_1\left(i\right)=\mathrm{real}\left(s_{{\mathrm{out}}_1}\left(i\right)\right)\·\mathrm{si}{g}_{I_1}\left(i\right)+\mathrm{imag}\left(s_{{\mathrm{out}}_1}\left(i\right)\right)\·{\mathrm{sig}}_{I_1}\left(i\right)\\ y_2\left(i\right)=\mathrm{real}\left(s_{{\mathrm{out}}_2}\left(i\right)\right)\·{\mathrm{sig}}_{I_2}\left(i\right)+\mathrm{imag}\left(s_{\mathrm{ou}{t}_2}\left(i\right)\right)\·{\mathrm{sig}}_{I_2}\left(i\right)\\ ...\\ y_n\left(i\right)=\mathrm{real}\left(s_{{\mathrm{out}}_n}\left(i\right)\right)\·{\mathrm{sig}}_{I_n}\left(i\right)+\mathrm{imag}\left(s_{{\mathrm{out}}_n}\left(i\right)\right)\·{\mathrm{sig}}_{I_n}\left(i\right)\end{array}\right.$

Step C2: modulation signal along separate routes will walk abreast deposit in chronologically in buffer.Each work clock produces one group of data y ₁(i), y ₂(i) ..., y _n(i), put into successively buffer according to the order on the 1st n road, road to the, the order of finally putting into data is:

[y ₁(1),y ₂(1),…,y _n(1),y ₁(2),y ₂(2),…,y _n(2),…,…,y ₁(m),y ₂(m),…,y _n(m)]

Step C3: as shown in Figure 2, by the data of buffer according to first-in first-out principle, with f _sspeed is sent in D/A processor, thus the whole generative process of settling signal.

Technological means and effect of taking for reaching predetermined object in order further to set forth the present invention, below provide a concrete application example, and the technical scheme that the present invention is proposed is further expalined explanation.

In this application example, using the maximum functional clock frequency of signal processor is 275MHz, and buffer output data rate is 1GHz to the maximum.The bandwidth that generates signal is the signal that 2MHz, centre frequency are 350MHz.Further, the live signal generation method described in this application example completes as follows:

Steps A: baseband signal is done to parallel processing along separate routes;

Concrete, the detailed processing procedure of this step is as follows:

Steps A 1: according to the work clock of equipment index signalization processor.

First determine that from the speed of FIFO buffer input D/A processor the work clock of signal processor uses 250MHz, parallel way n=4 according to the D/A performance of signal generation equipment and signal.

Steps A 2: prototype FIR filter.

Generation meets decay in passband 0 ~ 0.002 π and is not more than 0.1dB, and the filter that the interior decay of stopband 0.25 π ~ π is not less than 40dB is:

$\tilde{h}=[\mathrm{0.008087,0.0364044,0.09101758,0.15776736,0.20479681},$

$\mathrm{0.20479681,0.1577673,0.0910175,00364044,0.0080876}]$

The length of filter is 10.

Steps A 3: utilize FIR filter by the parallel baseband signal 4 road signals that are divided into;

Prototype low-pass FIR filter is divided into n the FIR of branch filter

Raw baseband signal is shown in Fig. 2, every through a clock, once, the each FIR of branch filter reads a baseband signal to buffer shifts simultaneously, produces n new data.Corresponding to each input baseband signal s _in(i), export respectively n data:

Input successively baseband signal according to said process just can complete the parallel 4 roadbed band signals that are divided into of a roadbed band signal

Step B, generates n Low Frequency Sine Signals data point and cosine signal data point, generates high-frequency carrier signal in order to subsequent combination;

Concrete, the detailed processing procedure of this step is as follows:

Step B1: the first phase of asking shunting sign according to frequency of carrier signal.

Due to base band signal process and the same signal processor of carrier signal generation use, working clock frequency is consistent, and therefore the same 4 tunnel signal combination that use of carrier signal represent, the sample rate of one-channel signal is 250MHz, and 4 tunnel carrier signals can be expressed as:

$\left\{\begin{array}{c}{\mathrm{sig}}_{I_1}\left(j\right)=\cos \left(2.8\mathrm{\πi}\right)\\ {\mathrm{sig}}_{I_2}\left(j\right)=\cos (2.8\mathrm{\πi}+0.7\mathrm{\π})\\ {\mathrm{sig}}_{I_3}\left(j\right)=\cos (2.8\mathrm{\πi}+1.4\mathrm{\π})\\ {\mathrm{sig}}_{I_4}\left(j\right)=\cos (2.8\mathrm{\πi}+2.1\mathrm{\π})\end{array}\right.$

So, the first phase of every road signal is respectively 0,0.7 π, 1.4 π, 2.1 π.

Step B2: calculate the minimum frequency that each road signal is corresponding.

Intuitively show that by step B1 the frequency that every road signal is corresponding is 350MHz, utilize the signal processor of work on hand clock frequency to complete, now, 350MHz is converted, due to therefore k=2, has:

$\left\{\begin{array}{c}{\mathrm{sig}}_{I_1}\left(i\right)=\cos (0.8\mathrm{\πi})\\ {\mathrm{sig}}_{I_2}\left(i\right)=\cos (0.8\mathrm{\πi}+0.7\mathrm{\π})\\ {\mathrm{sig}}_{I_3}\left(i\right)=\cos (0.8\mathrm{\πi}+1.4\mathrm{\π})\\ {\mathrm{sig}}_{I_4}\left(i\right)=\cos (0.8\mathrm{\πi}+2.1\mathrm{\π})\end{array}\right.$

In like manner can generate the signal of parallel n road phase phasic difference 90o be respectively:

$\left\{\begin{array}{c}{\mathrm{sig}}_{Q_1}\left(i\right)=\sin (0.8\mathrm{\πi})\\ {\mathrm{sig}}_{Q_2}\left(i\right)=\sin (0.8\mathrm{\πi}+0.7\mathrm{\π})\\ {\mathrm{sig}}_{Q_3}\left(i\right)=\sin (0.8\mathrm{\πi}+1.4\mathrm{\π})\\ {\mathrm{sig}}_{Q_4}\left(i\right)=\sin (0.8\mathrm{\πi}+2.1\mathrm{\π})\end{array}\right.$

The high-frequency carrier signal that thereby the low frequency that realization is 100MHz by the frequency that is less than signal processor work clock is sinusoidal and cosine signal combination producing frequency is 350MHz.As shown in Figure 2 n DDS being inserted to frequency is 100MHz, and first phase is set to 0,0.7 π, 1.4 π, 2.1 π.

Step C, modulating baseband signal output on parallel basis along separate routes;

Concrete, the detailed processing procedure of this step is as follows:

Step C1: as shown in Figure 2, carry out quadrature modulation on the work clock that is 250MHz by parallel baseband signal along separate routes and sine or the cosine signal of parallel shunt in signal processor frequency, 4 channel parallel datas of generation are wherein:

$\left\{\begin{array}{c}{y}_1\left(i\right)=\mathrm{real}\left(s_{{\mathrm{out}}_1}\left(i\right)\right)\·{\mathrm{sig}}_{I_1}\left(i\right)+\mathrm{imag}\left(s_{{\mathrm{out}}_1}\left(i\right)\right)\·{\mathrm{sig}}_{I_1}\left(i\right)\\ y_2\left(i\right)=\mathrm{real}\left(s_{{\mathrm{out}}_2}\left(i\right)\right)\·{\mathrm{sig}}_{I_2}\left(i\right)+\mathrm{imag}\left(s_{{\mathrm{out}}_2}\left(i\right)\right)\·{\mathrm{sig}}_{I_2}\left(i\right)\\ y_3\left(i\right)=\mathrm{real}\left(s_{{\mathrm{out}}_3}\left(i\right)\right)\·{\mathrm{sig}}_{I_3}\left(i\right)+\mathrm{imag}\left(s_{{\mathrm{out}}_3}\left(i\right)\right)\·{\mathrm{sig}}_{I_3}\left(i\right)\\ y_4\left(i\right)=\mathrm{real}\left(s_{{\mathrm{out}}_4}\left(i\right)\right)\·{\mathrm{sig}}_{I_4}\left(i\right)+\mathrm{imag}\left(s_{{\mathrm{out}}_4}\left(i\right)\right)\·{\mathrm{sig}}_{I_4}\left(i\right)\end{array}\right.$

Step C2: array along separate routes will walk abreast deposit in chronologically in buffer.Each work clock produces one group of data y ₁(i), y ₂(i), y ₃(i), y ₄(i), put into successively buffer according to the order on 4 tunnels, the 1st road to the.The order of finally putting into data is:

[y ₁(1),y ₂(1),y ₃(1),y ₄(1),y ₁(2),y ₂(2),y ₃(2),y ₄(2),

…,y ₁(m),y ₂(m),y ₃(m),y ₄(m)]

Step C3: according to as shown in Figure 2, the data of buffer, according to first-in first-out principle, are sent in D/A processor with 1GHz speed, thus the whole generative process of settling signal.

Embodiment tri-

As shown in Figure 3, the present embodiment provides a kind of signal processor, specifically comprises:

The parallel processing unit 310 along separate routes of baseband signal, reads the data point of a baseband signal taking work clock as sample rate, and the each baseband signal data point reading is walked abreast and is divided into n roadbed band signal data for each work clock;

Carrier signal parallel generation unit 320 can form a carrier signal and the data point of the low frequency sinusoidal signal taking work clock as sample rate and the data point of low frequency cosine signal after generating respectively n combination; Wherein, the frequency f of each low frequency signal data point _z'=f _z-kf _o' 2, in formula, k gets and meets 0≤f _z'≤f _o' 2 positive integer, f _o' be work clock, f _zfor set value be greater than the centre frequency of the signal to be generated of signal processor maximum functional clock, wherein, in the time that the value of k is odd number, n taking work clock as sample rate Low Frequency Sine Signals data point and n low frequency cosine signal data point need to, every a data point, be done sign-inverted one time;

Signal modulating unit 330, for described n roadbed band signal and n Low Frequency Sine Signals data point, a n low frequency cosine signal data point are carried out to quadrature modulation, obtains parallel n road modulation signal;

Signal buffer unit 340, for depositing chronologically described n road modulation signal in buffer memory, and according to first-in first-out principle, each work clock reads one group of n road modulation signal output.

Wherein, the work clock f of described signal processor _o' meet following condition: f _o'≤f _oand f _s=nf _o', f in formula _ofor the maximum functional clock frequency of signal processor, f _sfor the speed of signal processor output signal.

Preferably, the parallel processing unit 310 along separate routes of described baseband signal, comprising:

Filter arranges subelement, and for according to the signal bandwidth of the signal to be generated of work clock, along separate routes number n and setting, generation sample rate is nf _o', cut-off frequecy of passband is more than or equal to the prototype FIR filter that baseband signal bandwidth is less than or equal to work clock, and described prototype FIR filter is divided into n branching filter; Wherein, i the FIR of branch filter, from i value of prototype FIR filter, got a value every n point, until ending, i=1,2 ..., n;

Subelement is processed in parallel shunt, for utilizing the FIR of branch filter, reads a baseband signal data point at each work clock, uses respectively n the FIR of branch filter by parallel the each described baseband signal data point the reading n roadbed band signal data point that is divided into.

Preferably, carrier signal parallel generation unit 320 is followed successively by θ, 2 π f by the first phase of n Low Frequency Sine Signals data point is set _z/ nf _o'+θ ..., 2 π (n-1) f _z/ nf _o'+θ, realizes a sinusoidal pattern carrier signal of n the rear formation of Low Frequency Sine Signals data point combination; By being set, the first phase of n road low frequency cosine signal data point is followed successively by θ, 2 π f _z/ nf _o'+θ ..., 2 π (n-1) f _z/ nf _o'+θ, realizes a longitudinal cosine type carrier signal of n the rear formation of low frequency cosine signal data point combination; Wherein, θ is freely worth.

Preferably, carrier signal parallel generation unit 320, is f specifically for the frequency that n DDS is set _z', first phase is respectively 2 π (i-1) f _z/ nf _o'+θ, i=1,2 ..., n, and in the time that each work clock arrives, utilizes n DDS to generate respectively the individual Low Frequency Sine Signals data point taking work clock as sample rate of n and the data point of low frequency cosine signal.

In sum, method and apparatus described in the present embodiment, by using n low frequency sine and cosine signal data point combination producing high-frequency carrier signal, realize under lower work clock, complete the generative process of higher frequency signals, not only reduce the hardware device cost of signal generating system, but also realized the high-frequency signal that the current processor of real-time generation does not become according to the life of Nyquist law.

Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if these amendments of the present invention and within modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.

Claims (10)

1. a live signal generation method, is characterized in that, comprising:

The each work clock of signal processor reads the data point of a baseband signal taking work clock as sample rate, and by parallel the each baseband signal data point the reading n roadbed band signal data that are divided into;

The each work clock of signal processor can form the data point of a carrier signal and the Low Frequency Sine Signals taking work clock as sample rate and the data point of low frequency cosine signal after generating respectively n combination; Wherein, the frequency f of each low frequency signal data point _z'=f _z-kf _o'/2, in formula, k gets and meets 0≤f _z'≤f _o'/2 positive integer, f _o' be work clock, f _zfor the value of setting is greater than the centre frequency of the signal to be generated of signal processor maximum functional clock, wherein, in the time that the value of k is odd number, the n taking work clock as sample rate Low Frequency Sine Signals data point and n low frequency cosine signal data point are done sign-inverted one time every a work clock;

Described n roadbed band signal and n Low Frequency Sine Signals data point, a n low frequency cosine signal data point are carried out quadrature modulation by signal processor, obtain after parallel n road modulation signal, deposit chronologically described n road modulation signal in buffer memory, and according to first-in first-out principle, each work clock reads one group of n road modulation signal output.

2. the method for claim 1, is characterized in that, the work clock f of described signal processor _o' meet following condition: f _o'≤f _oand f _s=nf _o', f in formula _ofor the maximum functional clock frequency of signal processor, f _sfor the speed of signal processor output signal.

3. method as claimed in claim 1 or 2, is characterized in that, described signal processor is divided into n roadbed band signal data by parallel the each baseband signal data point reading, and specifically comprises:

According to the signal bandwidth of the signal to be generated of work clock, along separate routes number n and setting, generation sample rate is nf _o', cut-off frequecy of passband is more than or equal to the prototype FIR filter that baseband signal bandwidth is less than or equal to work clock, and described prototype FIR filter is divided into n branching filter; Wherein, i the FIR of branch filter, from i value of prototype FIR filter, got a value every n point, until ending, i=1,2 ..., n; Wherein, prototype FIR filter is low pass filter;

Described signal processor utilizes the FIR of branch filter, reads a baseband signal data point at each work clock, uses respectively n the FIR of branch filter by parallel the each described baseband signal data point the reading n roadbed band signal data point that is divided into.

4. method as claimed in claim 1 or 2, is characterized in that, described signal processor is followed successively by θ, 2 π f by the first phase of n Low Frequency Sine Signals data point is set _z/ nf _o'+θ ..., 2 π (n-1) f _z/ nf _o'+θ, realizes a sinusoidal pattern carrier signal of n the rear formation of Low Frequency Sine Signals data point combination; By being set, the first phase of n low frequency cosine signal data point is followed successively by θ, 2 π f _z/ nf _o'+θ ..., 2 π (n-1) f _z/ nf _o'+θ, realizes a longitudinal cosine type carrier signal of n the rear formation of low frequency cosine signal data point combination; Wherein, θ is arbitrary value.

5. method as claimed in claim 4, is characterized in that, described signal processor is f by the frequency that n DDS is set _z', first phase is respectively 2 π (i-1) f _z/ nf _o'+θ, i=1,2 ..., n, realizes in the time that each work clock arrives, and utilizes n DDS to generate respectively the individual Low Frequency Sine Signals data point taking work clock as sample rate of n and the data point of low frequency cosine signal.

6. a signal processor, is characterized in that, comprising:

The parallel processing unit along separate routes of baseband signal, reads the data point of a baseband signal taking work clock as sample rate, and the each baseband signal data point reading is walked abreast and is divided into n roadbed band signal data for each work clock;

Carrier signal parallel generation unit can form a carrier signal and the data point of the low frequency sinusoidal signal taking work clock as sample rate and the data point of low frequency cosine signal after generating respectively n combination; Wherein, the frequency f of each low frequency signal data point _z'=f _z-kf _o'/2, in formula, k gets and meets 0≤f _z'≤f _o'/2 positive integer, f _o' be work clock, f _zfor set value be greater than the centre frequency of the signal to be generated of signal processor maximum functional clock, wherein, in the time that the value of k is odd number, n taking work clock as sample rate Low Frequency Sine Signals data point and n low frequency cosine signal data point need to, every a data point, be done sign-inverted one time;

Signal modulating unit, for described n roadbed band signal and n Low Frequency Sine Signals data point, a n low frequency cosine signal data point are carried out to quadrature modulation, obtains parallel n road modulation signal;

Signal buffer unit, for depositing chronologically described n road modulation signal in buffer memory, and according to first-in first-out principle, each work clock reads one group of n road modulation signal output.

7. signal processor as claimed in claim 6, is characterized in that, the work clock f of described signal processor _o' meet following condition: f _o'≤f _oand f _s=nf _o', f in formula _ofor the maximum functional clock frequency of signal processor, f _sfor the speed of signal processor output signal.

8. the signal processor as described in claim 6 or 7, is characterized in that, the parallel processing unit along separate routes of described baseband signal, specifically comprises:

Filter arranges subelement, and for according to the signal bandwidth of the signal to be generated of work clock, along separate routes number n and setting, generation sample rate is nf _o', cut-off frequecy of passband is more than or equal to the prototype FIR filter that baseband signal bandwidth is less than or equal to work clock, and described prototype FIR filter is divided into n branching filter; Wherein, i the FIR of branch filter, from i value of prototype FIR filter, got a value every n point, until ending, i=1,2 ..., n; Wherein, prototype FIR filter is low pass filter;

Subelement is processed in parallel shunt, for utilizing the FIR of branch filter, reads a baseband signal data point at each work clock, uses respectively n the FIR of branch filter by parallel the each described baseband signal data point the reading n roadbed band signal data point that is divided into.

9. the signal processor as described in claim 6 or 7, is characterized in that, described carrier signal parallel generation unit is followed successively by θ, 2 π f by the first phase of n Low Frequency Sine Signals data point is set _z/ nf _o'+θ ..., 2 π (n-1) f _z/ nf _o'+θ, realizes a sinusoidal pattern carrier signal of n the rear formation of Low Frequency Sine Signals data point combination; By being set, the first phase of n road low frequency cosine signal data point is followed successively by θ, 2 π f _z/ nf _o'+θ ..., 2 π (n-1) f _z/ nf _o'+θ, realizes a longitudinal cosine type carrier signal of n the rear formation of low frequency cosine signal data point combination; Wherein, θ is arbitrary value.

10. signal processor as claimed in claim 9, is characterized in that, described carrier signal parallel generation unit, is f specifically for the frequency that n DDS is set _z', first phase is respectively 2 π (i-1) f _z/ nf _o'+θ, i=1,2 ..., n, and in the time that each work clock arrives, utilizes n DDS to generate respectively the individual Low Frequency Sine Signals data point taking work clock as sample rate of n and the data point of low frequency cosine signal.