CN103150990B - Light-emitting diode (LED) display screen constant-current driving circuit with plurality of mirror image ratios - Google Patents
Light-emitting diode (LED) display screen constant-current driving circuit with plurality of mirror image ratios Download PDFInfo
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- CN103150990B CN103150990B CN201310080466.2A CN201310080466A CN103150990B CN 103150990 B CN103150990 B CN 103150990B CN 201310080466 A CN201310080466 A CN 201310080466A CN 103150990 B CN103150990 B CN 103150990B
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Abstract
The invention discloses a light-emitting diode (LED) display screen constant-current driving circuit with a plurality of mirror image ratios. The driving circuit comprises a reference voltage source circuit, a constant-current regulation circuit, a voltage sampling circuit, a current mirror image ratio self-regulation circuit, a current mirror circuit and a display frame data processing circuit. The reference voltage source circuit comprises a seven-stage ring oscillator and a band-gap reference circuit. The constant-current regulation circuit comprises a comparator, a current biasing tube and an external grounding resistor. The current mirror circuit comprises a plurality of current mirror image tubes. The display frame data processing circuit comprises a plurality of display frame data processing units. An output driving channel port of the circuit is provided with a voltage-resistant circuit comprising two N-channel metal oxide semiconductor (NMOS) tubes. A first-stage current mirror group comprises a plurality of current mirror image tubes. A second-stage current mirror group comprises a plurality of current mirror image tubes. The driving circuit has a plurality of mirror image ratios, and has the advantages that gray levels of an LED display screen can be regulated and added, the brightness contrast of the LED display screen can be improved, the problem of voltage resistance of the output driving channel port is solved with lower cost, and the like.
Description
The application is the divisional application that application number is 201110301641.7, the applying date is on September 28th, 2011, denomination of invention is " the LED display constant-current drive circuit of optional mirror image ratio ".
Technical field
The present invention relates to a kind of driving circuit, especially a kind of LED display constant-current drive circuit with multiple image ratio.
Background technology
Light emitting diode is a kind of current control device, has the advantages such as brightness is high, volume is little, low in energy consumption, monochromaticity good, fast response time, long service life.Form large, medium and small type LED display by light emitting diode matrix, can be used for the various information such as display text, figure, image, animation, market, video, and the Full color LED display screen being made up of light emitting diodes red, green and blue three primary colours can show fine and smooth coloured image especially.In full-color LED display screen, in order to improve the display quality of display screen, make it to adapt to daytime, night, cloudy day, the various light environments such as sunny, and the different display background such as mountain, building, sky, people need to set up different brightness and gray scale corresponding relation, make beholder obtain the optimized image gray-level and the brightness contrast relation that are applicable to human eye characteristic.
Prior art generally adopts the mode of scan control, sets up different gradation of image levels and brightness contrast relation.The principle of this control control technology is, within the scan period, the brightness of light emitting diode is carried out to time quantization, is divided into M time brightness unit, bright N(N≤M within the scan period) inferior; In the time that the sweep frequency of time brightness unit is greater than the distinguishable frequency of human eye, just can obtain
the display effect of individual light-emitting diode luminance, then by three kinds of colors
,
,
modulate, thereby obtain the system of a gradation of image level and brightness contrast relation.The value of the M is here larger, and the gray-level that can realize is just more, and luminance contrast is just larger, and displayable information is just abundanter, and image is also just finer and smoother.But because the brightness of light emitting diode is to be determined by the size of current that drives it, so the value of M can be activated the conforming restriction of electric current between electric current constant current accuracy and different current drives passage, thereby be difficult to set up the system of very accurate more gray-levels and brightness contrast relation, and then affect the display quality of whole full-color LED display screen.
In addition, in order to improve the overall brightness of LED display, adapt to the stronger environment of light, when part LED display is produced in design, several LED strings can be increased to brightness together, but such scheme can increase the supply voltage of whole system, also require the output of LED drive circuit to drive access port to there is the characteristic that voltage endurance capability can promote simultaneously.For making the output of LED drive circuit drive access port to there is the characteristic that voltage endurance capability can promote, the mode of main solution is to use higher withstand voltage processing technology instead or each data-out port removes driving LED string by a withstand voltage driving tube, but this two schemes all can increase the cost of whole system.
Summary of the invention
The present invention is the weak point existing in above-mentioned prior art for avoiding, and a kind of LED display constant-current drive circuit with multiple image ratio is provided, to make driving circuit have multiple image ratio and image ratio can be adjusted as required.
The present invention be technical solution problem by the following technical solutions.
There is the LED display constant-current drive circuit of multiple image ratio, its design feature is, comprises that reference voltage source circuit, constant flow regulation circuit, voltage sampling circuit, current mirror are than adaptive circuit, adjustable second level current mirror group and the display frame data processing circuit of first order current mirror, image ratio that image ratio is adjustable; Described reference voltage source circuit is connected with voltage sampling circuit with constant flow regulation circuit respectively, for generation of reference voltage U
0, and by reference voltage U
0input to respectively constant flow regulation circuit and voltage sampling circuit; Described constant flow regulation circuit is connected with first order current mirror, for the reference voltage U producing according to described reference voltage source circuit
0, produce a steady current I
0, and by steady current I
0transfer to first order current mirror; First order current mirror is connected with voltage sampling circuit with second level current mirror group respectively, and by steady current I
0the electric current I that mirror image obtains later
1be transferred to respectively second level current mirror group, simultaneously by voltage signal
export voltage sampling circuit to; Described voltage sampling circuit is connected than adaptive circuit with current mirror, for according to reference voltage U
0and voltage signal
obtain two signals of a26 and a32, and signal a26 and a32 input current mirror image are compared to adaptive circuit; Described current mirror is connected with second level current mirror group with first order current mirror respectively than adaptive circuit, according to signal a26 and the a32 of the output of voltage sampling circuit, obtain current mirror than control signal d08 and d09 and export first order current mirror to, obtain current mirror than control signal a27 and a31 and export second level current mirror group to; First order current mirror, than output control signal d08 and the d09 of adaptive circuit, adjusts different current mirror image tube conduction modes according to current mirror, realizes the adjustment of image ratio; Second level current mirror group, than output control signal a27 and the a31 of adaptive circuit, adjusts different current mirror image tube conduction modes according to current mirror, realizes the adjustment of image ratio; Described display frame data processing circuit, comprises multiple display frame data processing units; The output terminal of described display frame data processing unit is connected to respectively the input end of second level current mirror group; Output drives access port to be provided with voltage holding circuit, and described voltage holding circuit comprises two NMOS pipes: M1 and M2; Wherein, the source of M1 and the drain terminal of M2 link together, the source ground connection of M2, and the drain terminal of M1 connects data output pressure welding point.
Described first order current mirror comprises multiple current mirror image tubes, than output control signal d08 and the d09 of adaptive circuit, adjusts different current mirror image tube conduction modes according to current mirror, realizes the adjustment of 1:1,1:2 and tri-kinds of image ratios of 1:4; The described second level adjustable current mirroring circuit of image ratio comprises multiple current mirror image tubes, according to current mirror than output control signal a27 and the a31 of adaptive circuit, adjust different current mirror image tube conduction modes, realize the adjustment of 1:15,1:7.5 and tri-kinds of image ratios of 1:3.75; The image ratio of described first order current mirror: 1:1,1:2 and 1:4, with image ratio 1:15,1:7.5 and the 1:3.75 of second level current mirror circuit be one-to-one relationship, can synthesize: 1:1:15; 1:2:7.5; 1:4:3.75 three kinds of image ratios.
Described reference voltage source circuit comprises seven grades of loop oscillators and band-gap reference circuit; Wherein, seven grades of described loop oscillators produce one group each other oppositely oscillator signal as the enabling signal of band-gap reference circuit; Described band-gap reference circuit for generation of reference voltage U
0, be input to respectively constant flow regulation circuit and voltage sampling circuit.
Described constant flow regulation circuit comprises a comparer, a current offset pipe and an external stake resistance, by regulating the size adjustment steady current I of external stake resistance
0; Wherein, described comparer reference voltage U that input termination reference voltage source circuit provides
0; The ungrounded end of another input end of described comparer and external stake resistance and the source three of current offset pipe link together; The grid end of the output termination current offset pipe of described comparer, the drain terminal of current offset pipe is as steady current I
0output terminal.
Described voltage sampling circuit comprises two differential comparators and a logic processing circuit; An input end of two differential comparators all connects from the voltage signal of first order current mirror output
, another input end of two differential comparators meets respectively the reference voltage U of reference voltage source circuit output
0with the voltage that supply voltage dividing potential drop obtains, the signal of the output terminal of two differential comparators, through logic processing circuit processing, obtains two signals of a26 and a32, and input current mirror image compares adaptive circuit.
Described current mirror comprises multiple logics and sequential circuit than adaptive circuit, according to sampled result signal a26 and the a32 of voltage sampling circuit, automatically select the current mirror of corresponding states to export than control signal, be that output current mirror image arrives first order current mirror than control signal d08 and d09, output current mirror image arrives second level current mirror group than control signal a27 and a31 simultaneously.
Described display frame data processing circuit comprises multiple display frame data processing units; Each display frame data processing unit comprises 1 bit data register, a 1 bit data latch and two input nand gate compositions; Described 1 bit data latch D termination 1 bit data register Q end, an input end of 1 bit data latch Q termination two input nand gates; Another input end of two input nand gates in described all display frame data processing units arranges unified data output switch signal, the input end of the corresponding second level of the output terminal current mirror group of each two input nand gates; 1 bit data register D end input display frame serial data in described first display frame data processing unit, 1 bit data register Q end in last display frame data processing unit outputs to chip pin by circuit, 1 bit data register Q end in 1 bit data register D termination in all the other display frame data processing units in a display frame data processing unit, 1 bit data register D end in the next display frame data processing unit of 1 bit data register Q termination in display frame data processing unit; The clock signal of 1 bit data register in described all display frame data processing units is identical; The clock signal of 1 bit data latch in described all display frame data processing units is identical; 1 bit data register in described all display frame data processing units is identical with 1 bit data latch reset signal.
Compared with the prior art, beneficial effect of the present invention is embodied in:
(1) apply the constant flow regulation circuit that operational amplification circuit forms, make the electric current of constant flow regulation circuit output only adjust leakage resistance relevant to reference voltage and definite value, recycle bandgap voltage reference technology, improved the constant current accuracy of chip;
(2) according to the voltage sample result of first order current mirror output offset pipe, select suitable current mirror ratio, avoid the primary current of second level current mirror excessive or too small, ensure the mirror image precision of second level current mirror;
(3) chip has shared the adjustable current mirroring circuit of first order image ratio, in improving chip performance, has reduced the area of repetitive in chip, effectively reduces chip cost, work power consumption and different output and drives the current error between passage; Can synthesize: 1:1:15; 1:2:7.5; 1:4:3.75 three kinds of image ratios
(4) output of chip drives access port that voltage holding circuit is set, and improves in the scheme of brightness of display screen at serial LED, and directly driving LED string, can not increase the cost of whole system.
LED display constant-current drive circuit of the present invention, can improve the drive current constant current accuracy of existing LED display chip and reduce the current error between different current drives passages, increase LED display gray-level and strengthen luminance contrast, thereby realize the object that promotes LED display display quality, and solve and export the problem of withstand voltage that drives access port at lower cost, and can synthesize: 1:1:15; 1:2:7.5; 1:4:3.75 three kinds of image ratios.
Brief description of the drawings
Fig. 1 is integrated circuit block diagram in the present invention's one embodiment.
Fig. 2 is constant flow regulation circuit in the present invention's one embodiment.
Fig. 3 is first order current mirror in the present invention's one embodiment.
Fig. 4 is the single current mirror circuit in the current mirror group of the second level in the present invention's one embodiment.
Fig. 5 is display frame data processing circuit in the present invention's one embodiment.
Fig. 6 is 13V voltage holding circuit in the present invention's one embodiment.
Below pass through embodiment, and the invention will be further described by reference to the accompanying drawings.
Embodiment
Referring to Fig. 1～Fig. 6, there is the LED display constant-current drive circuit of multiple image ratio, comprise that reference voltage source circuit, constant flow regulation circuit, voltage sampling circuit, current mirror are than adaptive circuit, adjustable second level current mirror group and the display frame data processing circuit of first order current mirror, image ratio that image ratio is adjustable; Described reference voltage source circuit is connected with voltage sampling circuit with constant flow regulation circuit respectively, for generation of reference voltage U
0, and by reference voltage U
0input to respectively constant flow regulation circuit and voltage sampling circuit; Described constant flow regulation circuit is connected with first order current mirror, for the reference voltage U producing according to described reference voltage source circuit
0, produce a steady current I
0, and by steady current I
0transfer to first order current mirror; First order current mirror is connected with voltage sampling circuit with second level current mirror group respectively, and by steady current I
0the electric current I that mirror image obtains later
1be transferred to respectively second level current mirror group, simultaneously by voltage signal
export voltage sampling circuit to; Described voltage sampling circuit is connected than adaptive circuit with current mirror, for according to reference voltage U
0and voltage signal
obtain two signals of a26 and a32, and signal a26 and a32 input current mirror image are compared to adaptive circuit; Described current mirror is connected with second level current mirror group with first order current mirror respectively than adaptive circuit, according to signal a26 and the a32 of the output of voltage sampling circuit, obtain current mirror than control signal d08 and d09 and export first order current mirror to, obtain current mirror than control signal a27 and a31 and export second level current mirror group to; First order current mirror, than output control signal d08 and the d09 of adaptive circuit, adjusts different current mirror image tube conduction modes according to current mirror, realizes the adjustment of image ratio; Second level current mirror group, than output control signal a27 and the a31 of adaptive circuit, adjusts different current mirror image tube conduction modes according to current mirror, realizes the adjustment of image ratio; Described display frame data processing circuit, comprises multiple display frame data processing units; The output terminal of described display frame data processing unit is connected to respectively the input end of second level current mirror group; Output drives access port to be provided with voltage holding circuit, and described voltage holding circuit comprises two NMOS pipes: M1 and M2; Wherein, the source of M1 and the drain terminal of M2 link together, the source ground connection of M2, and the drain terminal of M1 connects data output pressure welding point.
Described first order current mirror comprises multiple current mirror image tubes, than output control signal d08 and the d09 of adaptive circuit, adjusts different current mirror image tube conduction modes according to current mirror, realizes the adjustment of 1:1,1:2 and tri-kinds of image ratios of 1:4; The described second level adjustable current mirroring circuit of image ratio comprises multiple current mirror image tubes, according to current mirror than output control signal a27 and the a31 of adaptive circuit, adjust different current mirror image tube conduction modes, realize the adjustment of 1:15,1:7.5 and tri-kinds of image ratios of 1:3.75; The image ratio of described first order current mirror: 1:1,1:2 and 1:4, with image ratio 1:15,1:7.5 and the 1:3.75 of second level current mirror circuit be one-to-one relationship, can synthesize: 1:1:15; 1:2:7.5; 1:4:3.75 three kinds of image ratios.
Described reference voltage source circuit comprises seven grades of loop oscillators and band-gap reference circuit; Wherein, seven grades of described loop oscillators produce one group each other oppositely oscillator signal as the enabling signal of band-gap reference circuit; Described band-gap reference circuit for generation of reference voltage U
0, be input to respectively constant flow regulation circuit and voltage sampling circuit.
Described constant flow regulation circuit comprises a comparer, a current offset pipe and an external stake resistance, by regulating the size adjustment steady current I of external stake resistance
0; Wherein, described comparer reference voltage U that input termination reference voltage source circuit provides
0; The ungrounded end of another input end of described comparer and external stake resistance and the source three of current offset pipe link together; The grid end of the output termination current offset pipe of described comparer, the drain terminal of current offset pipe is as steady current I
0output terminal.
Described voltage sampling circuit comprises two differential comparators and a logic processing circuit; An input end of two differential comparators all connects from the voltage signal of first order current mirror output
, another input end of two differential comparators meets respectively the reference voltage U of reference voltage source circuit output
0with the voltage that supply voltage dividing potential drop obtains, the signal of the output terminal of two differential comparators, through logic processing circuit processing, obtains two signals of a26 and a32, and input current mirror image compares adaptive circuit.
Described current mirror comprises multiple logics and sequential circuit than adaptive circuit, according to sampled result signal a26 and the a32 of voltage sampling circuit, automatically select the current mirror of corresponding states to export than control signal, be that output current mirror image arrives first order current mirror than control signal d08 and d09, output current mirror image arrives second level current mirror group than control signal a27 and a31 simultaneously.
Described display frame data processing circuit comprises multiple display frame data processing units; Each display frame data processing unit comprises 1 bit data register, a 1 bit data latch and two input nand gate compositions; Described 1 bit data latch D termination 1 bit data register Q end, an input end of 1 bit data latch Q termination two input nand gates; Another input end of two input nand gates in described all display frame data processing units arranges unified data output switch signal, the input end of the corresponding second level of the output terminal current mirror group of each two input nand gates; 1 bit data register D end input display frame serial data in described first display frame data processing unit, 1 bit data register Q end in last display frame data processing unit outputs to chip pin by circuit, 1 bit data register Q end in 1 bit data register D termination in all the other display frame data processing units in a display frame data processing unit, 1 bit data register D end in the next display frame data processing unit of 1 bit data register Q termination in display frame data processing unit; The clock signal of 1 bit data register in described all display frame data processing units is identical; The clock signal of 1 bit data latch in described all display frame data processing units is identical; 1 bit data register in described all display frame data processing units is identical with 1 bit data latch reset signal.
In Fig. 1, the flow direction that the direction of arrow is signal, reference voltage source circuit output reference voltage U
0to constant flow regulation circuit and voltage sampling circuit; Constant flow regulation circuit is according to reference voltage U
0with the size of external setting resistance R ext, export elementary image current I
0; Voltage sampling circuit is according to reference voltage U
0with the current offset pipe grid end of the first order current mirror voltage obtaining of sampling
, output sampled result signal a26 and a32; Current mirror is than adaptive circuit according to sampled result signal a26 and a32, and output current mirror image arrives first order current mirror than signalization d08 and d09, and output current mirror image arrives second level current mirror group than signalization a27 and a31; First order current mirror is pressed current mirror than image ratio and the elementary image current I of signalization d08 and d09 setting
0the secondary image current I that output is corresponding
1; Display frame data processing circuit is by corresponding each bit data in the display frame serial data of an input display frame data processing unit, display frame data processing circuit is exported 16 bit data and a display frame data cascade data altogether, a second level current mirror group of the corresponding input of each bit data; Each second level current mirror is pressed current mirror than image ratio and the secondary image current I of signalization a27 and a31 setting
1export corresponding drive current I
oUT, each with it corresponding bit data as output current I
oUTswitching signal;
Reference voltage source circuit is made up of seven grades of loop oscillators and a band-gap reference circuit, wherein, seven grades of described loop oscillators produce one group each other oppositely oscillator signal as the enabling signal of band-gap reference circuit, then produce U by band-gap reference circuit
0to constant flow regulation circuit and voltage sampling circuit;
Shown in Fig. 2 is constant flow regulation circuit, and wherein a25 is offset signal, and differential pair tube M8 and M5 meet respectively reference voltage U
0ungrounded end with external setting resistance R ext, regulates M1 by the output terminal of comparator circuit, by the voltage clamp of ungrounded end of setting resistance R ext to reference voltage U
0equally size, elementary image current I flows through
0the size of current of corresponding current offset pipe M12 is U
0/ R
ext;
Voltage sampling circuit comprises two differential comparators and a logic processing circuit, and an input end of two differential comparators all connects from the current offset pipe grid end of the first order current mirror voltage obtaining of sampling
, another input end of two differential comparators meets respectively the reference voltage U of reference voltage source circuit output
0with the voltage that supply voltage dividing potential drop obtains, the signal of the output terminal of two differential comparators, through logic processing circuit processing, obtains two signals of a26 and a32, and input current mirror image compares adaptive circuit;
Current mirror comprises a series of logic and sequential circuit than adaptive circuit, according to sampled result signal a26 and the a32 of voltage sampling circuit, automatically select the current mirror of corresponding states to export than control signal, be that output current mirror image arrives the adjustable current mirroring circuit of first order image ratio than control signal d08 and d09, drive current and elementary image current I when d08 and the work of d09 low level
0size is identical; Output current mirror image arrives the adjustable current mirroring circuit of second level image ratio than control signal a27 and a31 simultaneously, drive current and secondary image current I when a27 and the work of a31 high level
1size is identical;
Shown in Fig. 3 is first order current mirror, in figure, a25 is offset signal, M14, M15 and M16 are current mirror image tube, and wherein m=20 (or 10) indicates 20(or 10) individual identical current mirror image tube parallel connection, in circuit the length of the current mirror image tube of two inter-stages with wide be corresponding identical.I in Fig. 2
0the m parameter of corresponding current offset pipe M12 is 10, according to current mirror principle, can obtain the current mirror ratio that M14, M15 and M16 are corresponding and be respectively: 1:2; 1:1; 1:1, can obtain current mirror ratio: 1:1 by array mode; 1:2; 1:4.In Fig. 3, secondary image current I flows through
1the size of current of corresponding current offset pipe M18 is corresponding mirror image multiple and U
0/ R
extproduct;
Shown in Fig. 4 is the single current mirror circuit in the current mirror group of the second level.In Fig. 4, a25 is offset signal; D_OUT is the bit data signal of display frame data processing circuit output; M21, M20 and M19 are current mirror image tube, and m parameter is respectively 15; 15; I in 30, Fig. 3
1the m parameter of corresponding current offset pipe M18 is 4, due to the length of the current mirror image tube of two inter-stages in circuit with wide be corresponding identical, according to current mirror principle, can obtain the current mirror ratio that M21, M20 and M19 are corresponding and be respectively: 1:3.75; 1:3.75; 1:7.5, can obtain current mirror ratio: 1:15 by array mode; 1:7.5; 1:3.75.In Fig. 4, the electric current of output current I_out is that twice current mirror multiple product is multiplied by U again
0/ R
ext.During due to circuit design there is corresponding relation in the image ratio of first order current mirror and second level current mirror, and two-stage current mirror ratio can synthesize: 1:1:15; 1:2:7.5; 1:4:3.75, the mirror image multiple product of two-stage current mirror is 15 all the time, output current is 15(U all the time
0/ R
ext);
Shown in Fig. 5 is display frame data processing circuit.Shown in figure, display frame data processing circuit is formed by 16 identical display frame data processing unit cascades.Each display frame data processing unit is made up of a 1 bit data register fd01, a 1 bit data latch fd02 and two input nand gates, the D termination 1 bit data register Q end of described 1 bit data latch fd02, a input end of Q termination two input nand gates of 1 bit data latch fd02, two input nand gate b input ends in described all display frame data processing units arrange unified data output switch signal switch, and the output terminal z of each two input nand gates, as D_out output terminal, outputs to the corresponding unit in the current mirror group of the second level, the D end input display frame serial data frame of 1 bit data register fd01 in described first display frame data processing unit, the Q end of 1 bit data register fd01 in last display frame data processing unit is held as F_out, output to chip pin by circuit, the Q end of 1 bit data register fd01 in the D termination of 1 bit data register fd01 in all the other display frame data processing units in a display frame data processing unit, the 1 bit data register D end of fd01 in the next display frame data processing unit of Q termination of 1 bit data register fd01 in display frame data processing unit, the clock signal of 1 bit data register fd01 in described all display frame data processing units is all clk, the clock signal of 1 bit data latch fd02 in described all display frame data processing units is all lock, 1 bit data register fd01 in described all display frame data processing units and the reset signal of 1 bit data latch fd02 are all clr,
Shown in Fig. 6, the 13V voltage holding circuit that the output of chip drives access port to arrange.Voltage holding circuit in figure comprises two NMOS pipes: M1 and M2, and wherein, the source of M1 and the drain terminal of M2 link together, the source ground connection of M2, the drain terminal of M1 connects data output pressure welding point, and in figure, A, B are the signals of controlling M1 and M2 switch; In the time that OUT port has electric current output: after current-limiting resistance R current limliting, the voltage of OUT port is limited to (0.4V～1.0V), now all conductings of M1 and M2, V
dS1with V
dS2all be less than 1V; In the time that OUT port does not have electric current output: the voltage of supposing OUT end is 13V, M1 and M2 end, not very large because the wide appearance of M1 and M2 is poor, within two orders of magnitude, M1 and M2 can be similar to and be equivalent to resistance R 1 and the R2 series connection that two resistance values as shown in dotted line in figure are very large and close, and Z point voltage is about 13/2=6.5V.Now the VDS of M1 and M2 is about 6.5V, within the technique withstand voltage of normal NMOS pipe.
Claims (1)
1. there is the LED display constant-current drive circuit of multiple image ratio, it is characterized in that, comprise that reference voltage source circuit, constant flow regulation circuit, voltage sampling circuit, current mirror are than adaptive circuit, adjustable second level current mirror group and the display frame data processing circuit of first order current mirror, image ratio that image ratio is adjustable;
Described reference voltage source circuit is connected with voltage sampling circuit with constant flow regulation circuit respectively, for generation of reference voltage U
0, and by reference voltage U
0input to respectively constant flow regulation circuit and voltage sampling circuit;
Described constant flow regulation circuit is connected with first order current mirror, for the reference voltage U producing according to described reference voltage source circuit
0, produce a steady current I
0, and by steady current I
0transfer to first order current mirror;
First order current mirror is connected with voltage sampling circuit with second level current mirror group respectively, and by steady current I
0the electric current I that mirror image obtains later
1be transferred to respectively second level current mirror group, simultaneously by voltage signal
export voltage sampling circuit to;
Described voltage sampling circuit is connected than adaptive circuit with current mirror, for according to reference voltage U
0and voltage signal
obtain two signals of a26 and a32, and signal a26 and a32 input current mirror image are compared to adaptive circuit;
Described current mirror is connected with second level current mirror group with first order current mirror respectively than adaptive circuit, according to signal a26 and the a32 of the output of voltage sampling circuit, obtain current mirror than control signal d08 and d09 and export first order current mirror to, obtain current mirror than control signal a27 and a31 and export second level current mirror group to;
First order current mirror, the current mirror of exporting than adaptive circuit according to current mirror, than control signal d08 and d09, is adjusted different current mirror image tube conduction modes, realizes the adjustment of image ratio;
Second level current mirror group, the current mirror of exporting than adaptive circuit according to current mirror, than control signal a27 and a31, is adjusted different current mirror image tube conduction modes, realizes the adjustment of image ratio;
Described display frame data processing circuit, comprises multiple display frame data processing units; The output terminal of each in described multiple display frame data processing unit is connected to respectively the input end of second level current mirror group;
Output drives access port to be provided with voltage holding circuit, and described voltage holding circuit comprises two NMOS pipes: M1 and M2; Wherein, the source of M1 and the drain terminal of M2 link together, the source ground connection of M2, and the drain terminal of M1 connects data output pressure welding point;
Described first order current mirror comprises multiple current mirror image tubes, and the current mirror of exporting than adaptive circuit according to current mirror, than control signal d08 and d09, is adjusted different current mirror image tube conduction modes, realizes the adjustment of 1:1,1:2 and tri-kinds of image ratios of 1:4; Described second level current mirror group comprises multiple current mirror image tubes, the current mirror of exporting than adaptive circuit according to current mirror is than control signal a27 and a31, adjust different current mirror image tube conduction modes, realize the adjustment of 1:15,1:7.5 and tri-kinds of image ratios of 1:3.75; The image ratio of described first order current mirror: 1:1,1:2 and 1:4, with image ratio 1:15,1:7.5 and the 1:3.75 of second level current mirror group be one-to-one relationship, can synthesize: 1:1:15; 1:2:7.5; 1:4:3.75 three kinds of image ratios.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310080466.2A CN103150990B (en) | 2011-09-28 | 2011-09-28 | Light-emitting diode (LED) display screen constant-current driving circuit with plurality of mirror image ratios |
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|---|---|---|---|
| CN201310080466.2A CN103150990B (en) | 2011-09-28 | 2011-09-28 | Light-emitting diode (LED) display screen constant-current driving circuit with plurality of mirror image ratios |
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| CN2011103016417A Division CN102306480B (en) | 2011-09-28 | 2011-09-28 | LED (light-emitting diode) display screen constant-current driving circuit with optional mirror image ratio |
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| JP2015069019A (en) * | 2013-09-30 | 2015-04-13 | シナプティクス・ディスプレイ・デバイス株式会社 | Semiconductor device |
| CN104485073B (en) * | 2014-12-25 | 2017-02-22 | 广东威创视讯科技股份有限公司 | Brightness adjustment method and system for LED display screens |
| CN110234188A (en) * | 2019-05-08 | 2019-09-13 | 深圳市富满电子集团股份有限公司 | The self shifter of LED drive chip adjusts circuit |
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| CN1549434A (en) * | 2003-05-08 | 2004-11-24 | 尹启凤 | Output current adjustable electric current drive circuit |
| CN101572984A (en) * | 2009-06-04 | 2009-11-04 | 吉林大学 | Image ratio constant flow source circuit driving multipath light emitting diode |
| CN201984781U (en) * | 2010-12-31 | 2011-09-21 | 海信（山东）空调有限公司 | LED (light-emitting diode) constant current drive circuit |
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| US7839099B2 (en) * | 2006-04-07 | 2010-11-23 | Semiconductor Components Industries, Llc | LED control circuit and method therefor |
| KR100691628B1 (en) * | 2006-04-07 | 2007-03-12 | 삼성전기주식회사 | Apparatus for driving led arrays |
| US8169387B2 (en) * | 2007-09-14 | 2012-05-01 | Ixys Corporation | Programmable LED driver |
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| CN1549434A (en) * | 2003-05-08 | 2004-11-24 | 尹启凤 | Output current adjustable electric current drive circuit |
| CN101572984A (en) * | 2009-06-04 | 2009-11-04 | 吉林大学 | Image ratio constant flow source circuit driving multipath light emitting diode |
| CN201984781U (en) * | 2010-12-31 | 2011-09-21 | 海信（山东）空调有限公司 | LED (light-emitting diode) constant current drive circuit |
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