CN103123954A - Method for manufacturing magnetic tunnel junction device - Google Patents
Method for manufacturing magnetic tunnel junction device Download PDFInfo
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- CN103123954A CN103123954A CN2011103711482A CN201110371148A CN103123954A CN 103123954 A CN103123954 A CN 103123954A CN 2011103711482 A CN2011103711482 A CN 2011103711482A CN 201110371148 A CN201110371148 A CN 201110371148A CN 103123954 A CN103123954 A CN 103123954A
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Abstract
The invention provides a method for manufacturing a magnetic tunnel junction device. The method includes the steps: providing a semiconductor substrate; forming an MTJ (magnetic tunnel junction) stacking structure on the semiconductor substrate; forming low dielectric materials on the MTJ stacking structure; forming a patterned hard mask layer on the low dielectric materials; removing parts of the low dielectric materials by etching and taking the patterned hard mask layer as a mask, and forming holes in the low dielectric materials; depositing oxides on the hard mask layer and in the holes; removing oxides outside the holes by chemical mechanical polishing; polishing the surfaces of the oxides and removing the hard mask layer; and removing the low dielectric materials to form a columnar structure comprising the oxides.
Description
Technical field
The present invention relates to a kind of manufacture method of magnetic RAM spare, particularly relate in making the technical process of magnetic funnel node device, a kind ofly form improving one's methods of hard mask.
Background technology
Magnetic RAM (Magnetic Random Access Memory, MRAM) device is widely used as nonvolatile memory.In MRAM, by the magnetic state storage data of memory element.Mram cell forms a memory cell jointly by a transistor and a MTJ (MTJ) usually.Described mtj structure comprises at least two electromagnetic layer and the insulating barrier that is used for isolating described two electromagnetic layer.Described two electromagnetic layer can be kept two magnetic polarization fields of being separated by insulating barrier, and one of them be fixed magnetic layer, or are called pinned (pinned) layer, and its polarised direction is fixed; Another is freely to rotate magnetosphere, and its polarised direction can change with the variation of external field.When the polarised direction of two electromagnetic layer was parallel, the tunnelling current of the mtj structure of flowing through had maximum, and the mtj structure cell resistance is lower; When two magnetospheric polarised direction antiparallels, the tunnelling current of the mtj structure of flowing through has minimum value, and the mtj structure cell resistance is higher.Come reading information by the resistance of measuring mram cell, the operation principle of Here it is mtj structure.
As shown in Figure 1, be a kind of existing mtj structure schematic diagram, wherein fixed magnetic layer 110, freely rotate magnetosphere 120 and at fixed magnetic layer 110 with freely rotate tunnel barrier layer 130 between magnetosphere 120.Described fixed magnetic layer 110, freely to rotate magnetosphere 120 and tunnel barrier layer 130 be all cylinder (or cylindroid) type structure.
In integrated circuit fabrication process, the transistor manufacturing is commonly referred to leading portion operation (FEOL) technological process, mtj stack be formed on transistor after, therefore, the formation of mtj stack should be compatible with standard last part technology (BEOL) technological process.And, due to the special nature of magnetic material, can not adopt the high-temperature technology flow process after mtj structure storehouse deposition.
In the mtj structure etching technics of mram cell, needing at first, the oxide after forming composition on the magnetic material of mtj stack as mask, defines the MTJ unit area.This oxide mask is column structure, in the prior art, by directly define the composition of column with photoetching process on photoresist, then adopts dry etching that drawing is transferred on oxide.Because the critical dimension of column type mtj structure is very little, must adopt FA lithographic equipment to define litho pattern, this can cause the MRAM manufacturing cost to rise.In addition, make mtj structure by prior art, the photoresist layer in the dry etch process process after composition is easy to be consumed light, and then makes oxide mask coarse, thereby causes the inconsistency of the relatively poor and shape of formed mtj structure critical size.
Therefore need a kind of improving one's methods of high-temperature technology that need not, form and have the oxide mask of critical size and the conforming column structure of shape preferably, thus the mtj structure in the preparation mram cell.
Summary of the invention
The invention provides a kind of method, form and to have the oxide mask of critical size and the conforming column structure of shape preferably, thus the preparation mtj structure.
Manufacture method according to the invention provides a kind of magnetic funnel node device comprises:
Semiconductor substrate is provided; Form the MTJ stepped construction on described Semiconductor substrate; Form advanced low-k materials on described formation MTJ stepped construction; Form the hard mask layer of patterning on described advanced low-k materials; Take the hard mask layer of described patterning as mask, remove a part of described advanced low-k materials by etch step, form hole in described advanced low-k materials; Deposition oxide on described hard mask layer and in described hole; Remove the outer described oxide of described hole by the cmp step, with described oxide surface polishing, and remove described hard mask layer; Remove described advanced low-k materials, form the column structure that described oxide consists of.
Preferably, wherein said Semiconductor substrate comprises transistor and is used for being electrically connected to described transistor and the interconnect architecture of the MTJ unit of formation subsequently.
Preferably, wherein said MTJ stepped construction comprises at least fixed magnetic layer, tunnel barrier layer and freely rotates magnetosphere.
Preferably, wherein said advanced low-k materials is the porous low dielectric constant material.
Preferably, adopt the described porous ultra-low dielectric constant material of spin coating method deposition.
Preferably, the polymer penetration step of carrying out after forming described advanced low-k materials.
Preferably, wherein said hard mask layer is titanium nitride (TiN) or boron nitride (BN).
Preferably, wherein said etch step is dry etching.
Preferably, after carrying out described cmp step, also comprise heating steps.
Preferably, wherein said column structure is elliptical cylinder-shape or cylindrical.
Description of drawings
Following accompanying drawing of the present invention is used for understanding the present invention at this as a part of the present invention.Shown in the drawings of one embodiment of the present of invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 is a kind of existing magnetic funnel node device structural representation;
Fig. 2 A-2J be according to one embodiment of the invention make magnetic funnel node device the manufacture method flow process in the schematic diagram of each step, wherein Fig. 2 A-2I is longitdinal cross-section diagram, Fig. 2 J is vertical view;
Fig. 3 makes the process chart of magnetic funnel node device according to one embodiment of the invention.
Symbol description:
Fig. 1
110: fixed magnetic layer, 120: freely rotate magnetosphere, 130: tunnel barrier layer
Fig. 2
200: Semiconductor substrate, 210:MTJ stepped construction, 211: fixed magnetic layer, 212: tunnel barrier layer, 213: freely rotate magnetosphere, 214: the first electrode layers, 220: porous low k material, 230: hard mask layer, 240: photoresist layer, 250: hole, 260: oxide, 270: the column structure of required form.
Embodiment
Next, more intactly describe the present invention in connection with accompanying drawing, the cross-sectional view as the schematic diagram of desirable embodiment of the present invention (and intermediate structure) shown in accompanying drawing is described inventive embodiment.In the accompanying drawings, for clear, size and the relative size in floor and district may be exaggerated.And, due to for example manufacturing technology and/or tolerance, change of shape shown in causing.Therefore, embodiments of the invention should not be confined to the specific size shape in district shown here, but comprise owing to for example making the form variations that causes.The district that shows in figure is in fact schematically, their shape be not intended display device the district actual size and shape and be not intended to limit scope of the present invention.The present invention can be with multi-form enforcement, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiment to expose thorough and complete, and scope of the present invention is fully passed to those skilled in the art.
The purpose of term only is to describe specific embodiment and not as restriction of the present invention as used herein.Should be noted that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or when layer, its can be directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, perhaps can have between two parties element or layer.On the contrary, when element be called as " directly exist ... on ", when " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer, do not have between two parties element or layer." one ", " one " and " described/as to be somebody's turn to do " that should be noted that singulative also are intended to comprise plural form, unless the other mode of pointing out known in context.Also should be noted that, term " composition " and/or " comprising ", when using in these specifications, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other existence or the interpolations of feature, integer, step, operation, element, parts and/or group.When this uses, term " and/or " comprise any and all combinations of relevant Listed Items.
At first, please refer to shown in Fig. 2 A, the dielectric layer 200 on Semiconductor substrate and Semiconductor substrate is provided.Described Semiconductor substrate comprises transistor and is used for being electrically connected to transistorized inner interconnection structure, do not illustrate in the drawings for accompanying drawing is easy.Described Semiconductor substrate also comprises the dielectric layer on Semiconductor substrate, wherein also comprises interconnection structure, is used for the MTJ unit that is electrically connected to the transistor of Semiconductor substrate and forms subsequently.
Then, please refer to shown in Fig. 2 B, form MTJ stepped construction 210 on described Semiconductor substrate 200.Forming described MTJ stepped construction 210 comprises at least and forms successively the first electrode layer 211, fixed magnetic layer 213, tunnel barrier layer 215 and freely rotate magnetosphere 217.In an embodiment of the present invention, it is 100 TaN that described MTJ stepped construction comprises thickness successively, and thickness is 150 MnIr, and thickness is 40 CoFe, and thickness is 35 MgO, and thickness is 50 CoFeB, and thickness is 150 Ru.Wherein, TaN and MnIr form fixed magnetic layer, and MgO is tunnel barrier layer, and CoFeB and Ru composition freely rotate magnetosphere.
Then, please refer to shown in Fig. 2 C, form porous low k material 220 on described MTJ stepped construction 210.Generally speaking, the dielectric constant k of low-k materials＜4, be organic dielectric materials or the siliceous inorganic material of single or multiple lift, comprise the organic polymer materials such as polyimide, Parylene class, polyene chain class, the inorganic material such as the silicon dioxide of fluoridizing, amorphous carbon nitrogen film, hydrogen base silsesquioxane (Hydrogen silsesquioxane, HSQ, (HSiO
3/2)
n), poly methyl silsesquioxane (Methylsilsesquioxane, MSQ, (CH
3SiO
3/2)
n) etc. silica-based porous low k material, and nanometer low-k materials.The porous low k material can adopt chemical vapour deposition technique (CVD) or spin coating method (Spin-On Deposition, SOD) to be deposited in substrate, then through solidifying to form dielectric layer.In an embodiment of the present invention, porous low k material 220 adopts spin coating method (SOD) deposition.Follow to a great extent the pattern of this porous media due to the film that deposits on the porous low k material, the roughness of porous low k material can affect its upper film as the effect of mask or diffusion impervious layer.Therefore, preferably, after deposition porous low k material, carry out polymer penetration step filling pore, make porous low k material 220 processing that strengthened.
Then, please refer to shown in Fig. 2 D, form hard mask layer 230 on described porous low k material 220.The deposition process of hard mask for example adopts chemical vapour deposition (CVD), plasma enhanced chemical vapor deposition, chemical solution deposition, evaporation, and perhaps by heat treatment, for example oxidation or nitrogenize forms hard mask.Hard mask comprises oxide, nitride, oxynitride or their multiple layer combination.In an embodiment of the present invention, described hard mask layer 230 is metal hard mask, preferably, is titanium nitride (TiN) or boron nitride (BN).
Then, please refer to shown in Fig. 2 E ~ 2F, remove a part of porous low k material 220 and hard mask layer 230 by photoetching process and etch step, form the hole 250 of required form.At first conventional photoetching process forms the photoresist layer on hard mask layer 230, this photoresist that then exposes forms required composition, and the baking process after then exposing also uses developer that composition is developed, thereby forms the photoresist layer 240 as shown in Fig. 2 E.Adopt subsequently for example dry etching enforcement main etching operation of conventional etching technics, figure is transferred to hard mask layer 230 and porous low k material 220 from the photoresist of patterning, form the hole 250 of the required form as shown in Fig. 2 F.What described hole 250 was for example elliptical cylinder-shape, cylindrical or other any formation mtj structure is required is irregularly shaped.Photoresist layer 240 after composition is removed by photoresistance ashing (Photo Resist Ashing) process after figure is transferred to hard mask layer 230 and porous low k material 220.
Subsequently, please refer to shown in Fig. 2 G, on described hard mask layer 230 and in the hole 250 of described porous low k material 220 and hard mask layer 230 formation, deposition oxide 260 is to fill hole 250.Subsequently, please refer to shown in Fig. 2 H, with described oxide 260 surface finish, the oxide 260 that major part is unnecessary is removed, and removes hard mask layer 230 by cmp (Chemical Mechanic Polishing, CMP) method.This chemical mechanical milling tech can adopt the grinding agent in general conventional art.Preferably, after the cmp step, the porous low k material 220 for by polymer penetration step filling pore makes its reinstatement by heating steps.
At last, please refer to shown in Fig. 2 I, remove described porous low k material 220, form the column structure 270 of the required form of oxide 260 formations.Fig. 2 J is the vertical view of column structure 270 in one embodiment of the invention that forms on dielectric layer 200 on described Semiconductor substrate and MTJ stepped construction 210, and wherein column structure 270 is oval column structure.
The making flow process of making magnetic funnel node device according to one embodiment of the invention as shown in Figure 3.In step 301, provide Semiconductor substrate.In step 302, form the MTJ stepped construction on described Semiconductor substrate.In step 303, form the porous low k material on described MTJ stepped construction.In step 304, form hard mask layer on described porous low k material.In step 305, by photoetching process and etch step for example dry etching remove a part of porous low k material and hard mask layer, form elliptical cylinder-shape, the erose hole that cylindrical or other any formation mtj structure is required.In step 306, on described hard mask layer and in the hole of described porous low k material and hard mask layer formation, deposition oxide is to fill hole.In step 307, with described oxide surface polishing, the oxide that major part is unnecessary is removed, and removes hard mask layer by chemical mechanical milling method.In step 308, remove described porous low k material, form the column structure of the required form of oxide formation.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just is used for for example and the purpose of explanation, but not is intended to the present invention is limited in described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (10)
1. the manufacture method of a magnetic funnel node device comprises:
Semiconductor substrate is provided;
Form the MTJ stepped construction on described Semiconductor substrate;
Form advanced low-k materials on described formation MTJ stepped construction;
Form the hard mask layer of patterning on described advanced low-k materials;
Take the hard mask layer of described patterning as mask, remove a part of described advanced low-k materials by etch step, form hole in described advanced low-k materials;
Deposition oxide on described hard mask layer and in described hole;
Remove the outer described oxide of described hole by the cmp step, with described oxide surface polishing, and remove described hard mask layer;
Remove described advanced low-k materials, form the column structure that described oxide consists of.
2. method according to claim 1, wherein said Semiconductor substrate comprise transistor and are used for being electrically connected to described transistor and the interconnect architecture of the MTJ unit of formation subsequently.
3. method according to claim 1, wherein said MTJ stepped construction comprises at least fixed magnetic layer, tunnel barrier layer and freely rotates magnetosphere.
4. method according to claim 1, wherein said advanced low-k materials is the porous low dielectric constant material.
5. method according to claim 4, is characterized in that, adopts the described porous ultra-low dielectric constant material of spin coating method deposition.
6. method according to claim 4, is characterized in that, also is included in to form the polymer penetration step of carrying out after described advanced low-k materials.
7. method according to claim 1, wherein said hard mask layer is titanium nitride (TiN) or boron nitride (BN).
8. method according to claim 1, wherein said etch step is dry etching.
9. according to claim 1 or 6 described methods, is characterized in that, after carrying out described cmp step, also comprises heating steps.
10. method according to claim 1, wherein said column structure is elliptical cylinder-shape or cylindrical.
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| CN201110371148.2A CN103123954B (en) | 2011-11-21 | 2011-11-21 | A kind of manufacture method of magnetic funnel node device |
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| CN201110371148.2A CN103123954B (en) | 2011-11-21 | 2011-11-21 | A kind of manufacture method of magnetic funnel node device |
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| CN103123954B CN103123954B (en) | 2015-11-25 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104659201A (en) * | 2013-11-22 | 2015-05-27 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing magnetoresistive memory unit |
| CN105830155A (en) * | 2013-12-17 | 2016-08-03 | 高通股份有限公司 | Hybrid synthetic antiferromagnetic layer for perpendicular magnetic tunnel junction (mtj) |
| CN107785485A (en) * | 2016-08-31 | 2018-03-09 | 中电海康集团有限公司 | A kind of preparation method of MTJ |
| CN110678995A (en) * | 2017-04-21 | 2020-01-10 | 艾沃思宾技术公司 | Method of integrating a magnetoresistive device |
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| KR20030001109A (en) * | 2001-06-28 | 2003-01-06 | 주식회사 하이닉스반도체 | A fabricating method of capacitor using low-k sacrificial layer |
| US20060022286A1 (en) * | 2004-07-30 | 2006-02-02 | Rainer Leuschner | Ferromagnetic liner for conductive lines of magnetic memory cells |
| CN101060079A (en) * | 2006-04-21 | 2007-10-24 | 台湾积体电路制造股份有限公司 | Method of forming a low-K dielectric thin film |
| US20110089511A1 (en) * | 2007-02-12 | 2011-04-21 | Avalanche Technology, Inc. | Magnetic Random Access Memory (MRAM) Manufacturing Process for a Small Magnetic Tunnel Junction (MTJ) Design with a Low Programming Current Requirement |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20030001109A (en) * | 2001-06-28 | 2003-01-06 | 주식회사 하이닉스반도체 | A fabricating method of capacitor using low-k sacrificial layer |
| US20060022286A1 (en) * | 2004-07-30 | 2006-02-02 | Rainer Leuschner | Ferromagnetic liner for conductive lines of magnetic memory cells |
| CN101060079A (en) * | 2006-04-21 | 2007-10-24 | 台湾积体电路制造股份有限公司 | Method of forming a low-K dielectric thin film |
| US20110089511A1 (en) * | 2007-02-12 | 2011-04-21 | Avalanche Technology, Inc. | Magnetic Random Access Memory (MRAM) Manufacturing Process for a Small Magnetic Tunnel Junction (MTJ) Design with a Low Programming Current Requirement |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104659201A (en) * | 2013-11-22 | 2015-05-27 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing magnetoresistive memory unit |
| CN105830155A (en) * | 2013-12-17 | 2016-08-03 | 高通股份有限公司 | Hybrid synthetic antiferromagnetic layer for perpendicular magnetic tunnel junction (mtj) |
| CN105830155B (en) * | 2013-12-17 | 2018-11-09 | 高通股份有限公司 | Mixing synthetic anti-ferromagnetic layer for vertical magnetism tunnel knot (MTJ) |
| CN107785485A (en) * | 2016-08-31 | 2018-03-09 | 中电海康集团有限公司 | A kind of preparation method of MTJ |
| CN107785485B (en) * | 2016-08-31 | 2021-06-01 | 中电海康集团有限公司 | Preparation method of magnetic tunnel junction |
| CN110678995A (en) * | 2017-04-21 | 2020-01-10 | 艾沃思宾技术公司 | Method of integrating a magnetoresistive device |
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| CN103123954B (en) | 2015-11-25 |
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