CN103123929B - The domain structure of the high withstand voltage field effect transistor of isolated form - Google Patents
The domain structure of the high withstand voltage field effect transistor of isolated form Download PDFInfo
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- CN103123929B CN103123929B CN201110371064.9A CN201110371064A CN103123929B CN 103123929 B CN103123929 B CN 103123929B CN 201110371064 A CN201110371064 A CN 201110371064A CN 103123929 B CN103123929 B CN 103123929B
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Abstract
The invention discloses the domain structure of the high withstand voltage field effect transistor of a kind of isolated form, comprise drain region, source region, drift region, drain region, drift region, source region polysilicon field plate and grid and drain region polysilicon field plate; Source region polysilicon field plate and grid are double-deck U-shaped structure inside and outside being connected by circular arc field plate, and the opening part of U-shaped structure is closed; The drain region polysilicon field plate closed is inside and outside source region polysilicon field plate and grid between double-deck U-shaped structure; Drain region is positioned at closed drain region polysilicon field plate, drift region, drain region is at source region polysilicon field plate and between grid and drain region polysilicon field plate, source region is outside the skin of source region polysilicon field plate and grid and between internal layer and skin, described source region and drain region are positioned at drift region, and source region and silicon substrate substrate are by separated drift regions.The present invention utilizes whole encirclement drain region, source region, and increases field plate at device afterbody, by drift region, encirclement drain region, P type doped region, prevents electric field from concentrating, improves device electric breakdown strength.
Description
Technical field
The present invention relates to semiconductor integrated circuit field, particularly the high withstand voltage field effect transistor domain structure of a kind of isolated form.
Background technology
The high withstand voltage N-type field effect transistor of the isolated form formed on P-type silicon substrate substrate 301 used at present, cross section as shown in Figure 2, P-type silicon substrate substrate 101 is formed the drift region 102 of N-type, described drift region 102 comprises drift region, drain region 203, drift region, described drain region 203 is drawn by the first active area 107 of N-type and is formed drain region 201, generate in drift region, drain region 203 and have an oxygen isolation 105, the below of field oxygen isolation 105 forms the first doped region 104 of P type, when drain region 201 adds high pressure, P type first doped region 104 provides the electronics neutralization of hole more easily and in drift region, drain region 203, produce depletion region to improve the withstand voltage of drain region 201.The well region 103 of P type is formed in P-type silicon substrate substrate 101, well region 103 is drawn by the 3rd active area 108 of P type, source is formed by the second active area 106 of N-type, second active area 106 is connected with the 3rd active area 108 and forms source region 202, be formed with the second doped region 104a of P type below source region 202, the second doped region 104a and field oxygen are isolated between the first doped region 104 under 105 segment distance.Described source region 202 is positioned at the inside of drift region 102, and well region 103 and P-type silicon substrate substrate 101 are isolated by N-type drift region 102.
Field oxygen isolation 105 is coated with source region polysilicon field plate and grid 109 above the one end in source region 202, its one end covers the first doped region 104 on the region in source region 202, and the other end covers the second doped region 104a on the region of drift region, drain region 203.Field oxygen isolation 105 is coated with drain region polysilicon field plate 110 above the one end in drain region 201, and described drain region polysilicon field plate 110 is connected with the first active area 107 by Metal field plate 112.Be provided with Metal field plate 113 with Metal field plate 111 at a distance of a segment distance place, described Metal field plate 113 is connected with grid polycrystalline silicon, both forms Metal field plate, again because with gate connected in parallel and reduce resistance.
The surface plate graph structure of above-mentioned isolated form field effect transistor as shown in Figure 1, the cross section that B '-B ' and C '-C ' locates is as Fig. 2 structure, above the source of device afterbody, the cross section at (A ' place in Fig. 1) as shown in Figure 3, there is no source region polysilicon field plate, therefore electric field concentrates on herein, easily causes device breakdown to reduce.
Summary of the invention
The technical problem to be solved in the present invention is to provide the domain structure of the high withstand voltage field effect transistor of a kind of isolated form, can improve the problem that device afterbody electric field is concentrated, and improves the puncture voltage of device.
For solving the problems of the technologies described above, the domain structure of the high withstand voltage field effect transistor of isolated form of the present invention, comprises drain region, source region, drift region, drain region, drift region, source region polysilicon field plate and grid and drain region polysilicon field plate;
Described source region polysilicon field plate and grid are double-deck U-shaped structure inside and outside being connected by circular arc field plate, and the opening part of U-shaped structure is closed by source region polysilicon field plate and grid; Described drain region polysilicon field plate is also the U-shaped structure of inside and outside bilayer, and inside and outside bilayer is connected by circular arc field plate, and drain region polysilicon field plate is inside and outside source region polysilicon field plate and grid between double-deck U-shaped structure;
Described drain region is positioned at closed drain region polysilicon field plate, drift region, drain region is at source region polysilicon field plate and between grid and drain region polysilicon field plate, source region is outside the skin of source region polysilicon field plate and grid and between internal layer and skin, described source region and drain region are positioned at drift region, and source region and silicon substrate substrate are by separated drift regions.
Wherein, closed by source region polysilicon field plate and grid inside and outside the field effect transistor at double-deck U-shaped structural openings place be:
The well region with the first conduction type is formed in described silicon substrate substrate, well region is drawn by the 3rd active area with the first conduction type, source is formed by second active area with the second conduction type, second active area is connected with the 3rd active area and forms source region, is formed with second doped region with the first conduction type below source region;
The silicon substrate substrate with the first conduction type is formed the drift region that has second conduction type contrary with the first conduction type, described drift region comprises drift region, drain region, generate in drift region, drain region and have an oxygen isolation, one end of field oxygen isolation is arranged in drift region, the other end is positioned at outside drift region, the below of field oxygen isolation forms the 3rd doped region with the first conduction type, a segment distance is had between 3rd doped region and the second doped region, 3rd doped region is positioned at outside drift region away from the one end in source region and surrounds drift region, and is connected with silicon substrate substrate;
Described source region is positioned at the inside of drift region, and well region and the second doped region are positioned at the drift region below source region, and pass through separated drift regions between silicon substrate substrate.
Further, the described 3rd doped region width be positioned at outside drift region is 2 μm.
Wherein, the field effect transistor that in domain structure, double-deck U-shaped structural openings sentences external position inside and outside being closed by source region polysilicon field plate and grid is:
The silicon substrate substrate with the first conduction type is formed the drift region that has second conduction type contrary with the first conduction type, described drift region comprises drift region, drain region, drift region, described drain region is drawn by first active area with the second conduction type and is formed drain region, generate in drift region, drain region and have an oxygen isolation, the below of field oxygen isolation forms first doped region with the first conduction type;
The well region with the first conduction type is formed in described silicon substrate substrate, well region is drawn by the 3rd active area with the first conduction type, source is formed by second active area with the second conduction type, second active area is connected with the 3rd active area and forms source region, be formed with second doped region with the first conduction type below source region, the second doped region and field oxygen isolation under the first doped region between have a segment distance;
Described source region is positioned at the inside of drift region, and well region and silicon substrate substrate are by separated drift regions.
Further, oxygen isolation in described field is coated with source region polysilicon field plate and grid above the one end in source region, and its one end covers the first doped region on the region in source region, and the other end covers the second doped region on the region of drift region, drain region; The oxygen isolation of described field is coated with drain region polysilicon field plate above the one end in drain region, and described drain region polysilicon field plate is connected with the first active area by Metal field plate; Be provided with Metal field plate with Metal field plate at a distance of a segment distance place, described Metal field plate is connected with grid polycrystalline silicon.
Further, described first conduction type is P type, and the second conduction type is N-type, or described first conduction type is N-type, and the second conduction type is P type.
Beneficial effect of the present invention is:
1. the high withstand voltage field effect transistor of isolated form of the present invention can realize the substrate of field effect transistor and the substrate isolation of silicon substrate, and the current potential of the substrate of field effect transistor can not affect by the current potential of silicon substrate substrate, independently add current potential;
2., in domain structure of the present invention, utilize whole encirclement drain region, source region, use circular sliding slopes around the corner, the structure in cross section, circular arc place is consistent with the structure of the high withstand voltage field effect transistor of isolated form, and increase field plate at device afterbody, by drift region, encirclement drain region, P type doped region, improve device electric breakdown strength.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is the surface plate figure structure schematic representation of the high withstand voltage field effect transistor of existing isolated form;
Fig. 2 is the schematic cross-section of the high withstand voltage field effect transistor of isolated form that in Fig. 1, B '-B ' locates and C '-C ' locates;
Fig. 3 is the schematic cross-section of the high withstand voltage field effect transistor of isolated form at A ' place in Fig. 1;
Fig. 4 is the surface plate figure structure schematic representation of the high withstand voltage field effect transistor of isolated form of the present invention;
Fig. 5 is the schematic cross-section of the high withstand voltage field effect transistor of isolated form at B-B place and C-C place in Fig. 4;
Fig. 6 is the schematic cross-section of the high withstand voltage field effect transistor of isolated form at A place in Fig. 4.
Embodiment
The domain structure of the high withstand voltage field effect transistor of isolated form of the present invention, as shown in Figure 4, comprises drain region 201, source region 202, drift region, drain region 203, drift region 102, source region polysilicon field plate and grid 109 and drain region polysilicon field plate 110; Described source region polysilicon field plate and grid 109 are double-deck U-shaped structure inside and outside being connected by circular arc field plate, and the opening part of U-shaped structure is closed by source region polysilicon field plate and grid 109; Described drain region polysilicon field plate 110 is also the U-shaped structure of inside and outside bilayer, and inside and outside bilayer is connected by circular arc field plate, and drain region polysilicon field plate 110 is inside and outside source region polysilicon field plate and grid 109 between double-deck U-shaped structure; Described drain region 201 is positioned at closed drain region polysilicon field plate 110, drift region, drain region 203 is at source region polysilicon field plate and between grid 109 and drain region polysilicon field plate 110, source region 202 is outside the skin of source region polysilicon field plate and grid 109 and between internal layer and skin, described source region 202 and drain region 201 are positioned at drift region 102, and source region 202 and silicon substrate substrate 101 are isolated by drift region 102.
Wherein, as shown in Figure 6, closed by source region polysilicon field plate and grid 109 inside and outside the field effect transistor of double-deck U-shaped structural openings place A be:
The well region 103 of P type is formed in described silicon substrate substrate 101, well region 103 is drawn by the 3rd active area 108 of P type, source is formed by the second active area 106 of N-type, second active area 106 is connected with the 3rd active area 108 and forms source region 202, is formed with the second doped region 104a of P type below source region 202;
The silicon substrate substrate 101 of P type is formed the drift region 102 of N-type, described drift region 102 comprises drift region, drain region 203, generate in drift region, drain region 203 and have an oxygen isolation 105, one end of field oxygen isolation 105 is arranged in drift region 102, the other end is positioned at outside drift region 102, the below of field oxygen isolation 105 forms the 3rd doped region 104b of P type, a segment distance is had between 3rd doped region 104b and the second doped region 104a, 3rd doped region 104b is positioned at outer encirclement drift region 102, drift region 102 away from the one end in source region 202, and is connected with silicon substrate substrate 101;
Described source region 202 is positioned at the inside of drift region 102, well region 103 and the second doped region 104a are positioned at the drift region 102 below source region 202, and isolated by drift region 102 between silicon substrate substrate 101, whole drain region is communicated with the 3rd doped region 104b by N-type drift region 102.
The described 3rd doped region 104b width be positioned at outside drift region 102 is 2 μm, is encased drift region 102 by the 3rd doped region 104b, ensures N-type diffusion to exhaust completely, improves withstand voltage.
In domain structure, except the U-shaped closure of openings place A of source region polysilicon field plate and grid 109, the high withstand voltage field effect transistor of all the other isolated forms everywhere, as shown in Figure 5, P-type silicon substrate substrate 101 is formed the drift region 102 of N-type, described drift region 102 comprises drift region, drain region 203, drift region, described drain region 203 is drawn by the first active area 107 of N-type and is formed drain region 201, generate in drift region, drain region 203 and have an oxygen isolation 105, the below of field oxygen isolation 105 forms the first doped region 104 of P type, when drain region 201 adds high pressure, P type first doped region 104 provides the electronics neutralization of hole more easily and in drift region, drain region 203, produce depletion region to improve the withstand voltage of drain region 201.
The well region 103 of P type is formed in P-type silicon substrate substrate 101, well region 103 is drawn by the 3rd active area 108 of P type, source is formed by the second active area 106 of N-type, second active area 106 is connected with the 3rd active area 108 and forms source region 202, be formed with the second doped region 104a of P type below source region 202, the second doped region 104a and field oxygen are isolated between the first doped region 104 under 105 segment distance.
Described source region 202 is positioned at the inside of drift region 102, and well region 103 and P-type silicon substrate substrate 101 are isolated by N-type drift region 102.
Field oxygen isolation 105 is coated with source region polysilicon field plate and grid 109 above the one end in source region 202, its one end covers the first doped region 104 on the region in source region 202, and the other end covers the second doped region 104a on the region of drift region, drain region 203.
Field oxygen isolation 105 is coated with drain region polysilicon field plate 110 above the one end in drain region 201, and described drain region polysilicon field plate 110 is connected with the first active area 107 by Metal field plate 112.
Be provided with Metal field plate 113 with Metal field plate 111 at a distance of a segment distance place, described Metal field plate 113 is connected with grid polycrystalline silicon, both forms Metal field plate, again because with gate connected in parallel and reduce resistance.
In the high withstand voltage field effect transistor of above-mentioned N-type, convert each implanted layer ionic type, the high withstand voltage field effect transistor of P type can be formed.
The high withstand voltage field effect transistor of isolated form of the present invention can realize the substrate of field effect transistor and the substrate isolation of silicon substrate, and the current potential of the substrate of field effect transistor can not affect by the current potential of silicon substrate substrate, independently add current potential; In domain structure of the present invention, utilize whole encirclement drain region, source region, use circular sliding slopes around the corner, the structure in cross section, circular arc place is consistent with the structure of the high withstand voltage field effect transistor of isolated form, and increase field plate at device afterbody, by drift region, encirclement drain region, P type doped region, improve device electric breakdown strength.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (6)
1. the domain structure of the high withstand voltage field effect transistor of isolated form, it is characterized in that, comprise drain region (201), source region (202), drift region, drain region (203), drift region (102), source region polysilicon field plate and grid (109) and drain region polysilicon field plate (110);
Described source region polysilicon field plate and grid (109) are double-deck U-shaped structure inside and outside being connected by circular arc field plate, and the opening part of U-shaped structure is closed by source region polysilicon field plate and grid (109); Described drain region polysilicon field plate (110) is also the U-shaped structure of inside and outside bilayer, inside and outside bilayer is connected by circular arc field plate, and drain region polysilicon field plate (110) is positioned between the U-shaped structure of inside and outside bilayer of source region polysilicon field plate and grid (109);
Described drain region (201) is positioned at closed drain region polysilicon field plate (110), drift region, drain region (203) is positioned at source region polysilicon field plate and between grid (109) and drain region polysilicon field plate (110), outside the skin that source region (202) is positioned at source region polysilicon field plate and grid (109) and between internal layer and skin, described source region (202) and drain region (201) are positioned at drift region (102), and source region (202) and silicon substrate substrate (101) are isolated by drift region (102).
2. the domain structure of the high withstand voltage field effect transistor of isolated form according to claim 1, is characterized in that, the field effect transistor of the U-shaped structural openings place (A) of inside and outside bilayer closed by source region polysilicon field plate and grid (109) is:
The well region (103) with the first conduction type is formed in described silicon substrate substrate (101), well region (103) is drawn by the 3rd active area (108) with the first conduction type, source is formed by second active area (106) with the second conduction type, second active area (106) is connected with the 3rd active area (108) and forms source region (202), and source region (202) below is formed with second doped region (104a) with the first conduction type;
The upper formation one of silicon substrate substrate (101) with the first conduction type has the drift region (102) of second conduction type contrary with the first conduction type, described drift region (102) comprises drift region, drain region (203), generate in drift region, drain region (203) and have oxygen isolation (105), one end of field oxygen isolation (105) is arranged in drift region (102), the other end is positioned at drift region (102) outward, the below of field oxygen isolation (105) forms the 3rd doped region (104b) with the first conduction type, a segment distance is had between 3rd doped region (104b) and the second doped region (104a), 3rd doped region (104b) is positioned at drift region (102) away from the one end of source region (202) and surrounds drift region (102) outward, and be connected with silicon substrate substrate (101),
Described source region (202) is positioned at the inside of drift region (102), well region (103) and the second doped region (104a) are positioned at the drift region (102) of below, source region (202), and are isolated by drift region (102) between silicon substrate substrate (101).
3. the domain structure of the high withstand voltage field effect transistor of isolated form according to claim 2, it is characterized in that, it is 2 μm that described 3rd doped region (104b) is positioned at drift region (102) width outward.
4. the domain structure of the high withstand voltage field effect transistor of isolated form according to claim 1, it is characterized in that, in domain structure the U-shaped structural openings place (A) of inside and outside bilayer closed by source region polysilicon field plate and grid (109) with the field effect transistor of external position be:
There is in the upper formation one of the silicon substrate substrate (101) with the first conduction type the drift region (102) of second conduction type contrary with the first conduction type, described drift region (102) comprises drift region, drain region (203), drift region, described drain region (203) is drawn by first active area (107) with the second conduction type and is formed drain region (201), generate in drift region, drain region (203) and have oxygen isolation (105), the below of field oxygen isolation (105) forms first doped region (104) with the first conduction type;
The well region (103) with the first conduction type is formed in described silicon substrate substrate (101), well region (103) is drawn by the 3rd active area (108) with the first conduction type, source is formed by second active area (106) with the second conduction type, second active area (106) is connected with the 3rd active area (108) and forms source region (202), below, source region (202) is formed with second doped region (104a) with the first conduction type, second doped region (104a) and field oxygen are isolated between the first doped region (104) under (105) a segment distance,
Described source region (202) is positioned at the inside of drift region (102), and well region (103) and silicon substrate substrate (101) are isolated by drift region (102).
5. the domain structure of the high withstand voltage field effect transistor of isolated form according to claim 4, is characterized in that,
Described field oxygen isolation (105) is coated with source region polysilicon field plate and grid (109) above the one end in source region (202), its one end covers the first doped region (104) on the region in source region (202), and the other end covers the second doped region (104a) on the region of drift region, drain region (203);
Described field oxygen isolation (105) is coated with drain region polysilicon field plate (110) above the one end in drain region (201), and described drain region polysilicon field plate (110) is connected with the first active area (107) by Metal field plate (112);
Be provided with Metal field plate (113) with Metal field plate (111) at a distance of a segment distance place, described Metal field plate (113) is connected with grid polycrystalline silicon.
6. the domain structure of the high withstand voltage field effect transistor of the isolated form according to Claims 2 or 3 or 4 or 5, it is characterized in that, described first conduction type is P type, and the second conduction type is N-type, or described first conduction type is N-type, and the second conduction type is P type.
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| CN201110371064.9A CN103123929B (en) | 2011-11-21 | 2011-11-21 | The domain structure of the high withstand voltage field effect transistor of isolated form |
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| CN103123929B true CN103123929B (en) | 2015-10-14 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5040045A (en) * | 1990-05-17 | 1991-08-13 | U.S. Philips Corporation | High voltage MOS transistor having shielded crossover path for a high voltage connection bus |
| CN1424770A (en) * | 2003-01-08 | 2003-06-18 | 东南大学 | Transverse buffer P-type MOS transistors |
| CN1849710A (en) * | 2004-02-24 | 2006-10-18 | 崇贸科技股份有限公司 | High voltage ldmos transistor having an isolated structure |
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- 2011-11-21 CN CN201110371064.9A patent/CN103123929B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5040045A (en) * | 1990-05-17 | 1991-08-13 | U.S. Philips Corporation | High voltage MOS transistor having shielded crossover path for a high voltage connection bus |
| CN1424770A (en) * | 2003-01-08 | 2003-06-18 | 东南大学 | Transverse buffer P-type MOS transistors |
| CN1849710A (en) * | 2004-02-24 | 2006-10-18 | 崇贸科技股份有限公司 | High voltage ldmos transistor having an isolated structure |
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