CN103117305A - Fin type field-effect tube and substrate thereof - Google Patents
Fin type field-effect tube and substrate thereof Download PDFInfo
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- CN103117305A CN103117305A CN2011103637751A CN201110363775A CN103117305A CN 103117305 A CN103117305 A CN 103117305A CN 2011103637751 A CN2011103637751 A CN 2011103637751A CN 201110363775 A CN201110363775 A CN 201110363775A CN 103117305 A CN103117305 A CN 103117305A
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Abstract
The invention discloses a fin type field-effect tube Fin field effect transistor (FET) substrate. The fin type field-effect tube FinFET substrate is in a fin structure, and comprises a source region which is provided with a channel region in the middle in an extending mode, and a drain region, and is a multilayer stress silicon layer. The invention further discloses a FinFET which comprises the fin type field-effect tube FinFET substrate. The fin type field-effect tube FinFET substrate and the FinFET can further improve drive currents of the fin type field-effect tube FinFET substrate and the FinFET.
Description
Technical field
The present invention relates to the manufacturing technology of semiconductor device, particularly a kind of fin field effect pipe (FinFET) and matrix thereof.
Background technology
Along with the development of semiconductor technology, the performance of semiconductor device steadily improves.The performance of semiconductor device improves and mainly realizes by the characteristic size of constantly dwindling semiconductor device, and the characteristic size of semiconductor device has narrowed down to Nano grade.Semiconductor device is under this characteristic size, and conventional planar is made the method for semiconductor device, and namely the manufacture method of single gate semiconductor device can't be suitable for, so the manufacture method of multiple-grid semiconductor device occurred.Compare with the manufacture method of single gate semiconductor device, the multiple-grid semiconductor device has stronger short channel and suppresses ability, better subthreshold characteristic, higher driving force and can bring higher current densities.
At present, fin field effect pipe (FinFET) is widely used as the representative of multiple-grid semiconductor device, and FinFET is divided into double grid FinFET and three gate FinFETs, and double grid FinFET wherein is widely used.
Fig. 1 is the perspective view of prior art double grid FinFET.
As shown in Figure 1, FinFET is positioned on substrate 100, comprises matrix 101 and grid structure 102 with fin structure, and wherein each fin is rectangular-shaped, is respectively source region 103 and drain region 104, and the centre of fin structure is extended with channel region 105.In prior art, matrix 101 is formed by monocrystalline silicon layer, and substrate 100 is also formed by monocrystalline silicon layer.Grid structure 102 comprises gate oxide (not shown) and conductive grid.
Wherein, the fin structure of matrix 101 forms through patterning, and its forming process is:
At first, deposition mask layer on monocrystalline silicon layer, after applying the photoresistance glue-line on mask layer, after applying the photoresistance glue-line, the light shield exposure that employing has a fin structure develops, form the photoresistance glue-line of fin structure pattern on the photoresistance glue-line, then take photoresistance glue-line with fin structure pattern as mask, the etch mask layer obtains having the mask layer of fin structure pattern;
Then, for blocking, the etching single crystal silicon layer obtains having the matrix of fin structure, removes remaining mask layer with mask layer with fin structure pattern.
Wherein, the mask layer with fin structure pattern is preferably hard mask, can be silicon nitride layer, also can adopt the nano impression mode to form.
Grid structure 102 forming processes:
At channel region 105 surface formation gate oxides, gate oxide covers sidewall and the top of channel region;
Deposit spathic silicon layer on the substrate 100 that comprises matrix 101, and carry out planarization, then the patterned polysilicon layer, form the conductive grid around the gate oxide surface.
Although single gate semiconductor device that the FinFET that has stereochemical structure in Fig. 1 makes than the plane has higher drive current, optimizes the service behaviour of FinFET, further improves its drive current, become in the industry an especially problem of concern.
Summary of the invention
In view of this, the invention provides a kind of FinFET and matrix thereof, the FinFET with this matrix can realize higher drive current.
Technical scheme of the present invention is achieved in that
The invention provides a kind of fin field effect pipe FinFET matrix, this matrix is fin structure, comprises its middle source region and drain region that is extended with channel region, and this matrix is the multilayer stressed silicon layer.
Described multilayer stressed silicon layer to lower and on comprise monocrystalline silicon layer, germanium-silicon layer and/or silicon carbon layer.
Described multilayer stressed silicon layer to lower and on comprise monocrystalline silicon layer, silicon carbon layer and germanium-silicon layer.
Described silicon carbon layer and germanium-silicon layer are epitaxial loayer or ion implanted layer.
The Ge content of described germanium-silicon layer is 5%～35%; The carbon content of described silicon carbon layer is 3%～15%.
The top layer of described multilayer stressed silicon layer further comprises the top monocrystalline silicon layer.
The thickness of described top monocrystalline silicon layer is 5nm～50nm.
Wherein each fin is funnel-form, and each funnel comprises head and afterbody, and its afterbody extension connects and composes channel region.
The present invention also provides a kind of fin field effect pipe FinFET, comprises the FinFET matrix as above and the grid structure that are positioned on substrate; Wherein, described grid structure is surperficial around the channel region in the middle of fin structure, and this surface comprises sidewall and the top of channel region.
Described FinFET is a plurality of, and wherein, the fin structure of each FinFET is arranged in parallel, and each grid structure interconnects in alignment.
Can find out from such scheme, FinFET matrix provided by the invention is the multilayer stressed silicon layer, the material of every layer is different, stress distribution is not identical yet, the stressed silicon layer of multilayer combination has the compression higher than traditional silicon substrate, and then electronics or the hole channel region on matrix is when moving, have the carrier mobility higher than traditional silicon raceway groove, so the present invention utilizes the stress silicon channel layer to realize higher drive current in FinFET.
Description of drawings
Fig. 1 is the perspective view of prior art double grid FinFET.
Fig. 2 is the perspective view of embodiment of the present invention FinFET.
The perspective view that Fig. 3 grid structure that to be a plurality of FinFET of the embodiment of the present invention be made of straight line is controlled.
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in further detail.
The FinFET matrix adopting stressed silicon layer of multilayer, the material of every layer is different, stress distribution is not identical yet, the stressed silicon layer of multilayer combination, have the compression higher than traditional silicon substrate, and then electronics or the hole channel region on matrix have the carrier mobility higher than traditional silicon raceway groove, so the present invention utilizes the stress silicon channel layer to realize higher drive current in FinFET when moving.Further, each fin of FinFET matrix of the present invention has funnel-form, and each funnel comprises head and afterbody, and its afterbody extension connects and composes channel region.After grid structure rides on the matrix channel region like this, ride over the edge of funnel afterbody, further improved the compression of channel region, thereby further realize higher drive current in FinFET.
FinFET matrix of the present invention is no longer single monocrystalline silicon layer, but has comprised the stressed silicon layer of multilayer.The below enumerates embodiment and describes.
Embodiment one: the multilayer stressed silicon layer to lower and on comprise monocrystalline silicon layer and germanium-silicon layer.
Embodiment two: the multilayer stressed silicon layer to lower and on comprise monocrystalline silicon layer and silicon carbon layer.
Embodiment three: the multilayer stressed silicon layer to lower and on comprise monocrystalline silicon layer, germanium-silicon layer and silicon carbon layer.
Embodiment four: the multilayer stressed silicon layer to lower and on comprise monocrystalline silicon layer, silicon carbon layer and germanium-silicon layer.
Wherein, in each embodiment, silicon carbon layer thickness is 10nm～80nm; Germanium-silicon layer thickness is 20nm～100nm.
In addition, silicon carbon layer and germanium-silicon layer can have various ways to form.That is to say that silicon carbon layer and germanium-silicon layer can be epitaxial loayer or ion implanted layer, namely adopt the mode of extension or the mode of Implantation to form.Wherein, preferably, the Ge content of germanium-silicon layer is 5%～35%; The carbon content of described germanium-silicon layer is 3%～15%.Too much or very few germanium, carbon content is unfavorable for the raising of channel layer mobility, because the stress that very few content produces is very weak, being difficult to produce a certain amount of type becomes, and too much content can produce the defective that is difficult to repair, thereby cause the release of stress in annealing process, be unfavorable for the improvement of carrier mobility;
Further, the top layer of multilayer stressed silicon layer can also comprise the top monocrystalline silicon layer.This top monocrystalline silicon layer is very thin, and thickness is 5nm～50nm.Gate oxide covering matrix channel region due to the subsequent gate structure, and the adhesion of monocrystalline silicon layer and gate oxide, adhesion than other materials and gate oxide is better, so the top layer that the preferred embodiment of the present invention is the multilayer stressed silicon layer also comprises the top monocrystalline silicon layer, namely monocrystalline silicon layer directly contacts with gate oxide.
Fig. 2 is the perspective view of embodiment of the present invention FinFET.
In this embodiment, FinFET is positioned on substrate 100, and substrate still can be monocrystalline silicon layer.FinFET comprises matrix 201 and the grid structure 202 with fin structure.Wherein, matrix 201 is for comprising the multilayer stressed silicon layer of monocrystalline silicon layer 206, germanium-silicon layer 207 and silicon carbon layer 208 on extremely lower.Wherein, each fin is funnel-form, is respectively source region 203 and drain region 204, and each funnel comprises the afterbody that head is narrower with relative head, and its afterbody extension connects and composes channel region 205.Same as the prior art, grid structure 202 comprises gate oxide (not shown) and conductive grid.
Compared to Figure 1, except matrix be consisted of by the multilayer stressed silicon layer, difference also is the funnel-form that is shaped as of fin, and is different just because of the light shield shape with fin structure, finally will produce the matrix of respective shapes.Further, this embodiment is preferably channel region 205 and is just covered by grid structure 202 on width.Confirm to have the FinFET of this funnel-form matrix through overtesting, grid structure 202 rides over the edge of funnel afterbody, can further improve the compression of raceway groove.
The fin structure of matrix 201 forms through patterning, and its forming process is:
At first, form the multilayer stressed silicon layer of matrix, deposition mask layer on the multilayer stressed silicon layer after applying the photoresistance glue-line on mask layer, develops after adopting the light shield exposure with fin structure to apply the photoresistance glue-line, wherein, each fin with light shield of fin structure is funnel-form, forms the photoresistance glue-line of fin structure pattern on the photoresistance glue-line, then take photoresistance glue-line with fin structure pattern as mask, the etch mask layer obtains having the mask layer of fin structure pattern;
Then, for blocking, etching multilayer stressed silicon layer obtains having the matrix of fin structure, removes remaining mask layer with mask layer with fin structure pattern.
Wherein, the mask layer with fin structure pattern is preferably hard mask, can be silicon nitride layer, also can adopt the nano impression mode to form.
At channel region 205 surface formation gate oxides, gate oxide covers sidewall and the top of channel region;
Deposit spathic silicon layer on the substrate 100 that comprises matrix 201, and carry out planarization, then the patterned polysilicon layer, form the conductive grid around the gate oxide surface.
Wherein, described grid structure is surperficial around the channel region in the middle of fin structure, and this surface comprises sidewall and the top of channel region.
Further, gate oxide is preferably high-k (HK) material, and its effective oxide thickness of the gate oxide of HK material is very thin, can be good at controlling raceway groove, thereby further improves the raceway groove compression.
The present invention can also be controlled a plurality of FinFET by the grid structure that straight line consists of, thereby effectively improves device operation current, improves the integrated level of circuit, and can effectively improve the consistency of photoengraving pattern.
The perspective view that Fig. 3 grid structure that to be 2 FinFET of the embodiment of the present invention be made of straight line is controlled.Wherein, the fin structure of a FinFET301 and the 2nd FinFET302 is arranged in parallel, and each grid structure interconnects in alignment, forms grid structure 303.
The above is only preferred embodiment of the present invention, and is in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, is equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.
Claims (10)
1. fin field effect pipe FinFET matrix, this matrix is fin structure, comprises the source region and the drain region that are extended with channel region in the middle of it, it is characterized in that, this matrix is the multilayer stressed silicon layer.
2. matrix as claimed in claim 1, is characterized in that, described multilayer stressed silicon layer to lower and on comprise monocrystalline silicon layer, germanium-silicon layer and/or silicon carbon layer.
3. matrix as claimed in claim 1, is characterized in that, described multilayer stressed silicon layer to lower and on comprise monocrystalline silicon layer, silicon carbon layer and germanium-silicon layer.
4. matrix as claimed in claim 2 or claim 3, is characterized in that, described silicon carbon layer and germanium-silicon layer are epitaxial loayer or ion implanted layer.
5. matrix as claimed in claim 4, is characterized in that, the Ge content of described germanium-silicon layer is 5%～35%; The carbon content of described silicon carbon layer is 3%～15%.
6. matrix as claimed in claim 5, is characterized in that, the top layer of described multilayer stressed silicon layer further comprises the top monocrystalline silicon layer.
7. matrix as claimed in claim 6, is characterized in that, the thickness of described top monocrystalline silicon layer is 5nm～50nm.
8. matrix as claimed in claim 1, is characterized in that, wherein each fin is funnel-form, and each funnel comprises head and afterbody, and its afterbody extension connects and composes channel region.
9. a fin field effect pipe FinFET, is characterized in that, comprises the FinFET matrix as described in claim 1 to 8 any one and the grid structure that are positioned on substrate; Wherein, described grid structure is surperficial around the channel region in the middle of fin structure, and this surface comprises sidewall and the top of channel region.
10. FinFET as claimed in claim 9, is characterized in that, described FinFET is a plurality of, and wherein, the fin structure of each FinFET is arranged in parallel, and each grid structure interconnects in alignment.
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| CN2011103637751A CN103117305A (en) | 2011-11-16 | 2011-11-16 | Fin type field-effect tube and substrate thereof |
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| CN2011103637751A CN103117305A (en) | 2011-11-16 | 2011-11-16 | Fin type field-effect tube and substrate thereof |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1645629A (en) * | 2004-01-17 | 2005-07-27 | 三星电子株式会社 | At least penta-sided-channel type of finfet transistor and manufacture thereof |
| CN101189730A (en) * | 2004-03-31 | 2008-05-28 | 英特尔公司 | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1645629A (en) * | 2004-01-17 | 2005-07-27 | 三星电子株式会社 | At least penta-sided-channel type of finfet transistor and manufacture thereof |
| CN101189730A (en) * | 2004-03-31 | 2008-05-28 | 英特尔公司 | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
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Application publication date: 20130522 |