CN103107796B - Clock data recovery circuit - Google Patents
Clock data recovery circuit Download PDFInfo
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- CN103107796B CN103107796B CN201110352019.9A CN201110352019A CN103107796B CN 103107796 B CN103107796 B CN 103107796B CN 201110352019 A CN201110352019 A CN 201110352019A CN 103107796 B CN103107796 B CN 103107796B
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Abstract
The present invention relates to a kind of clock data recovery circuit, it has PGC demodulation module and Frequency Locking module.The phase detectors of PGC demodulation module compare the phase place of input data crossfire and the phase place of date restoring clock pulse, with output calibration signal.Frequency Locking module carries out an integral processing and twice integral processing to export first integral phase error and frequency control signal to correction signal.PGC demodulation module, according to first integral phase error and correction signal, produces phase control signal.The oscillating circuit of Frequency Locking module, according to frequency control signal, produces at least one with reference to clock pulse.The phase converter of PGC demodulation module, according to phase control signal and with reference to clock pulse, exports date restoring clock pulse to phase detectors.
Description
Technical field
The present invention relates to a kind of clock data recovery circuit, particularly relate to a kind of based on received input data crossfire to produce the clock data recovery circuit with reference to clock signal.
Background technology
Fig. 1 shows existing clock-data recovery (ClockandDataRecovery; CDR) configuration diagram of circuit.Clock data recovery circuit 100 comprises coarse adjustment module 110 and fine tuning module 120.Coarse adjustment module 110 is in order to provide a coarse adjustment control voltage to fine tuning module 120, and fine tuning module 120 is in order to receive input data crossfire IN_DATA, and exports date restoring clock pulse CDR_CLK.
Coarse adjustment module 110 has crystal oscillator 111, phase-frequency detector 112, first low pass filter 113, first voltage controlled oscillator 114 and frequency eliminator 115.Crystal oscillator 111 produces with reference to clock pulse S by the mode of its crystal oscillation
rEF.Phase-frequency detector 112 is in order to compare with reference to clock pulse S
rEFphase place and the phase place of frequency elimination signal C4, and according to the result compared, export control signal C1.First low pass filter 113, by after control signal C1 filtering, exports control voltage C2.First voltage controlled oscillator 114 is according to control voltage C2, and vibration produces oscillator signal C3.Frequency eliminator 115, by after oscillator signal C3 frequency elimination, exports frequency elimination signal C4.
Fine tuning module 120 has phase detectors 121, second low pass filter 122 and the second voltage controlled oscillator 123.Phase detectors 121 in order to compare phase place and the frequency of input data crossfire IN_DATA and date restoring clock pulse CDR_CLK, and according to comparative result, export control signal C5.Second low pass filter 122, by after control signal C5 filtering, exports control voltage C6.The control voltage C2 that first low pass filter 113 exports after resistance R and electric capacity C process, can convert control voltage C7 to.Second voltage controlled oscillator 123 is according to control voltage C6 and control voltage C7, and vibration produces date restoring clock pulse CDR_CLK.Date restoring clock pulse CDR_CLK can be transferred into phase detectors 121.
Clock data recovery circuit 100 can recover input data crossfire IN_DATA according to date restoring clock pulse CDR_CLK, and produces (retimed) data crossfire of reclocking.In some specific specification, for guaranteeing the accuracy of the data that clock data recovery circuit 100 is recovered, the vibration (jitter) of the data crossfire of reclocking can not be excessive.Therefore, the reference clock pulse S that produces of crystal oscillator 111
rEFfrequency must be less than within the scope of certain compared to the error of the frequency of input data crossfire IN_DATA.With universal serial bus (UniversalSerialBus; USB) specification of 3.0 is example, with reference to clock pulse S
rEFfrequency and input data crossfire IN_DATA frequency between error must be less than 300ppm (note a: ppm equals 1,000,000/).Although the crystal oscillator of commercialization can produce the clock signal of frequency error lower than positive and negative 100ppm, and can be used as desirable clock signal source, this crystal oscillator expensive, and larger circuit board space can be occupied.
Summary of the invention
The invention provides a kind of clock data recovery circuit, it can by received input data crossfire, the reference clock pulse needed for generation, and can not need to use outside crystal oscillator.
The present invention proposes a kind of clock data recovery circuit, and it comprises phase detectors, first integral module, arithmetic element, second integral module, third integral module, oscillating circuit and phase converter.Phase detectors input the phase place of data crossfire and the phase place of date restoring clock pulse, with output calibration signal in order to compare.First integral module couples phase detectors, in order to correction signal is carried out integral processing, to export first integral phase error.Arithmetic element couples first integral module, in order to carry out computing to obtain operation values based on first integral phase error and correction signal.Second integral module couples arithmetic element, in order to carry out integral processing to operation values, to export phase control signal.Third integral module couples first integral module, in order to first integral phase error is carried out integral processing, with output frequency control signal.Oscillating circuit couples third integral module, in order to according to frequency control signal, produces at least one with reference to clock pulse.Phase converter couples oscillating circuit, second integral module and phase detectors, in order to according to phase control signal and with reference to clock pulse, exports date restoring clock pulse to phase detectors.
The present invention proposes a kind of clock data recovery circuit, and it comprises phase detectors, first integral module, arithmetic element, second integral module, oscillating circuit and phase converter.Phase detectors input the phase place of data crossfire and the phase place of date restoring clock pulse, with output calibration signal in order to compare.First integral module couples phase detectors, in order to correction signal is carried out integral processing, to export first integral phase error.Arithmetic element couples first integral module, in order to carry out computing to obtain operation values based on first integral phase error and correction signal.Second integral module couples arithmetic element, in order to carry out integral processing to operation values, to export phase control signal.Oscillating circuit couples second integral module, in order to according to first integral phase error, produces at least one with reference to clock pulse.Phase converter couples oscillating circuit, second integral module and phase detectors, in order to according to phase control signal and with reference to clock pulse, exports date restoring clock pulse to phase detectors.
In one example of the present invention embodiment, above-mentioned clock data recovery circuit also comprises multiplier (-icator), couples between phase detectors and arithmetic element, in order to correction signal is multiplied by preset ratio, to export the correction signal of preset ratio to arithmetic element.
In one example of the present invention embodiment, above-mentioned clock data recovery circuit also comprises frequency eliminator, couples oscillating circuit, in order to carry out frequency elimination, to produce system clock to reference to clock pulse.
In one example of the present invention embodiment, above-mentioned phase detectors are according to date restoring clock pulse, and sampling input data crossfire, to export date restoring crossfire.
In one example of the present invention embodiment, above-mentioned input data crossfire is sequence (serial) data crossfires.
In one example of the present invention embodiment, above-mentioned oscillating circuit produces multiple reference clock pulses with same frequency and out of phase according to frequency control signal, and phase converter is phase selector (phaseselector), in order to according to phase control signal, in above-mentioned multiple reference clock pulse, select date restoring clock pulse.
In one example of the present invention embodiment, above-mentioned oscillating circuit produces multiple reference clock pulses with same frequency and out of phase according to frequency control signal, and phase converter is phase interpolator (phaseinterpolator), in order to foundation phase control signal, phase interpolation process is carried out, to export date restoring clock pulse to above-mentioned multiple reference clock pulse.
Based on above-mentioned, clock data recovery circuit of the present invention, it can by received input data crossfire, the reference clock pulse needed for generation, and can not need to use outside crystal oscillator.So, the manufacturing cost of clock data recovery circuit can be saved.In addition, because the board layout space not needing indwelling extra is to outside crystal oscillator, the size of clock data recovery circuit can also be reduced.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Fig. 1 shows the configuration diagram of existing clock data recovery circuit.
Fig. 2 to Fig. 5 shows the configuration diagram of the clock data recovery circuit of the present invention one exemplary embodiment respectively.
Fig. 6 A to Fig. 6 C is respectively the schematic diagram of the first integral module in the present invention one exemplary embodiment.
Fig. 7 A to Fig. 7 C is respectively the schematic diagram of the second integral module in the present invention one exemplary embodiment.
Fig. 8 A to Fig. 8 C is respectively the schematic diagram of the third integral module in the present invention one exemplary embodiment.
Fig. 9 shows the oscillating circuit of clock data recovery circuit and the schematic diagram of phase converter of the present invention one exemplary embodiment.
Figure 10 is multiple sequential chart with reference to clock pulse in Fig. 9.
Figure 11 is the schematic diagram of the frequency eliminator of clock data recovery circuit in the present invention one exemplary embodiment.
Figure 12 shows the configuration diagram of the clock data recovery circuit of the present invention one exemplary embodiment.
Main element symbol description:
100,200,300,400,500,1200: clock data recovery circuit
110: coarse adjustment module
111: crystal oscillator
112: phase-frequency detector
113: the first low pass filters
114: the first voltage controlled oscillators
115,290: frequency eliminator
120: fine tuning module
121,210: phase detectors
122: the second low pass filters
123: the second voltage controlled oscillators
220,232,252,274: multiplier (-icator)
234,254,272: integrator
280: phase converter
202,302: PGC demodulation module
204,404: Frequency Locking module
230: first integral module
240: arithmetic element
250: third integral module
260: oscillating circuit
270: second integral module
C: electric capacity
C1: control signal
C2, C6, C7: control voltage
C3: oscillator signal
C4: frequency elimination signal
C5: control signal
CDR_CLK: date restoring clock pulse
CDR_DATA: date restoring crossfire
IN_DATA: input data crossfire
Kp: preset ratio
K1: the first gain
K2: the second gain
K3: the three gain
R: resistance
S
rEF, C
rEF, C
rEF(0) ~ C
rEF(N): with reference to clock pulse
SYS_CLK: system clock
S1: correction signal
S2, S
a: phase error
S3: first integral phase error
S4: operation values
S5: phase control signal
S6: frequency control signal
S
b, S
f, S
d: integrated signal
S
c: gain operation value
S
e: second integral phase error
θ
1, θ
2, θ
n: phase difference
Embodiment
Please refer to Fig. 2, Fig. 2 shows the configuration diagram of the clock data recovery circuit of the present invention one exemplary embodiment.Clock data recovery circuit 200 has PGC demodulation module 202 and Frequency Locking module 204.PGC demodulation module 202, in order to carry out PGC demodulation to input data crossfire IN_DATA, has identical phase place to make data crossfire IN_DATA with date restoring clock pulse CDR_CLK.In addition, PGC demodulation module 202 also according to date restoring clock pulse CDR_CLK, can sample input data crossfire IN_DATA, to produce date restoring crossfire CDR_DATA.In the present invention one exemplary embodiment, clock data recovery circuit 200 can be applicable in wired links communication system (wire-linkedcommunicationsystem), and input data crossfire IN_DATA and can be sequence (serial) data crossfire, clock data recovery circuit 200 can receive input data crossfire IN_DATA by single channel.But the present invention is not as limit, in another exemplary embodiment, clock data recovery circuit 200 also can be applicable to a wireless communication system, and inputs data crossfire IN_DATA and also can be parallel data crossfire.
Frequency Locking module 204, in order to based on the phase difference between input data crossfire IN_DATA and date restoring clock pulse CDR_CLK, produces and exports at least one with reference to clock pulse C
rEFto PGC demodulation module 202.Furthermore, Frequency Locking module 204 can adjust with reference to clock pulse C progressively
rEFfrequency, to make with reference to clock pulse C
rEFfrequency approach the frequency of input data crossfire IN_DATA gradually.By this, can reduce with reference to clock pulse C
rEFvibration (jitter), and with reference to clock pulse C
rEFfrequency can be less than a predetermined value compared to the error of the frequency of input data crossfire IN_DATA.In this exemplary embodiment, when the frequency of input data crossfire IN_DATA is 5GHz, with reference to clock pulse C
rEFfrequency and the frequency of input data crossfire IN_DATA between error can be less than 100ppm, and meet both errors in USB3.0 specification and must be less than the specification of 300ppm.It can thus be appreciated that according to the configuration diagram of Fig. 2, clock data recovery circuit 200 under the situation not needing outside crystal oscillator, also can produce required reference clock pulse C
rEF.In addition, Frequency Locking module 204 can provide first integral phase error S3 to PGC demodulation module 202.
In the present invention one exemplary embodiment, PGC demodulation module 202 has phase detectors 210, inputs the phase place of data crossfire IN_DATA and the phase place of date restoring clock pulse CDR_CLK, with output calibration signal S1 in order to compare.Frequency Locking module 204 couples of correction signal S1 carry out an integral processing and twice integral processing to export first integral phase error S3 and frequency control signal S6.PGC demodulation module 202, according to correction signal S1 and first integral phase error S3, produces phase control signal S5.The oscillating circuit 260 of Frequency Locking module 204, according to frequency control signal S6, produces at least one with reference to clock pulse C
rEF.The phase converter 280 of PGC demodulation module 202 is according to phase control signal S5 and with reference to clock pulse C
rEF, export date restoring clock pulse CDR_CLK to phase detectors 210.
Above-mentioned oscillating circuit 260 can be voltage controlled oscillator (VoltagecontrolledOscillator; VCO), numerically-controlled oscillator (DigitalcontrolledOscillator; DCO), resistive-capacitive oscillator (RCOscillator) ... on oscillator, but the present invention is not as limit.
The correction signal S1 that phase detectors 210 export is in order to the phase difference between reflection input data crossfire IN_DATA and date restoring clock pulse CDR_CLK.For example, when inputting the phase place of phase-lead date restoring clock pulse CDR_CLK of data crossfire IN_DATA, correction signal S1 is positive voltage; When the phase place inputting data crossfire IN_DATA falls behind the phase place of date restoring clock pulse CDR_CLK, correction signal S1 is negative voltage; When the phase place inputting data crossfire IN_DATA equals the phase place of date restoring clock pulse CDR_CLK, the magnitude of voltage of correction signal S1 is zero volt.
Frequency Locking module 204 separately has first integral module 230.First integral module 230 couples phase detectors 210, in order to carry out gain and integral processing to correction signal S1, to export first integral phase error S3.
PGC demodulation module 202 separately has arithmetic element 240 and second integral module 270.Arithmetic element 240 couples phase detectors 210 and first integral module 230, in order to carry out computing to obtain operation values S4 based on first integral phase error S3 and correction signal S1.In one example of the present invention embodiment, arithmetic element 240 is an adder, in order to the summation of correction signal S1 and first integral phase error S3.In other words, S4=S1+S3.Moreover in one example of the present invention embodiment, arithmetic element 240 is a subtracter, in order to the measures of dispersion between correction signal S1 and first integral phase error S3.In other words, S4=S1-S3 or S4=S3-S1.In addition, in one example of the present invention embodiment, arithmetic element 240 is a calculator, in order to according to correction signal S1 and first integral phase error S3, produces operation values S4.
Second integral module 270 couples arithmetic element 240, in order to carry out integral processing to operation values S4, to export phase control signal S5.
In one example of the present invention embodiment, Frequency Locking module 204 separately has third integral module 250, couples first integral module 230, in order to first integral phase error S3 is carried out integral processing, with output frequency control signal S6.In one example of the present invention embodiment, third integral module 250 also can carry out gain process to first integral phase error S3.
The phase converter 280 of PGC demodulation module 202 couples oscillating circuit 260, second integral module 270 and phase detectors 210, in order to foundation phase control signal S5 and with reference to clock pulse C
rEF, export date restoring clock pulse CDR_CLK to phase detectors 210.
In one example of the present invention embodiment, clock data recovery circuit also comprises multiplier (-icator), couples between phase detectors 210 and arithmetic element 240.Please refer to Fig. 3, Fig. 3 shows the configuration diagram of the clock data recovery circuit 300 of the present invention one exemplary embodiment.Clock data recovery circuit 300 has PGC demodulation module 302 and Frequency Locking module 204.PGC demodulation module 302 is identical with the function of PGC demodulation module 202, also in order to carry out PGC demodulation to input data crossfire IN_DATA, has identical phase place to make data crossfire IN_DATA with date restoring clock pulse CDR_CLK.Difference between PGC demodulation module 302 and PGC demodulation module 202 is that PGC demodulation module 302 separately comprises multiplier (-icator) 220, couples between phase detectors 210 and arithmetic element 240.Multiplier (-icator) 220 in order to correction signal S1 is multiplied by preset ratio Kp, with output phase error S2 to arithmetic element 240.In other words, phase error S2 equals correction signal S1 and is multiplied by preset ratio Kp, and multiplier (-icator) 220 exports the correction signal S1 of preset ratio Kp to arithmetic element 240.Preset ratio Kp can be 100%, 150%, 80% or other numerical value.In this exemplary embodiment, arithmetic element 240 is an adder, in order to calculate the summation of phase error S2 and first integral phase error S3.In other words, S4=S2+S3.Moreover in one example of the present invention embodiment, arithmetic element 240 is a subtracter, in order to calculate the measures of dispersion between phase error S2 and first integral phase error S3.In other words, S4=S2-S3 or S4=S3-S2.In addition, in one example of the present invention embodiment, arithmetic element 240 is a calculator, in order to according to phase error S2 and first integral phase error S3, produces operation values S4.
In one example of the present invention embodiment, first integral phase error S3 can be used as frequency control signal, to make oscillating circuit 260 according to first integral phase error S3, produces at least with reference to clock pulse C
rEF.Please refer to Fig. 4, Fig. 4 shows the configuration diagram of the clock data recovery circuit 400 of the present invention one exemplary embodiment.Clock data recovery circuit 400 has PGC demodulation module 202 and Frequency Locking module 404.The function of Frequency Locking module 404 is identical with Frequency Locking module 204, and it is also based on the phase difference between input data crossfire IN_DATA and date restoring clock pulse CDR_CLK, produces and exports at least one with reference to clock pulse C
rEFto PGC demodulation module 202.Difference between Frequency Locking module 404 and Frequency Locking module 204 is that Frequency Locking module 404 does not have the third integral module 250 of Frequency Locking module 204.First integral phase error S3 in clock data recovery circuit 400, as frequency control signal, to make oscillating circuit 260 according to first integral phase error S3, produces at least with reference to clock pulse C
rEF.
In one example of the present invention embodiment, clock data recovery circuit has PGC demodulation module 302 and Frequency Locking module 204.Please refer to Fig. 5, Fig. 5 shows the configuration diagram of the clock data recovery circuit 500 of the present invention one exemplary embodiment.Clock data recovery circuit 500 has PGC demodulation module 302 and Frequency Locking module 204.Therefore, in this exemplary embodiment, clock data recovery circuit 500 has multiplier (-icator) 220 and third integral module 250 simultaneously.
Please refer to Fig. 6 A, in the present invention one exemplary embodiment, first integral module 230 has an integrator 234, in order to carry out integral processing to correction signal S1, to export first integral phase error S3.
In the present invention one exemplary embodiment, first integral module 230 can comprise multiplier (-icator) and integrator.Please refer to Fig. 6 B, Fig. 6 B is the schematic diagram of the first integral module 230 in the present invention one exemplary embodiment.First integral module 230 comprises multiplier (-icator) 232 and integrator 234.Multiplier (-icator) 232 couples phase detectors 210, in order to correction signal S1 to be multiplied by the first gain K1, with output phase error S
a.Integrator 234 couples multiplier (-icator) 232, in order to phase error S
acarry out integral processing, to export first integral phase error S3.
In the present invention one exemplary embodiment, the position of multiplier (-icator) 232 and integrator 234 is interchangeable.Please refer to Fig. 6 C, Fig. 6 C is the schematic diagram of the first integral module 230 in the present invention one exemplary embodiment.Integrator 234 couples phase detectors 210, in order to carry out integral processing to correction signal S1, to export integrated signal S
b.Multiplier (-icator) 232 couples integrator 234, in order to by integrated signal S
bbe multiplied by the first gain K1, to export first integral phase error S3.
Please refer to Fig. 7 A, in the present invention one exemplary embodiment, second integral module 270 has an integrator 272, in order to carry out integral processing to operation values S4, to export phase control signal S5.
Please refer to Fig. 7 B, in the present invention one exemplary embodiment, second integral module 270 has multiplier (-icator) 274 and integrator 272.Multiplier (-icator) 274 couples arithmetic element 240, in order to operation values S4 to be multiplied by the second gain K2, with output gain operation values S
c.Integrator 272 couples multiplier (-icator) 274, in order to gain operation value S
ccarry out integral processing, to export phase control signal S5.
In the present invention one exemplary embodiment, the position of multiplier (-icator) 274 and integrator 272 is interchangeable.Please refer to Fig. 7 C, Fig. 7 C is the schematic diagram of the second integral module 270 in the present invention one exemplary embodiment.Integrator 272 couples arithmetic element 240, in order to carry out integral processing to operation values S4, to export integrated signal S
d.Multiplier (-icator) 274 couples integrator 272, in order to by integrated signal S
dbe multiplied by the second gain K2, to export phase control signal S5.
Please refer to Fig. 8 A, in the present invention one exemplary embodiment, third integral module 250 has an integrator 254, in order to carry out integral processing to first integral phase error S3, with output frequency control signal S6.
In the present invention one exemplary embodiment, third integral module 250 can comprise multiplier (-icator) and integrator.Please refer to Fig. 8 B, Fig. 8 B is the schematic diagram of the third integral module 250 in the present invention one exemplary embodiment.Third integral module 250 can comprise multiplier (-icator) 252 and integrator 254.Multiplier (-icator) 252 couples first integral module 230, in order to first integral phase error S3 is multiplied by the 3rd gain K3, to export second integral phase error S
e.Integrator 254 couples multiplier (-icator) 252 in order to second integral phase error S
ecarry out integral processing, with output frequency control signal S6.
In the present invention one exemplary embodiment, the position of multiplier (-icator) 252 and integrator 254 is interchangeable.Please refer to Fig. 8 C, Fig. 8 C is the schematic diagram of the third integral module 250 in the present invention one exemplary embodiment.Integrator 254 couples first integral module 230, in order to carry out integral processing to first integral phase error S3, to export integrated signal S
f.Multiplier (-icator) 252 couples integrator 254, in order to by integrated signal S
fbe multiplied by the 3rd gain K3, with output frequency control signal S6.
In one example of the present invention embodiment, oscillating circuit 260 produces single with reference to clock pulse C
rEF, and phase converter 280 adjusts with reference to clock pulse C according to phase control signal S5
rEFfrequency, export date restoring clock pulse CDR_CLK to produce.
In addition, in the present invention one exemplary embodiment, oscillating circuit 260 can produce multiple with reference to clock pulse.Please refer to Fig. 9 and Figure 10.Fig. 9 shows the oscillating circuit of clock data recovery circuit and the schematic diagram of phase converter of the present invention one exemplary embodiment.Figure 10 is multiple sequential chart with reference to clock pulse in Fig. 9.Oscillating circuit 260 produces multiple with reference to clock pulse C according to frequency control signal S6
rEF(0) ~ C
rEF(N).With reference to clock pulse C
rEF(0) ~ C
rEF(N) there is same frequency, but phase place is each other not identical.As shown in Figure 10, with reference to clock pulse C
rEFand C (0)
rEF(1) phase difference between is θ
1, with reference to clock pulse C
rEFand C (0)
rEF(2) phase difference between is θ
2, with reference to clock pulse C
rEFand C (0)
rEF(N) phase difference between is θ
n.
In the present invention one exemplary embodiment, phase converter 280 is a phase selector (phaseselector), in order to foundation phase control signal S5, self-reference clock pulse C
rEF(0) ~ C
rEF(N) one is selected in reference to clock pulse as date restoring clock pulse CDR_CLK.
In the present invention one exemplary embodiment, phase converter 280 is a phase interpolator (phaseinterpolator), in order to according to phase control signal S5, to reference clock pulse C
rEF(0) ~ C
rEF(N) phase interpolation process is carried out, to export date restoring clock pulse CDR_CLK.When phase converter 280 is to reference clock pulse C
rEF(0) ~ C
rEF(N), when carrying out phase interpolation process, it can first be selected with reference to clock pulse C
rEF(0) ~ C
rEF(N) in, any two are with reference to clock pulse, then according to selected two with reference to clock pulse, produce date restoring clock pulse CDR_CLK, and its phase place of date restoring clock pulse CDR_CLK produced can between selected two phase places with reference to clock pulse.
Please refer to Figure 11, in the present invention one exemplary embodiment, clock data recovery circuit also has frequency eliminator 290, in order to reference to clock pulse C
rEFcarry out frequency elimination, and produce frequency and be less than with reference to clock pulse C
rEFthe system clock SYS_CLK of frequency, and system clock SYS_CLK can be used for clock data recovery circuit 200 other electronic components in an electronic, operate according to system clock SYS_CLK to make those electronic components.Must understand, produce multiple with reference in the embodiment of clock pulse at above-mentioned oscillating circuit 260, frequency eliminator 290 can alternatively to reference clock pulse C
rEF(0) ~ C
rEF(N) frequency elimination is carried out, to produce system clock SYS_CLK.
Please refer to Figure 12, Figure 12 shows the configuration diagram of the clock data recovery circuit 1200 of the present invention one exemplary embodiment.Clock data recovery circuit 1200 has PGC demodulation module 302 and Frequency Locking module 204.In this exemplary embodiment, the first integral module 230 of Frequency Locking module 204 implements in the mode of Fig. 6 B, and the third integral module 250 of Frequency Locking module 204 implements in the mode of Fig. 8 B.In this exemplary embodiment, the frequency range of qualification phase locking module 202 can be carried out by adjustment preset ratio Kp.Generally speaking, the frequency range of PGC demodulation module 202 is between 1.5MHz and 5.0MHz.For example, if clock data recovery circuit 200 meets the specification of USB3.0, then can by adjustment preset ratio Kp come qualification phase locking module 202 frequency range be 5MHz.Thus, get final product the high frequency noise in filtering input data crossfire IN_DATA by PGC demodulation module 202, and be beneficial to the phase place change that trace data recovers medium and low frequency (middle-to-lowfrequency) part of clock pulse CDR_CLK.In addition, in the present invention one exemplary embodiment, multiplier (-icator) 220 is programmed multiplier (-icator), can adjust preset ratio Kp by transfer control signal to the mode of multiplier (-icator) 220.
In addition, the first gain K1 and the 3rd gain K3 also can be adjusted.Wherein, the size of the 3rd gain K3 can in order to determine with reference to clock pulse C
rEFthe speed of frequency when being adjusted.In detail, in exemplary embodiment of the present invention, when the 3rd gain K3 is larger, with reference to clock pulse C
rEFfrequency change can be faster.Otherwise, when the 3rd gain K3 more hour, with reference to clock pulse C
rEFfrequency change can be slower.In addition, the frequency range of Frequency Locking module 204 can be set as the frequency range also less than PGC demodulation module 202, with the vibration noise (jitternoise) of filtering input data crossfire IN_DATA medium-high frequency, and avoid interference the PGC demodulation action that PGC demodulation module 202 carries out.In the present invention one exemplary embodiment, the frequency range of Frequency Locking module 204 is set between 1KHz to 100KMz, and the frequency range of PGC demodulation module 202 is set between 1.5MHz to 5.0MHz.
Phase detectors 210 input except the phase place of data crossfire IN_DATA and the phase place of date restoring clock pulse CDR_CLK except comparing, and also can sample input data crossfire IN_DATA, to produce date restoring crossfire CDR_DATA according to date restoring clock pulse CDR_CLK.Wherein, date restoring crossfire CDR_DATA comprises the data that will receive to some extent.In the present invention one exemplary embodiment, the back-end circuit of clock data recovery circuit 200 can read the data of date restoring crossfire CDR_DATA by date restoring clock pulse CDR_CLK.
In sum, clock data recovery circuit of the present invention, it can by received input data crossfire, the reference clock pulse needed for generation, and can not need to use outside crystal oscillator.So, the manufacturing cost of clock data recovery circuit can be saved.In addition, because the arrangement space not needing indwelling extra is to outside crystal oscillator, therefore the size of clock data recovery circuit can be reduced.
Although the present invention discloses as above with embodiment; but it is also not used to limit the present invention; any the technical staff in the technical field; without departing from the spirit and scope of the present invention; when doing suitable change and equal replacement, therefore the scope that protection scope of the present invention should define with the application's claim is as the criterion.
Claims (18)
1. a clock data recovery circuit, is characterized in that, comprising:
One phase detectors, in order to the phase place of the phase place and a date restoring clock pulse that compare an input data crossfire, to export a correction signal;
One first integral module, couples this phase detectors, in order to this correction signal is carried out integral processing, to export a first integral phase error;
One arithmetic element, couples this first integral module, in order to carry out computing to obtain an operation values based on this first integral phase error and this correction signal;
One second integral module, couples this arithmetic element, in order to carry out integral processing to this operation values, to export a phase control signal;
One third integral module, couples this first integral module, in order to this first integral phase error is carried out integral processing, to export a frequency control signal;
One oscillating circuit, couples this third integral module, in order to according to this frequency control signal, produces at least one with reference to clock pulse; And
One phase converter, couples this oscillating circuit, this second integral module and this phase detectors, in order to according to this phase control signal and this reference clock pulse, exports this date restoring clock pulse to these phase detectors.
2. clock data recovery circuit according to claim 1, also comprises a multiplier (-icator), couples between these phase detectors and this arithmetic element, in order to this correction signal is multiplied by a preset ratio, to export this correction signal of this preset ratio to this arithmetic element.
3. clock data recovery circuit according to claim 1, at least one integration module wherein in this first integral module, this second integral module and this third integral module comprises a multiplier (-icator) and an integrator, respectively in order to carry out gain and integral processing to the input of this at least one integration module.
4. clock data recovery circuit according to claim 1, at least one integration module wherein in this first integral module, this second integral module and this third integral module comprises an integrator, in order to carry out integral processing to the input of this at least one integration module.
5. clock data recovery circuit according to claim 1, also comprises a frequency eliminator, couples this oscillating circuit, in order to carry out frequency elimination to this reference clock pulse, to produce a system clock.
6. clock data recovery circuit according to claim 1, wherein these phase detectors are according to this date restoring clock pulse, sample this input data crossfire, to export a date restoring crossfire.
7. clock data recovery circuit according to claim 1, wherein this input data crossfire is sequence data crossfire.
8. clock data recovery circuit according to claim 1, wherein this oscillating circuit produces multiple reference clock pulses with same frequency and out of phase according to this frequency control signal, and this phase converter is a phase selector, in order to according to this phase control signal, select this date restoring clock pulse from those with reference in clock pulse.
9. clock data recovery circuit according to claim 1, wherein this oscillating circuit produces multiple reference clock pulses with same frequency and out of phase according to this frequency control signal, and this phase converter is a phase interpolator, in order to according to this phase control signal, phase interpolation process is carried out, to export this date restoring clock pulse with reference to clock pulse to those.
10. a clock data recovery circuit, is characterized in that, comprising:
One phase detectors, in order to the phase place of the phase place and a date restoring clock pulse that compare an input data crossfire, to export a correction signal;
One first integral module, couples this phase detectors, in order to this correction signal is carried out integral processing, to export a first integral phase error;
One arithmetic element, couples this first integral module, in order to carry out computing to obtain an operation values based on this first integral phase error and this correction signal;
One second integral module, couples this arithmetic element, in order to carry out integral processing to this operation values, to export a phase control signal;
One oscillating circuit, couples this second integral module, in order to according to this first integral phase error, produces at least one with reference to clock pulse; And
One phase converter, couples this oscillating circuit, this second integral module and this phase detectors, in order to according to this phase control signal and this reference clock pulse, exports this date restoring clock pulse to these phase detectors.
11. clock data recovery circuit according to claim 10, also comprise a multiplier (-icator), couple between these phase detectors and this arithmetic element, in order to this correction signal is multiplied by a preset ratio, to export this correction signal of this preset ratio to this arithmetic element.
12. clock data recovery circuit according to claim 10, at least one integration module wherein in this first integral module and this second integral module comprises a multiplier (-icator) and an integrator, respectively in order to carry out gain and integral processing to the input of this at least one integration module.
13. clock data recovery circuit according to claim 10, at least one integration module wherein in this first integral module and this second integral module comprises an integrator, in order to carry out integral processing to the input of this at least one integration module.
14. clock data recovery circuit according to claim 10, also comprise a frequency eliminator, couple this oscillating circuit, in order to carry out frequency elimination to this reference clock pulse, to produce a system clock.
15. clock data recovery circuit according to claim 10, wherein these phase detectors are according to this date restoring clock pulse, sample this input data crossfire, to export a date restoring crossfire.
16. clock data recovery circuit according to claim 10, wherein this input data crossfire is sequence data crossfire.
17. clock data recovery circuit according to claim 10, wherein this oscillating circuit produces multiple reference clock pulses with same frequency and out of phase according to this first integral phase error, and this phase converter is a phase selector, in order to according to this phase control signal, select this date restoring clock pulse from those with reference in clock pulse.
18. clock data recovery circuit according to claim 10, wherein this oscillating circuit produces multiple reference clock pulses with same frequency and out of phase according to this first integral phase error, and this phase converter is a phase interpolator, in order to according to this phase control signal, phase interpolation process is carried out, to export this date restoring clock pulse with reference to clock pulse to those.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110352019.9A CN103107796B (en) | 2011-11-09 | 2011-11-09 | Clock data recovery circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110352019.9A CN103107796B (en) | 2011-11-09 | 2011-11-09 | Clock data recovery circuit |
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| CN103107796B true CN103107796B (en) | 2016-02-03 |
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| CN107800427B (en) * | 2016-09-05 | 2021-04-06 | 创意电子股份有限公司 | Clock data recovery module |
| CN112821884B (en) * | 2019-11-18 | 2023-07-25 | 群联电子股份有限公司 | Signal generation circuit, memory storage device and signal generation method |
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| WO1993013602A1 (en) * | 1991-12-23 | 1993-07-08 | Telefonaktiebolaget Lm Ericsson | Shifting phase of a clock signal, in particular for clock recovery of a digital data signal |
| CN1360396A (en) * | 2000-12-21 | 2002-07-24 | 日本电气株式会社 | Clock and data restoring circuit and its clock control method |
| TWI248259B (en) * | 2002-10-10 | 2006-01-21 | Mstar Semiconductor Inc | Apparatus for generating quadrature phase signals and data recovery circuit using the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7215215B2 (en) * | 2004-03-15 | 2007-05-08 | Matsushita Electric Industrial Co., Ltd. | Phase modulation apparatus, polar modulation transmission apparatus, wireless transmission apparatus and wireless communication apparatus |
| US8170169B2 (en) * | 2006-12-01 | 2012-05-01 | Snowbush Inc. | Serializer deserializer circuits |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1993013602A1 (en) * | 1991-12-23 | 1993-07-08 | Telefonaktiebolaget Lm Ericsson | Shifting phase of a clock signal, in particular for clock recovery of a digital data signal |
| CN1360396A (en) * | 2000-12-21 | 2002-07-24 | 日本电气株式会社 | Clock and data restoring circuit and its clock control method |
| TWI248259B (en) * | 2002-10-10 | 2006-01-21 | Mstar Semiconductor Inc | Apparatus for generating quadrature phase signals and data recovery circuit using the same |
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