CN103106379B - A kind of non-contact IC card with robustness receives counting method - Google Patents

Abstract

There is a receipts counting method for the non-contact IC card of robustness, belong to the technical field that IC-card receives data, it is characterized in that adapting to different data demodulates width, position deviation.With exalted carrier clock over-sampling demodulating data, and in data buffer storage stored in 128+16 position; To detect in data buffer storage continuous zero, and record the center of continuous zero and the longest length of continuous zero; By judging that in data buffer storage, in forward and backward 64, the number of zero and the relation of the longest continuous zero-length judge sequence, to adapt to different data demodulates width; Go here and there the longer center of continuous zero as bit synchronization benchmark, as initiation of communication position using detect first; Thereafter every 128 clock period carry out sequence judgement, and compare in Z or X sequence zero center and data buffer storage 32nd ~ 63 or 96th ~ 127 in the deviation of position, in order to adjusted position synchronous base, thus position deviation.

Description

A kind of non-contact IC card with robustness receives counting method

Technical field

The receipts digital-to-analogue block that the present invention relates to the non-contact IC card meeting ISO/IEC14443TypeA agreement realizes, and especially change for applicable data demodulation width, sampling clock has deviation, has the receipts counting method of robustness.

Background technology

The concept of IC-card puts forward early 1970s, first boolean (BULL) company of France createed smart card sample in 1976, and this technology is applied to multiple industries such as finance, traffic, medical treatment and proof of identification, microelectric technique and computer technology combine by it, improve the up-to-dateness of people's live and work.

According to the form that card and exogenous data transmit, IC-card can be divided into Contact Type Ic Card and non-contact IC card.The international standard of non-contact IC card has in ISO/IEC10536, ISO/IEC14443 and ISO/IEC15693 and ISO/IEC7816 the part of standards that non-contact IC card is also suitable for.The physical characteristics of card, transmitting/accept electric signal, anti-collision mechanism, reset answer and host-host protocol is mainly discussed in contactless card international standard.

ISO/IEC14443 agreement defines two kinds of signaling interface: TypeA and TypeB.The non-contact IC card discussed herein defers to ISO/IEC14443typeA agreement.

According to ISO/IEC14443-2A agreement regulation, smart card reader produces the RF electromagnetic field being coupled to IC-card, in order to transmit energy and two-way communication.IC-card converts it into DC voltage after obtaining energy.The field strength range of RF field is 15A/m ~ 75A/m, carrier frequency f _cfor 1356MHz ± 7kHz.Data transmission rate=1356MHz/128=106Kb/s, the time cycle shared by a data is 94us.As shown in Figure 1, smart card reader reads transmission signal (01001) to non-contact IC.Modulation system adopts the ASK of 100%, creates one " gap (pause) " and transmit binary data in RF field.Pause waveform as shown in Figure 2.

Coded system adopts distortion Miller code, as shown in Figure 3, has three kinds of sequential: sequential X, at 64/f _cpart produces a pause; Sequential Y, does not modulate during whole position; Sequential Z, the starting of period in place produces a pause.Bits per inch is according to accounting for 94us, and modulation signal is 1 when the full width of carrier wave, and be 0 during pause, the time width that wherein pause continues can with reference to the parameter in figure 2.

The logical one of coding is sequential X.Logical zero is sequential Y.Have two or more 0 if adjacent, from second 0, adopt sequential Z.If first after the start bit of frame is 0, then represent this with sequential Z and directly follow thereafter 0.Communication starts: sequential Z; Sign off: logical zero, following is thereafter sequential Y; Without information: have two sequential Y at least.

Fig. 4 and Fig. 5 illustrates the frame format of transmission.What Fig. 4 represented is short frame, and for initialize communications, it comprises initiation of communication position S, 7 bit data (least significant bit (LSB) low level LSB first sends) and sign off position S.What Fig. 5 represented is standard frame, and for exchanges data, it consists of initiation of communication position S, N* (8 data bit+odd parity bit) and sign off position E.Wherein the least significant bit (LSB) of data byte first sends, and has an odd parity bit after each data byte.

According to agreement regulation, 100%ASK modulation, pause waveform has certain parameter area (as Fig. 2), and RF radio field intensity has certain limit (15 ~ 75A/m).Data width for the pause demodulation of different parameters is different.In addition along with RF field intensity is different, antenna envelope is different, and the data width of therefore demodulation is also different.And the data of demodulation may have certain burr or noise effect to have certain shake.

On the other hand, during pause, antenna does not have carrier wave, during such non-contact IC is stuck in pause, can not carrier clock be extracted.No matter be with clock recovery circuitry or with clock switch circuit, the deviation that the clock obtained is more certain than having with carrier clock.

In order to allow non-contact IC have more robustness, data must be received in the various situations of agreement regulation, and certain nargin can be left on area covered by agreement.

Summary of the invention

In order to the different pause shape of ISO/IEC14443TypeA agreement can be applicable to, the data width change of demodulation under different RF field intensity, and the impact of clock jitter can be solved, the invention provides a kind of receipts counting method with the non-contact IC card of robustness.

The invention is characterized in, realize according to the following steps successively in non-contact IC card:

Step (1), the regulator rectifier circuit in AFE (analog front end) obtains the DC voltage needed for non-contact IC card work from the RF carrier signal that antenna RF receives;

Step (2), the carrier extract circuit in AFE (analog front end) extracts RF carrier clock RF_CLK from described carrier wave, and input clock recovers or commutation circuit;

Step (3), after the described clock recovery of AFE (analog front end) or commutation circuit receive carrier clock RF_CLK, during the pause of gap, switch to frequency close to the clock of 1356MHz, be input in this, as sampling clock CLK_S in the data buffer storage of the 128+16 position of receiving in digital-to-analogue block

Step (4), the data RF_DIN of described demodulator circuit over-sampling demodulation from RF carrier wave, under described sampling clock CLK_S is synchronous, is moved in described 128+16 bit data buffer memory;

Step (5), described receipts digital-to-analogue block utilizes the data in data buffer storage to go to detect initiation of communication position: think that when detecting at least continuous three zero data are " 0 ", the first series winding continuous " 0 " detected is as initiation of communication position, and using the center of this continuous " 0 " as bit synchronous benchmark, record the length of the longest " 0 " continuously;

Step (6), when the center of continuous " 0 " moves on in data buffer storage, use X sequence, in three kinds of distortion Miller code sequences that Y sequence and Z sequence represent in any one sequence, with the center of the centers of 32nd ~ 63 as front 64 half bit periods, with the center of the centers of 96th ~ 127 as rear 64 half bit periods: current 64 half bit periods, in rear 64 half bit periods, the number of " 0 " is all less than a half of the longest " 0 " length continuously, then whole bit period does not have " 0 ", data are described Y sequence, when in described front 64 half bit periods, the number of " 0 " is greater than the number of " 0 " in described rear 64 half bit periods, data are Z sequence, X sequence is thought in other situations,

Step (7), state machine in described receipts digital-to-analogue block is behind the initiation of communication position obtained received in step (5) and bit synchronization benchmark, the first bit data after 128 clock period judge described initiation of communication position: if the first bit data is Y sequence, then return step (5), again detect initiation of communication position;

Step (8), after described state machine synchronous base in place, the sequence of carrying out described distortion Miller code every 128 clock period judges, the same step of determination methods (6);

Step (9), centered by described bit synchronization benchmark, open the correction " window " of 32 clock period, detect the center of continuous " 0 " of next bit data:

If Z sequence, the center of " 0 " and the difference of the position in corresponding data buffer storage 96th ~ 127 relatively continuously,

If X sequence, the position relatively continuously in " 0 " and the difference of the position in corresponding data buffer storage 32nd ~ 63, if Y sequence, think that whole bit period does not have " 0 ", do not go comparison position deviation,

With the deviation adjusting bit synchronization benchmark of described center at the end of described correction " window ", correcting range is ± 8 clock period,

Step (10), at the end of described correction " window ", the sequence judged by step (8), judge sequence buffer memory seq_buf [3:0], X sequence is write 1101, Y sequence and is write 1111, Z sequence writes 0111, and juxtaposition plays sequence effective marker seq_val;

Step (11), after decoding, obtain: present bit cur_bit, the effective marker bit_en of present bit is when seq_buf [3:0]=1101, cur_bit is 1, in other situations, cur_bit is 0, and when seq_buf [7:0]=0111-1111 or 1111-1111, terminating mark end_flag is 1.

The invention has the beneficial effects as follows, pause demodulation width 037 ~ 63us can be demodulated, the data in every bit clock deviation ± 8 cycle, and burr and the shake that well can resist demodulating data, there is good robustness.

Accompanying drawing explanation

Fig. 1 is the interface traffic channel citing of ISO/IEC14443TypeA agreement, and modulation system adopts ASK100%, and coded system is distortion Miller code, and data transmission rate is 106kbit/s.

Fig. 2 is the pause oscillogram that ISO/IEC14443TypeA agreement 100%ASK modulates.

Fig. 3 is three kinds of sequences of ISO/IEC14443TypeA protocol variations Miller code.

Fig. 4 is the short frame format of the data transmission of ISO/IEC14443TypeA agreement.

Fig. 5 is the standard frame format of the data transmission of ISO/IEC14443TypeA agreement.

Fig. 6 is the structured flowchart of receipts digital-to-analogue block of the present invention and AFE (analog front end).

Fig. 7 demodulating data RF_DIN that to be AFE (analog front end) obtain from RF and carrier clock RF_CLK.

Fig. 8 is the sampling clock CLK_S after antenna carrier clock RF_CLK and clock recovery.

Fig. 9 is the data buffer storage data_buf of 128+16 position.

Figure 10 is for detecting the sequential chart of " 0 " continuously.

Figure 11 is state machine.

Figure 12 is that start bit detects, state machine changes and the crucial sequential chart of clock correction.

Figure 13 is that start bit detects, state machine change and clock correction time corresponding data buffer storage data_buf in " 0 " change in location figure.

The minimum clock frequency that Figure 14 allows during being the pause demodulation width and corresponding pause tested.

In figure, RF represents the antenna waveform received, RF_CLK represents the carrier clock of extraction, VDD represents the DC voltage after rectifying and voltage-stabilizing, RF_DIN represents the data of demodulation, CLK_S represent carrier clock fill up disappearance after sampling clock, data_buf represents the data buffer storage of 128+16 position, data_0 represents the mark detecting continuous zero, zero_ptr represents the position of the center of continuous zero in data buffer storage, max_len0 represents the longest continuous zero-length, half1_cnt represents the zero number in first half bit period, half2_cnt represents the zero number in later half bit period, start_flag represents initiation of communication bit flag, seq_x represents that the sequence of detection is X sequence, seq_y represents that the sequence of detection is Y sequence, seq_z represents that the sequence of detection is Z sequence, bit_cnt represents digit counter, cnt represents counter, window represents " window " Status Flag, rec_cnt represents counts corrected device, seq_val represents sequence effective marker, seq_buf represents sequence buffer memory, state represents state machine state, end_flag represents sign off bit flag, cur_bit represents bit data, bit_en represents bit data effective marker, IDLE represents init state, FIRST_CNT represents the first bit data position count status, FIRST_WIN represents the first bit data clock correction " window " state, FIRST_SEQ represents that the first bit data sequence judges state, BIT_CNT represents data bit count status, REC_WIN represents clock correction " window " state, JUDGE_SEQ represents that sequence judges state.

Embodiment

The technical solution adopted for the present invention to solve the technical problems is:

First, by the carrier clock over-sampling of the data from RF demodulation, stored in the data buffer storage data_buf of 128+16 position.The carrier clock of wherein sampling is the carrier clock extracted from RF, switches to the clock close to carrier frequency 1356MHz during pause.According to agreement ISO/IEC14443TypeA regulation, a data accounts for 128 carrier cycles, and what sequence what so just can judge by the data in 128+16 bit data buffer memory to receive is.Distortion Miller code has three kinds of sequences: X sequence (1101), Y sequence (1111) and Z sequence (0111).Each sequence is made up of four numbers, is designated as " S3S2S1S0 ".0 ~ 31 bit representation S0 of data buffer storage data_buf can be used like this, 32 ~ 63 bit representation S1,64 ~ 95 bit representation S2,96 ~ 127 bit representation S3.

Then, go to detect initiation of communication position by the data in data buffer storage data_buf.Because the data of demodulation may have certain burr or noise effect to have shake, so when judging sequence, think that a string " 0 " is continuously just data " 0 ", and using the center of continuous " 0 " as bit synchronous benchmark.When not having information, antenna is full width, in time receiving the first series winding continuous " 0 ", thinks and detects initiation of communication position.When the center of the first series winding continuous 0 moves on to S3 center, the sequence that data buffer storage represents is " 0111 ", i.e. initiation of communication position, in this, as bit synchronization benchmark.

Then judge subsequent sequence and detect sign off position.After synchronous base in place, every 128 clock period, next sequence just moves in data buffer storage data_buf, can judge the sequence of its correspondence.According to the regulation of ISO/IEC14443TypeA agreement, as shown in Figure 2, gap pause has different wave, thus the data width of demodulation has certain limit.In order to be applicable to wider demodulation width, can be applicable to again narrow demodulation width, we think that, if first half bit period has zero, data are X sequence; If later half bit period has zero, data are Z sequence; If whole bit period does not have zero, data are Y sequence.Here use two counters, record the number of in 64 bit data in data buffer storage data_buf centered by S3 and S1 0 respectively.By the half of the longest continuous 0 length received in data, have as in judgement half bit period the threshold value not having zero.If two sequences are " YY " or " ZY ", then it is sign off position.

Clock jitter corrects.After synchronous starting point in place, every 128 clock period, next sequence just moves in data buffer storage data_buf.If do not have clock jitter, X sequence " 0 " center should at the center of the S1 of data buffer storage data_buf, and Z sequence " 0 " center should at the center of the S3 of data buffer storage data_buf.If there is clock jitter, compare the deviation of the center of " 0 " center and S3, S1, just can know and lost or add several clock, can clock jitter correction be carried out when next bit data bit sync.If Y sequence just can not judge clock jitter, but communication period, do not have two continuous print Y sequences, only sign off positions, therefore the last position of Y sequence and latter one can carry out clock correction.In this patent, carry out clock correction with " window " of one 32, can correct the clock jitter of ± 16 at every turn, can not position deviation during consideration Y sequence, the clock jitter number that therefore can correct is ± 8.

The present invention proposes a kind of receipts counting method with the non-contact IC card of robustness, can be applicable to different pause shape, the data width change of demodulation under different RF field intensity, and can solve clock jitter.

For making object of the present invention, technical scheme and advantage clearly understand, to develop simultaneously embodiment referring to accompanying drawing, the present invention is described in more detail.

Fig. 6 is the receipts digital-to-analogue block of the non-contact IC card of this patent and the structured flowchart of AFE (analog front end).

1 AFE (analog front end)

Non-contact IC card is passive, and from the carrier signal that antenna RF receives, obtain energy, AFE (analog front end) obtains the DC voltage VDD needed for IC-card work by regulator rectifier circuit.Demodulate data RF_DIN by the carrier envelope of antenna RF, obtain carrier clock RF_CLK by Clock Extraction clock circuit, as shown in Figure 7.Because modulation system is 100%ASK, so during the pause of gap, carrier clock RF_CLK has certain disappearance.Carrier clock RF_CLK, by clock recovery circuitry or clock switch circuit, fills up the clock close to 1356MHz, as sampling clock CLK_S, as shown in Figure 8 during the pause of gap.Final sampling clock CLK_S has certain clock disappearance, and clock frequency changes during the pause of gap.

In the figure 7, from the data RF_DIN that RF demodulates, when the full width of antenna waveform, be high level 1, be low level 0 during pause.According to the regulation of 14443A agreement, the waveform of pause is determined (with reference to figure 2) by four parametric t 1, t2, t3, t4.For the data width t that the pause of different parameters demodulates _pausedifferent.In addition along with RF field intensity is different, antenna envelope also changes, thus affects the demodulation width t of pause _pause.Therefore, the data width t of demodulation _pausewith RF field intensity and pause parameter change and change.From theory, according to Fig. 2, pause demodulation width t _pause, be the widelyst no more than t _1max+ t _3max=30+15=45 (us), is narrower than t most _2min=05us, i.e. 05us≤t _pause≤ 45us, in other words pause demodulation continuous zero time be 6 to 60 clock period.

2 data buffer storages

The data RF_DIN of AFE (analog front end) demodulation, with sampling clock CLK_S synchronized sampling, moves in data buffer storage data_buf.

According to ISO/IEC14443TypeA agreement regulation, data transmission rate is 1356MHz/128=106Kb/s, and such a data accounts for 128 carrier cycles.Distortion Miller code has three kinds of sequences: X sequence (1101), Y sequence (1111) and Z sequence (0111).Each sequence is made up of four numbers, is designated as " S3S2S1S0 ".A sequence accounts for 128 carrier cycles, and therefore in sequence, each number accounts for 32 carrier cycles.So just can use 0 ~ 31 bit representation S0 of data buffer storage data_buf, 32 ~ 63 bit representation S1,64 ~ 95 bit representation S2,96 ~ 127 bit representation S3, as shown in Figure 9.

3 detect continuous zero, record continuous zero length and location

As shown in Figure 10, this occurs 30 when data_buf lowest order data_buf [0] is continuous, data_0 is set to height, then records the length zero_len of continuous zero and the longest continuous zero number max_len0.Because the both sides of continuously " 0 " may jagged or shake, but the center of " 0 " is more accurately continuously, therefore judge sequence and bit synchronous time be all go judgement using the center of " 0 " continuously as benchmark.So after " 0 " terminates continuously, record the center of " 0 " continuously in the position of data buffer storage databuf with counter zero_ptr.Before a full bit period, if there is longer continuous zero, zero_ptr by the center of longer for record continuous zero.

4 half bit period to-zero counters and sequence judge

Observe three kinds of sequences: X sequence (1101), Y sequence (1111) and Z sequence (0111), can find that X sequence only has S1 to be that 0, Z sequence only has S3 to be 0, and Y sequence does not have zero.Visible judgement sequence key is the position judging " 0 ", the namely position of pause.According to the demodulation width t introducing pause above _pausefor 05us ~ 45us.Therefore the width of " 0 " may be greater than the bit period 236us of 1/4th, but can not be greater than the bit period 47us of half.In order to be applicable to different demodulation width, so we think that, if " 0 " appears at first half bit period, data are X sequence; If " 0 " appears at later half bit period, data are Z sequence; If there is no zero, then data bit Y sequence.

When judging sequence, the center of " 0 " has been moved on to the center of data buffer storage S3 or S1 by us.So only need counter half1_cnt and half2_cnt judged as shown in the figure, they calculate the number of zero in first half bit period and later half bit period respectively.When having data " 0 ", the size comparing half1_cnt and half2_cnt just can know sequence X or Z.Do not have data " 0 ", sequence is Z sequence.When whether judgement has data " 0 ", because " 0 " impact wider in some burrs or context, in Z sequence, half1_cnt and half2_cnt can not be 0.Therefore a threshold value is needed to go to judge whether there are data " 0 ".We think and are once receiving in the process of number, and the demodulation width of pause remains unchanged substantially, therefore can with the half half_len0 of the maximum length max_len0 of continuous zero as threshold value.

To sum up, judge sequence: when half1_cnt and half2_cnt is all less than the half of max_len0, sequence is Y; Otherwise when half1_cnt is greater than half2_cnt, sequence is Y; In other situations, sequence is Z.

5 start bits judge

When not having information, antenna is full width (Y sequence).When receiving a string data, first there is initiation of communication position, i.e. Z sequence.So when first Z sequence being detected, just start to receive number.When the center of the first series winding continuous " 0 " moves on to the center of the S3 of data_buf time, start bit may be have found, so start_flag is set to height.Then as bit synchronization starting point, the judgement of sequence is below carried out.

6 state machines and clock correction

This patent state machine goes control sequence to judge and clock correction.As shown in figure 11, state machine has seven states respectively: init state IDLE, first bit data position count status FIRST_CNT, clock correction " window " the state FIRST_WIN of the first bit data, first bit data sequence judges state FIRST_SEQ, other bit data positions count status BIT_CNT, clock correction " window " state REC_WIN and sequence judge state JUDGE_SEQ.

Time initialized, state machine is IDLE state.When initiation of communication position being detected, start_flag is set to 1, and state machine enters FIRST_CNT state, and digit counter bit_cnt starts counting.The moment of so just having put with start_flag, for starting point, carries out bit synchronization.Wait 128 clock period after start bit, the sequence in data_buf is the first bit data after start bit.Therefore, when digit counter bit_cnt counts 128, the first bit data just moves in data_buf completely, now can judge the first bit data.Therefore when bit_cnt=128, judge half1_cnt, the relation of half2_cnt and max_len0/2, thus judge it is what sequence: if X sequence has put seq_x, if Y sequence has put seq_y, if Z sequence has put seq_z.Meanwhile, when bit_cnt=128, detect the center zero_ptr of next bit data zero, for position deviation.When next sequence is Z sequence, center should be 128-16=112, if but lose clock, zero_ptr can be greater than 112, if add the clock period, zero_ptr can be less than 112.Consider that zero_ptr varies, directly subtract each other with 112 and compare difference, have negative and occur, in order to represent convenient, zero_ptr adds 16 certainly than 112 greatly, remember counts corrected device rec_cnt=(zero_ptr+16)-(128-16)=zero_ptr-96.So just can represent clock jitter number with rec_cnt.In like manner when next sequence is X sequence, be designated as rec_cnt=(zero_ptr+16)-(64-16)=zero_ptr-32.

Because clock during pause has certain deviation, so before and after we counter counts bit_cnt=128 in place, open " window " of 32 clock period centered by 128, detect the center of next bit data continuous " 0 ", thus position deviation.This " window " just represents with clock correction " window " state FIRST_WIN.When digit counter bit_cnt counts 127-16=111, enter FIRST_WIN state; When bit_cnt counts 127+16=134, terminate FIRST_WIN state.Could position deviation when only having next sequence to be X, Z sequence, and once to correct the clock jitter number that can correct be ± 16.If next sequence is Y sequence, there is no continuous zero " 0 ", this clock jitter can not be corrected.In communication process, there will not be continuous two Y sequences, only sign off position.Therefore the window of 32 clock cycle length can position number deviation be ± 8.In other words, in a data, clock many 8 cycles or few 8 cycles can correct.

When digit counter bit_cnt counts 127+16=134, state machine enters FIRST_SEQ state, and the sequence according to having judged does respective handling.If when bit_cnt=128, the sequence of judgement is seq_x or seq_z, and in low 4 writes 1101 or 0111 of seq_buf, juxtaposition plays sequence effective marker seq_val.If the sequence judged is seq_y, owing to after start bit can only be, now start bit likely misjudgment, so get back to IDLE state by state.Simultaneously under FIRST_SEQ state, by the number in counts corrected device rec_cnt to bit_cnt, start the judgement of next sequence, this completes clock jitter and correct.

If sequence is not Y sequence, state machine enters a count status BIT_CNT, identical with FIRST_CNT.Then, as bit_cnt=127-16, state enters correction " window " state REC_WIN, identical with FIRST_WIN.Again as bit_cnt=127+16, state enters sequence and judges state JUDGE_SEQ, similar to FIRST_SEQ.Can have Y sequence unlike the sequence judged in JUDGE_SEQ state, when sequence is Y sequence, after seq_buf, four are labeled as 1111.In addition, because two continuous sequences are sign off positions for " ZY " or " YY ", so when seq_buf is " 0111-1111 " or " 1111-1111 ", sign off mark end_flag will have been put, get back to IDLE state.If do not have end_flag, state machine proceeds to the judgement that BIT_CNT carries out next bit data, until sign off position detected.

As Figure 12 and Figure 13, illustrate judgement start bit, the change of data in the change of key signal and data buffer storage when the judgement of the first bit data and clock correction.1. the moment, first length is that continuous " 0 " of n just moves in data_buf completely, and what the center pointer zero_ptr of " 0 " represented is [n/2+1] ([] floor operation).2. the moment, the center of first continuous " 0 " has moved on to the center of the S3 of data_buf, detects initiation of communication position, has put start bit mark start_flag.3. the moment, bit_cnt=127-16, state machine enters first clock and corrects " window " state FIRST_WIN.4. the moment, bit_cnt=128, carries out sequence and judges and clock jitter judgement.As in example, the zero number half1_cnt in first half bit period is greater than the half of the longest zero-length max_len0, and the zero number half1_cnt in first half bit period is greater than the zero number half0_cnt in later half bit period, and therefore sequence is Z sequence, has put seq_z.Now, if clock does not have deviation, " 0 " center of second sequence should in the center of S3 or S1.But zero_ptr=116 in this example, second sequence " 0 " center apart from S3 center location difference 4, so lost the clock of 4 clock period.rec_cnt=zero_ptr-96=116-96=20。5. the moment, cnt=127+16, clock correction " window " terminates, and the value of counts corrected device rec_cnt is assigned to bit_cnt, starts the counting of next bit data.If do not have loss of clock, now bit_cnt should from 16.And bit_cn is from 20 in this example, such starting point has postponed 4 clock period, is equivalent to 4 clocks that compensate for loss.

7 decodings

By distortion Miller code, logical one can be expressed as X sequence (1101), and logical zero can be expressed as Y sequence (1111) or Z sequence (0111).Therefore, when seq_val is effective, if seq_buf is low 4 when being " 1101 ", data are " 1 ", and in other situations, data are " 0 ".Namely time seq_buf [3:0]=1101, cur_bit is 1, and in other situations, cur_bit is 0.Put bit_en, mark current data is effective simultaneously.

The present embodiment designs under Taiwan Semiconductor Mfg 180nm technique, and final chip is surveyed known, according to the different parameters of protocol changes pause, changes the different field intensity of antenna RF, the correct data that this example can solve.As Figure 14 be demodulation width during pause and corresponding pause during the minimum frequency that allows of clock, it is 037 ~ 62us that this example can solve pause demodulation width in scope, and area covered by agreement can also leave certain nargin., therefore pause demodulation width is from 62 ~ 11us, and demodulation width is less, and the minimum clock frequency of permission is lower, because the clock jitter number that can correct is certain.After pause demodulation width is less than 11us, the time minimum clock frequency allowed during pause increases on the contrary, because at least adopt three continuous zero just think data zero.So pause.In addition in test process, add certain noise in antenna RF, this example also can well demodulate correct data.

The above, be only preferred embodiment of the present invention, be not intended to limit protection scope of the present invention, and all any amendments done within the spirit and principles in the present invention, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (1)

1. there is a receipts counting method for the non-contact IC card of robustness, it is characterized in that, realize according to the following steps successively in non-contact IC card:

Step (1), the regulator rectifier circuit in AFE (analog front end) obtains the DC voltage needed for non-contact IC card work from the RF carrier signal that antenna RF receives;

Step (2), the carrier extract circuit in AFE (analog front end) extracts RF carrier clock RF_CLK from described carrier wave, and input clock recovers or commutation circuit;

Step (3), after the described clock recovery of AFE (analog front end) or commutation circuit receive carrier clock RF_CLK, during the pause of gap, switch to frequency close to the clock of 13.56MHz, be input in this, as sampling clock CLK_S in the data buffer storage of the 128+16 position of receiving in digital-to-analogue block

Step (4), the data RF_DIN of demodulator circuit over-sampling demodulation from RF carrier wave, under described sampling clock CLK_S is synchronous, is moved in described 128+16 bit data buffer memory;

Step (5), described receipts digital-to-analogue block utilizes the data in data buffer storage to go to detect initiation of communication position: think that when detecting and being no less than continuous three zero data are " 0 ", the first series winding continuous " 0 " detected is as initiation of communication position, and using the center of this continuous " 0 " as bit synchronous benchmark, record the length of the longest " 0 " continuously;

Step (6), when the center of continuous " 0 " moves on in data buffer storage, use X sequence, Y sequence and Z sequence represent three kinds of distortion Miller code sequences, with the center of the centers of 32nd ~ 63 as front 64 half bit periods, with the center of the centers of 96th ~ 127 as rear 64 half bit periods: current 64 half bit periods, in rear 64 half bit periods, the number of " 0 " is all less than a half of the longest " 0 " length continuously, then whole bit period does not have " 0 ", data are described Y sequence, when in described front 64 half bit periods, the number of " 0 " is greater than the number of " 0 " in described rear 64 half bit periods, data are Z sequence, X sequence is thought in other situations,

Step (7), state machine in described receipts digital-to-analogue block is behind the initiation of communication position obtained received in step (5) and bit synchronization benchmark, the first bit data after 128 clock period judge described initiation of communication position: if the first bit data is Y sequence, then return step (5), again detect initiation of communication position;

Step (8), after described state machine synchronous base in place, the sequence of carrying out described distortion Miller code every 128 clock period judges, the same step of determination methods (6);

Step (9), centered by described bit synchronization benchmark, open the correction " window " of 32 clock period, detect the center of continuous " 0 " of next bit data:

If Z sequence, the center of " 0 " and the difference of the position in corresponding data buffer storage 96th ~ 127 relatively continuously,

If X sequence, the difference of the position relatively continuously in " 0 " and the position in corresponding data buffer storage 32nd ~ 63,

If Y sequence, think that whole bit period does not have " 0 ", do not go comparison position deviation,

With the deviation adjusting bit synchronization benchmark of described center at the end of described correction " window ", correcting range is ± 8 clock period,

Step (10), at the end of described correction " window ", the sequence judged by step (8), judge sequence buffer memory seq_buf [3:0], X sequence is write 1101, Y sequence and is write 1111, Z sequence writes 0111, and juxtaposition plays sequence effective marker seq_val;

Step (11), seq_buf [7:0] is 8 and receives buffer memory sequence, what seq_buf [3:0] was seq_buf [7:0] is low four, represent the sequence be currently received, what seq [7:4] was seq_buf [7:0] is high four, represent the sequence that a reception arrives, after decoding, obtain: present bit cur_bit, the effective marker bit_en of present bit is when seq_buf [3:0]=1101, the sequence be namely currently received is X, cur_bit is 1, in other situations, cur_bit is 0, when seq_buf [7:0]=0111-1111 or 1111-1111, the sequence being namely consecutively detected a moment and current time is ZY or YY, terminating mark end_flag is 1.