CN103098029B - The dynamic optimization of background memory system interface - Google Patents

Abstract

Give internal controller and the structure of memory circuitry interface and the corresponding operating technology of the accumulator system of device for such as flash card or other similar structures.Interface between controller circuitry and memory circuitry includes feedback processing, wherein monitors the amount of error occurred due to controller storage transmission and can revise transmission characteristic (such as clock rate, driving intensity etc.) accordingly.Give the technology of the performance of controller storage (or " backstage ") interface for dynamically optimizing Nonvolatile memory system.Accumulator system is typically designed to certain error margins amount with the mistake for may then pass through ECC correction.In most cases, such as when device is new, the ECC ability of system has exceeded the ability needed for correction data storage mistake.In these cases, the non-zero of this error correction capability is internally distributed to back office interface by accumulator system.This allows this interface to operate with such as more speed or lower power, although this will likely result in transmitting path error.This system can also calibrate back office interface to determine the amount of error obtained from each operating condition, it is allowed to arrange the operating parameter of back office interface according to the amount of error distributing to transmission process.

Description

The dynamic optimization of background memory system interface

Technical field

The application relates to the operation of the Reprogrammable Nonvolatile memory system of such as semiconductor flash memory, more particularly, to the internal interface between controller and the memory circuitry of accumulator system.

Background technology

The solid-state memory of non-volatile memories electric charge, the solid-state memory of the EEPROM being particularly encapsulated as small-sized specification card and quick flashing EEPROM form can recently become the storage in various movement and handheld device, particularly massaging device and consumption electronic product and select.Being different from also is the RAM(random access memory of solid-state memory), flash memory is non-volatile, even and if still keeping the data that it is stored after cutting off the electricity supply.And, unlike ROM(read only memory), flash memory is similar to disk storage device and rewritable.Although cost is higher, but flash memory is just by more in massive store is applied.The Conventional mass storage of rotating magnetic media based on such as hard disk drive and floppy disk is not suitable for mobile and handheld environment.This is because disk drive tends to volume greatly, easily there was a mechanical failure, and has high latency and high power requirement.These undesirable attributes make the major part that is stored in based on dish move and impracticable in portable use.On the other hand, embedded and removable card form both flash memory is preferably suited for mobile and handheld environment due to its small size, low-power consumption, high speed and high reliability feature.

Quick flashing EEPROM is similar to EPROM(Electrically Erasable Read Only Memory) it is that it is can be wiped free of and make new data to be written to or be " programmed " into the nonvolatile memory in its memory cell.In scene effect transistor arrangement, both utilize floating (being not connected with) conductive grid on channel region between source electrode and drain region, that be positioned in Semiconductor substrate.Then control gate is provided on floating grid.By the quantity of electric charge being retained on the floating gate to control the threshold voltage characteristic of transistor.It is, for the electric charge of given level on floating grid, exist and must be applied to control gate before " conducting " transistor to allow the relevant voltage (threshold value) of conduction between its source electrode and drain region.Specifically, the flash memory of such as quick flashing EEPROM allows the memory cell of simultaneously erased whole piece.

Floating grid can keep the electric charge of a scope, therefore may be programmed into any threshold voltage levels in threshold voltage window.Minimum and maximum threshold level by device defines the size of (delimit) threshold voltage window, and this minimum and maximum threshold level is again corresponding to may be programmed into the scope of the electric charge on floating grid.Threshold window generally depends on the characteristic of storage component part, working condition and history.Each different distinguishable threshold voltage level range in this window may be used for the clear and definite memory state of designating unit in principle.

Generally by one of two kinds of mechanism, the transistor serving as memory cell is programmed into " programming " state.In " thermoelectron injection ", the high voltage being applied to drain electrode accelerates the electronics through substrate channel region.Meanwhile, the high voltage being applied to control gate pulls thermoelectron on thin gate-dielectric to floating grid.In " tunneling injection ", relative to substrate, high voltage is applied to control gate.In this way, electronics is moved to from substrate (intervening) floating grid of centre.Although having used term " to program " charge storage elements being initially wiped free of described by injecting electrons into memory cell so that the write to memorizer of change memory state, but now the most can with such as " write " or the exchange use of term more often of " record ".

Storage component part can be wiped by number of mechanisms.For EEPROM, can by relative to control gate to undercoat high voltage in case the electronics tunnel in induction floating grid cross thin-oxide to substrate channel region (that is, Fowler-Nordheim tunnelling) electrically-erasable memory unit.Generally, EEPROM can byte-by-byte wipe.For quick flashing EEPROM, this memorizer can disposably all electrically erasable or erasable piece of the most one or more minimum ground electrically erasable, the most minimum erasable piece can be made up of one or more sectors, and each sector can store 512 bytes or more data.

Storage component part generally includes the one or more memory chips can being installed on card.Each memory chip includes the array of the memory cell supported by the peripheral circuit of such as decoder and erasing, write and read circuit.More complicated storage component part also works together with carrying out the external memory controller of intelligence and the storage operation of higher level and interface.

There is the commercial successful non-volatile solid state memory device of many most just used.These storage component parts can be quick flashing EEPROM, maybe can use other kinds of Nonvolatile memery unit.The example of flash memory and system and manufacture method thereof is given in United States Patent (USP) No.5,070,032,5,095,344,5,315,541,5,343,063 and 5,661,053,5,313,421 and 6,222,762.Specifically, in United States Patent (USP) No.5,570,315,5,903,495,6, describe the flush memory device with NAND string structure in 046,935.And, also manufactured nonvolatile memory device by the memory cell of the dielectric layer having for storing electric charge.Replace previously described conducting floating gate element, use dielectric layer.By " NROM:A Novel Localized Trapping, the 2-Bit Nonvolatile Memory Cell " of Eitan et al., IEEE Electron Device Letters, Vol.21, No.11,2000 November, 543-545 page describes this storage component part utilizing dielectric storage element.ONO dielectric layer extends across the raceway groove between source electrode and drain diffusion.Electric charge for a data bit is positioned in and drains in adjacent dielectric layer, and the electric charge being used for another data bit is positioned in the dielectric layer adjacent with source electrode.Such as, United States Patent (USP) No.5,768,192 and 6,011,725 discloses and has capture (trapping) the dielectric Nonvolatile memery unit being clipped between two silicon dioxide layers.Realize multi-state data by the binary condition reading the charge storage region being spatially separated in this electrolyte respectively to store.

In order to improve reading and program performance, concurrently read or programmed array in multiple charge storage cells or memory transistor.Therefore, one " page " memory component is read or programmed together.In existing memory architecture, row generally comprises the page of several intertexture or it may be constructed one page.All memory components of one page will be read or programmed together.

In flash memory system, erasing operation may spend ratio to read and the long almost an order of magnitude of programming operation.Therefore, it is desirable to have the erasing block of abundant size.In this way, the time that clashes can be split on the memory cell of jumpbogroup.

The person's character of flash memory imply that data must be written to the memory location being wiped free of.Data if from certain logical address of main frame are to be updated, and a kind of mode is to rewrite more new data in identical network memory position.It is, logic does not changes to physical address map.But, this will imply that first needs are wiped free of by the whole erasing block comprising this physical location, then with the rewriting data being updated.This update method efficiency is low, because its needs clash and rewrite whole erasing block, if data the most to be updated occupy a fraction of situation of erasing block.Also will cause the erasing recirculation of the higher frequency of memory block, it is contemplated that the effective durability during the memorizer of this type, this is undesirable.

The data transmitted by the external interface of host computer system, accumulator system and other electronic systems are addressed and are mapped to the physical location of flash memory system.Generally, system produce or the address of data file that receives is mapped to according to the logical block of data in the continuous logic address space of different range set up into system (hereinafter referred to " LBA interface ").The range of address space is usually enough to the four corner of the address that covering system can process.In one example, disk storage driver is communicated with computer or other host computer systems by such logical address space.This address space has the range of the enough total data memory capacity of addressing disk drive.

Making great efforts to be improved the performance of storage component part by reduction power consumption and increase device speed.As it has been described above, nonvolatile memory device is generally formed by controller circuitry and one or more memory chips of being connected to each other by bus structures.Controller/storage component part the interface of all magnitudes of voltage as used and frequency the situation generally according to expection worst condition that arranges arrange to there is enough safe clearances thus avoiding equipment fault.Thus, in most of the cases, interface operates not reach optimal conditions.Therefore the limiting factor in terms of this interface is probably device performance, therefore this is the space of the improvement for the design to this interface.

Summary of the invention

According to the general aspect of the present invention, the method giving operation Nonvolatile memory system.This Nonvolatile memory system includes: controller circuitry, has memory interface；Memory circuitry, has array and the control unit interface of Nonvolatile memery unit；And bus structures, it is connected to memory interface and the control unit interface of described memory circuitry of described controller circuitry, for transmitting data and order between described controller circuitry and described memory circuitry.Described accumulator system can tolerate from data from controller transmission to write memory array until data are being read back at controller the cumulative error being received as the first non-zero amount only subsequently from memory array.The method includes: described controller circuitry to the first non-zero joining the first amount of error via bus-structured sub data transmission between described controller circuitry and described memory circuitry, the write of the data that the residue of described first amount of error is assigned on described memory circuitry, stores and reads.Described controller circuitry arranges transmission characteristic between described controller circuitry and described memory circuitry and allows to reach the mistake of Part I to operate.

In other respects, the method that operation has the Nonvolatile memory system of controller circuitry and memory circuitry is given.Described controller circuitry is by being transmitted improper correction to each being processed to of each multiple values of the bus-structured one or more operating parameters connecting controller and described memory circuitry.This process includes: from described controller transmission circuit through described controller, the data set of given data pattern is transferred to described bus structures；And received from described bus-structured data set by the reception circuit on described memory circuitry.Being stored in the buffer storage on described memory circuitry by the data set of reception, the data set that then will be stored in the described buffer storage on described memory circuitry is transferred to described bus structures by the transmission circuit on described memory circuitry and is not written in described array.Received from described bus-structured data set by the reception circuit on described controller；And the data set being received and the comparison of known pattern.Compare based on this, determine one or more parameters for being used with the amount of error being associated at transmission.Operate described accumulator system subsequently to allow the first non-zero amount of error in the data transmission between described controller circuitry and memory circuitry, wherein said controller circuitry according to based on determined by the error of transmission calibration process of amount of error that is associated carry out the value of selection manipulation parameter.

According to another general aspect of the present invention, Nonvolatile memory system has: controller circuitry, including memory interface and logic circuit；And memory circuitry, including array, control unit interface and the logic circuit of Nonvolatile memery unit.This accumulator system also includes bus structures, is connected to the memory interface of described controller circuitry and the control unit interface of described memory circuitry for transmitting data and order between controller and memory circuitry.The logic circuit being connected between feedback processing circuit data transfer period between described controller and described memory circuitry on described controller circuitry and described memory circuitry is to receive the information about the amount of error produced due to transmission, and is connected to one or both of described memory interface and described control unit interface to adjust the characteristic of the transmission between described controller circuitry and described memory circuitry in response to described amount of error.

In other respects, the method that operation includes the Nonvolatile memory system of Nonvolatile memory circuit and controller circuitry is given.The logic circuit on first in described controller circuitry and memory circuitry produces the first cryptographic Hash from data set.Transmit described data set and the first cryptographic Hash by the interface on first in described controller circuitry and memory circuitry to bus structures, and receive described data set and described first cryptographic Hash by the interface on second in described controller circuitry and memory circuitry from described bus structures.Then the logic circuit on second in described controller circuitry and memory circuitry produces the second cryptographic Hash from the data set received, then on second in described controller circuitry and memory circuitry, compare the first cryptographic Hash of reception and described second cryptographic Hash.Based on the first cryptographic Hash to receiving of the logic circuit on second in described controller circuitry and memory circuitry and the comparison of described second cryptographic Hash, the characteristic of the data transmission that described system determines whether to change between described controller circuitry and described memory circuitry.

Various aspects of the invention, advantage, feature and embodiment are included in the following description of its illustrative examples, and this description should be considered in conjunction with the accompanying.All patents cited herein, patent application, article, other publications, document and things are herein incorporated by quoting its whole this for all purposes.As for definition or any inconsistent or repugnance of use of the term between the publication being arbitrarily incorporated to, document or things and the application, should be as the criterion with the definition of the application or use.

Accompanying drawing explanation

Fig. 1 schematic illustration is adapted for carrying out the major hardware components of the accumulator system of the present invention.

Fig. 2 schematic illustration Nonvolatile memery unit.

Fig. 3 illustrates the source-drain current I of four different charge Q 1-Q4 that can store for floating grid in any one time selectivity_DWith control gate voltage V_CGBetween relation.

Fig. 4 A schematic illustration is organized as the string of the memory cell of NAND string.

Fig. 4 B illustrates the example of the NAND array 210 of the memory cell being made up of all NAND strings 50 as shown in Figure 4 A.

Fig. 5 illustrates the page of memory unit such as organized being sensed or programmed in parallel by NAND configuration.

Fig. 6 (0)-6(2) illustrate the example programming a group 4-state memory cells.

Fig. 7 A-7E illustrates programming or the reading of the 4-status register with 2 given code codings.

Fig. 8 example memory is managed by the memory manager as the component software being present in controller.

Fig. 9 illustrates the software module of background system.

Figure 10 A(i)-10A(iii) schematic illustration logical groups and unit block between mapping.

Mapping between Figure 10 B schematic illustration logical groups and unit's block.

Figure 11 is the block diagram illustrating the feedback mechanism for determining interface integrity based on existing structure.

Figure 12 is to illustrate wherein feedback mechanism to use hash engine to determine the block diagram of the embodiment of interface integrity.

Figure 13 is the figure of the example of the hashed value being shown through EBI transmission data and generation.

Figure 14 schematic illustration contributor to the bit-errors in accumulator system.

Figure 15 may be used for illustrating the operation of the pseudo-returning method in back office interface.

Figure 16 and Figure 17 corresponds respectively to the block 705 and 709 of Figure 15.

Figure 18 is to illustrate transmission BER relative data bus voltage and the simulation drawing of data transfer rate.

Figure 19 is the block diagram of this crosstalk in the accumulator system illustrating bus structures use multi-memory data/address bus.

Detailed description of the invention

Accumulator system

Fig. 1 to Fig. 7 provides the example memory system that wherein can realize or illustrate various aspects of the invention.

Fig. 8 to Figure 10 illustrates preferred memorizer and block frame structure for realizing various aspects of the invention.

Figure 11-13 illustrates the use of the adaptability internal interface between controller and one or more memory circuitry.

Fig. 1 schematic illustration is adapted for carrying out the major hardware components of the accumulator system of the present invention.Accumulator system 90 is generally operated together with main frame 80 by HPI.Accumulator system is typically the form of the accumulator system of storage card or embedding.Accumulator system 90 includes that it operates the memorizer 200 controlled by controller 100.Memorizer 200 includes one or more arrays of the Nonvolatile memery unit being distributed on one or more IC chip.Controller 100 includes interface 110, processor 120, optional coprocessor 121, ROM122(read only memory), RAM130(random access memory) and optional programmable non-volatile memory 124.Interface 110 has another assembly of an assembly of controller and main frame interfaces and interface to memorizer 200.The firmware being stored in non-volatile ROM 122 and/or optional nonvolatile memory 124 provides code to realize the function of controller 100 for processor 120.Error-correcting code can be processed by processor 120 or optional coprocessor 121.In an alternative embodiment, controller 100 is realized by state machine (not shown).In another embodiment, controller 100 realizes in main frame.

Physical memory structure

Fig. 2 schematic illustration Nonvolatile memery unit.Memory cell 10 can be realized by the field-effect transistor of the charge storage elements 20 with such as floating grid or dielectric layer.Memory cell 10 also includes source electrode 14, drain electrode 16 and control gate 30.

There is the commercial successful non-volatile solid state memory that many is the most just using.These storage component parts can use different types of memory cell, and each type has one or more charge storage cell.

Typical Nonvolatile memery unit includes EEPROM and quick flashing EEPROM.The example of EEPROM cell and manufacture method thereof is given in United States Patent (USP) no.5,595,924.Flash EEPROM cell, its use in accumulator system and the example of manufacture method thereof is given in United States Patent (USP) No.5,070,032,5,095,344,5,315,541,5,343,063,5,661,053,5,313,421 and 6,222,762.Specifically, in United States Patent (USP) No.5,570,315,5,903,495 and 6, describe the example of the storage component part with NAND cell structure in 046,935.And, by Eitan et al. at " NORM:A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell ", IEEE Electron Device Letters, Vol.21, No.11, in November, 2000, in 543-545 page and in United States Patent (USP) No.5,768,192 and 6, describe the example of the storage component part utilizing dielectric storage element in 011,725.

It practice, the conductive current of the source electrode and drain electrode generally striding across unit by the sensing when applying reference voltage to control gate reads the memory state of this unit.Therefore, for each given electric charge on the floating grid of unit, the corresponding conductive current about fixing reference control gate voltage can be detected.Similarly, the scope of the electric charge being programmed on floating grid defines corresponding threshold voltage window or corresponding conduction current window.

Or, replace detection conductive current between the current window divided, it is possible to be that the given memory state being under test arranges threshold voltage at control gate, and detect conductive current and be less than and be also above threshold current.In one embodiment, by checking that the speed that conductive current discharges through the electric capacity of bit line realizes relative to the threshold current detection to conductive current.

Fig. 3 illustrates can be with the source-drain current I of four different charge Q 1-Q4 of selectivity storage for the floating grid when any one time_DWith control gate voltage V_CGBetween relation.The I of four solid lines_DV relatively_CGCurve represents four possible charge level that correspond respectively to four possible memory states, that can be programmed on the floating grid of memory cell.As an example, the threshold voltage window scope of a group unit can be from 0.5V to 3.5V.By threshold window is divided into five regions with the interval of each 0.5V, expression one respectively of can demarcating has been wiped and the seven of six states programmed possible memory states " 0 ", " 1 ", " 2 ", " 3 ", " 4 ", " 5 ", " 6 ".Such as, if using the reference current IREF of 2 μ A as shown, then may be considered that with the unit of Q1 programming and be in memory state " 1 ", because its curve intersects with IREF in the region of the threshold window demarcated by VCG=0.5V and 1.0V.Similarly, Q4 is in memory state " 5 ".

As from the above, it can be seen that the state making memory cell store is the most, its threshold window divides the finest.Such as, storage component part can have containing scope from the memory cell of the threshold window of-1.5V to 5V.This provides the Breadth Maximum of 6.5V.If memory cell to store 16 states, the most each state can take up in threshold window from 200mV to 300mV.This would be required to the higher degree of accuracy in programming and read operation so as to realize the resolution required.

Fig. 4 A schematic illustration is organized as the string of the memory cell of NAND string.NAND string 50 includes by its source electrode and drain electrode a series of memory transistor M1 of daisy-chain connection, M2 ... Mn(such as n=4,8,16 or bigger).Transistor S1, S2 is selected for a pair to control memory transistor chain respectively via the source terminal 54 of NAND string and drain electrode end 56 and outside connection.In memory arrays, when drain selection transistor S1 turns on, source terminal is couple to source electrode line (see Fig. 4 B).Similarly, when drain electrode selects transistor S2 conducting, the drain electrode end of NAND string is couple to the bit line of memory array.Each memory transistor 10 in this chain takes on memory cell.It has the electric charge for storing specified rate to represent the charge storage cell 20 of the memory state being intended to.The control gate 30 of each memory transistor allows the control to read and write operation.As will be from Fig. 4 B, the control gate 30 of respective memory transistor of row of N AND string be all connected to identical wordline.Similarly, the control gate 32 of each selection transistor S1, S2 provides the control gone here and there NAND via its source terminal 54 and drain electrode end 56 respectively to access.Equally, the corresponding control gate 32 selecting transistor of row of N AND string is all connected to identical selection line.

When reading or verify the addressed memory transistor 10 in NAND string during programming, provide suitable voltage for its control gate 30.Meanwhile, remaining the unaddressed memory transistor in NAND string 50 is fully on by the sufficient voltage that is applied in its control gate.In this way, the source terminal gone here and there from the source electrode of each memory transistor to NAND establishes conductive path effectively, and the same drain electrode end 56 from the drain electrode of each memory transistor to this unit establishes conductive path effectively.In United States Patent (USP) No.5,570,315, describe in 5,903,495,6,046,935 there is the storage component part of this NAND string structure.

Fig. 4 B illustrates the example of the NAND array 210 of the memory cell being made up of all NAND strings 50 as shown in Figure 4 A.Along each column of NAND string, the such as bit line of bit line 36 is couple to the drain electrode end 56 of each NAND string.Along often arranging NAND string, the such as source electrode line of source electrode line 34 is couple to the source terminal 54 of each NAND string.And, the control gate along the row of memory cells in a row NAND string is connected to the wordline of such as wordline 42.Control gate along the row selecting transistor in a row NAND string is connected to such as select the selection line of line 44.The full line memory cell during this row NAND goes here and there can be addressed by the suitable voltage in the wordline of a row NAND string and selection line.Memory transistor in NAND goes here and there just is read out, remaining memory transistor in this string turns on (turn on hard) firmly via its relevant wordline, in order to the electric current flowing through this string substantially depends on the level of the electric charge of storage in the unit being read.

Fig. 5 illustrates the page of memory unit such as organized being sensed or programmed in parallel by NAND configuration.Fig. 5 mainly illustrates a pile NAND string 50 in the memory array 210 of Fig. 4 B, is explicitly illustrated in the details such as Fig. 4 A of the most each NAND string." page " of such as page 60 is the group of memory cell being enabled to be sensed or programmed in parallel.This is realized by the sensing amplifier 212 of corresponding page.The result of sensing is latched in the latch 214 of respective sets, and each sensing amplifier can be couple to NAND string via bit line.Enable page by the control gate being commonly connected to the unit of the page of wordline 42, and each unit that can be accessed by sensing amplifier can access via bit line 36.As an example, when sensing or the page 60 of programming unit respectively, sensing voltage or program voltage are respectively applied to common word line WL3 together with the suitable voltage on bit line.

The physical organization of memorizer

An important difference between flash memory and other kinds of memorizer is that unit must program from erased state.That is, floating grid is not it is first necessary to have electric charge.Then program and desired amount of electric charge is add backed to floating grid.It does not support to remove a part of electric charge to come less programming state from more programming state from floating grid.It means that more new data can not overwrite (overwrite) available data and must be written to the position being previously not written into.

Additionally, erasing to empty all electric charges from floating grid and to generally take the considerable time.For this reason, unit or to wipe the most page by page to be irksome and the slowest one by one.In practice, the array of memory cell is divided into the block of substantial amounts of memory cell.As universal for quick flashing EEPROM, block is the unit of erasing.That is, every piece comprises the minimal number of memory cell being wiped free of together.Although assembling a large amount of unit in block, to be wiped free of parallel, performance is wiped in raising, but large-sized piece also making to must cope with substantial amounts of renewal and discarding data.Just before block is wiped free of, need garbage reclamation to save the non-discarded data in block.

Each piece is generally divided into multipage.Page is programming or the unit read.In one embodiment, each page the section of being divided into and section can contain as basic programming operation and be once written of minimal number of unit.One page or many page datas are generally stored inside in row of memory cells.One page can store one or more sector.Sector includes user data and overhead data.Cross over multiple pieces of multiple array distribution and page can also operate as unit's block together with metapage.If they are distributed on multiple chip, then they can operate together with metapage as unit's block.

Multi-level unit (" MLC ") memorizer divide example

The nonvolatile memory of the most each memory cell storage long numeric data is described already in connection with Fig. 3.Object lesson is the memorizer formed by the array of field-effect transistor, and each field-effect transistor has the charge storage layer between its channel region and its control gate.Charge storage layer or unit can store the electric charge of a scope, cause the threshold voltage of a scope for each field-effect transistor.The range spans of possible threshold voltage is threshold window.When threshold window is divided into multiple subranges or the region of threshold voltage, each distinguishable region is for representing the different memory state of memory cell.Multiple memory state can be encoded by one or more binary digits.Such as, the memory cell being divided into four regions can support to be encoded as four states of 2 bit data.Similarly, the memory cell being divided into eight regions can support to be encoded as eight memory states of 3 bit data, etc..

All positions, complete sequence MLC Programming

Fig. 6 (0)-6(2) illustrate the example programming a group 4 state memory cells.Fig. 6 (0) illustrates and is programmed for representing this group of memory cells that memory state " 0 ", " 1 ", " 2 " are distributed with the four of " 3 " different threshold voltages respectively.Fig. 6 (1) illustrates the initial distribution of " being wiped free of " threshold voltage for the memorizer being wiped free of.Fig. 6 (2) is illustrated in the example of the most programmed memorizer afterwards of many memory cells.Substantially, unit initially has " being wiped free of " threshold voltage and programming can be moved into higher value and enter by checking level vV₁、vV₂And vV₃One of three regions demarcated.In this way, each memory cell may be programmed into one of three programmed state " 1 ", " 2 " and " 3 " or keeps not being programmed in " being wiped free of " state.Along with memorizer obtains more programming, the initial distribution of " being wiped free of " state as shown in Fig. 6 (1) will become narrower and erased state by " 0 " state representation.

Can use to have and represent each of four memory states compared with the 2-bit code of low level and high bit.Such as, " 0 ", " 1 ", " 2 " and " 3 " state is represented by " 11 ", " 01 ", " 00 " and " 10 " respectively.Can by under " complete sequence " pattern sensing and from memorizer read 2-bit data, in this " complete sequence " pattern, by respectively three sons all in relative to read description threshold value rV₁、rV₂And rV₃Carry out sensing and sense two together.

By turn MLC Programming and reading

Fig. 7 A-7E illustrates programming and the reading of 4 status registers with 2 given bit code codings.Fig. 7 A illustrates the threshold voltage distribution of 4 state memory array when each memory cell uses 2-bit code storage two bits.Such 2 bit codes are disclosed in United States Patent (USP) No.7,057,939.

Fig. 7 B illustrates higher page programming (high bit) of the 2 times programming schemes using 2 bit codes.Being programmed in second time of " 0 " higher page position, if relatively low page position is in " 1 ", then as by " not being programmed that " that memory state " 0 " is programmed into represented by " 1 ", logic state (1,1) is converted to (0,1).If relatively low page position is in " 0 ", then by being programmed into " 3 " from " middle " state, it is thus achieved that logic state (0,0).Similarly, if higher page to be maintained at " 1 ", and relatively low page has been programmed into " 0 ", then as by being programmed into represented by " 2 " by " middle " state, it would be desirable to from the conversion of " middle " state to (1,0).

Fig. 7 C illustrates higher page programming (high bit) in the 2 times programming schemes using 2 bit codes.High bit being programmed in second time of " 0 ", if relatively low page position is in " 1 ", then as represented by memory state " 0 " " will be programmed that " to be programmed into " 1 ", logic state (1,1) is converted to (0,1).If relatively low page position is in " 0 ", then by being programmed into " 3 " acquisition logic state (0,0) from " middle " state.Similarly, if higher page to be maintained at " 1 ", and relatively low page has been programmed into " 0 ", then as by being programmed into represented by " 2 " by " middle " state, it would be desirable to from the transformation of " middle " state to (1,0).

Fig. 7 D illustrates the read operation needed for distinguishing the relatively low level of 4 status registers with 2 bit code codings.First B operation it is read out to determine whether to read LM mark.If it can, higher page the most programmed and read B operation will be correctly created relatively low page data.On the other hand, if higher page is the most not programmed, the most relatively low page data will be read by A operation and is read.

Fig. 7 E illustrates the read operation needed for distinguishing the high bit of 4 status registers with 2 bit code codings.As seen from the diagram, higher page reads and needs is respectively relative to demarcation threshold voltages D_A、D_BAnd D_CReading A, read B and read 3 times of C readings.

For in the scheme by turn of 2 bit memories, the Physical Page of memory cell will store two logical data pages: corresponds to the lower data page of relatively low level and corresponds to the higher data page of high bit.

Binary system and MLC Memorizer divides

Fig. 6 and Fig. 7 illustrates the example of 2 (also referred to as " D2 ") memorizeies.As can be seen D2 memorizer has its threshold range or the threshold window being divided into four regions, it is intended that 4 states.Similarly, in D3, each unit stores 3 (relatively low, between and high bit), and there are 8 regions.In D4, there are 4 and 16 regions, etc..Along with the limited threshold window of memorizer is divided into more region, the resolution programming and reading necessarily will become finer.Along with memory cell configurations is for storing more multidigit, two problems occur.

First, when the threshold value of unit must program more accurately or read, program slower or read.It is true that in practice, (required in programming and reading) the sensing time by quantity along with the rank divided square and increase.

Second, flash memory has durability issues along with using aging.When power supply is repeatedly programmed and erased, by striding across dielectric tunnelling, electric charge passes in and out floating grid 20(back and forth and sees Fig. 2).Some are put and may become to be captured in the dielectric and will revise the threshold value of unit every time.It is true that along with use, threshold window is by gradually constriction.Therefore, MLC memory is normally provided as having between capacity, Performance And Reliability compromise.

On the contrary, it will be observed that for binary storage device, the threshold window of memorizer is only divided into two regions.This will allow the maximum surplus of mistake.Therefore, although but binary partition reduces in memory capacity will provide maximum Performance And Reliability.

In conjunction with the multipass described in Fig. 7, program and smooth transformation that reading technology provides between MLC and binary partition by turn.In the case, if only using relatively low level programmable memory, then it effectively becomes the memorizer of binary partition.Although the method is not to the scope optimizing threshold window completely such in the case of single stage unit (" SLC ") memorizer, but it has the boundary or the advantage of levels sensed used with system in the operation of the relatively low level of MLC memory.As will be described later, the method allows MLC memory " to be taken over for use " for use as binary storage device, otherwise or still.It should be understood, however, that MLC memory trends towards having tightened up operating specification.

Binary storage device and partial page program

The electric charge being programmed in the charge storage cell wanting a memory cell produces the electric field of the electric field of interference neighbor memory cell.This will affect the characteristic of the neighbor memory cell of the field-effect transistor actually with charge storage cell.Specifically, when sensed, memory cell will appear to have than its less disturbed time higher threshold level (or more be programmed).

Generally, if memory cell is programmed checking under first environment and is again read under different field environment owing to adjacent unit is programmed with different electric charges subsequently after a while, due to the coupling between the adjacent floating grid in the phenomenon being referred to as " Yupin effect ", reading accuracy may be impacted.Along with continuous higher integrated in semiconductor memory, along with internal cellular spacing is shunk, the perturbation (Yupin effect) of the electric field that the electric charge due to storage between memory cell causes becomes the most considerable.

It is designed to minimize the programming from the team member along same word line above in association with the programming technique of MLC by turn described in Fig. 7 disturb.As from Fig. 7 B, in the first pass of twice programming, the threshold value of unit at most moves the half distance more than threshold window.The impact of first pass is by final time compacting (overtake).At final time, threshold value only moves 1/4th of distance.In other words, for D2, the charge difference between adjacent cells is limited to 1/4th of its maximum.For D3, by three times, final all over charge difference being restricted to 1/8th of its maximum.

But, multi-pass programming technology will be damaged by partial page program by turn.Page is the group of the memory cell generally along a line wordline, and it is programmed together as unit.Nonoverlapping part of one page can be programmed respectively by multi-pass programming.But, due to be not this page all unit all final all in be programmed together, may complete, at one page, the big difference in being programmed that electric charge that creates afterwards between cells.Therefore, partial page program will cause bigger programming to be disturbed, and bigger surplus will be needed to be used for sensing accuracy.

In the case of memorizer is configured to binary storage device, the surplus of operation is wider with the surplus of the operation of MLC.In a preferred embodiment, binary storage device is configured to support sector's paging programming, in this partial page program, can program nonoverlapping part of this page respectively in one time of the multi-pass programming of team's one page.By with large-sized page operations, programming and reading performance can be improved.But, when page size write than main frame unit (sectors of usual 512 bytes) much bigger time, its use will be poor efficiency.The more effective use of such page is allowed with the granularity operation finer than one page.

Between binary system is relative to MLC, provided example.It should be understood that generally, memorizer that identical principle is applicable to have the grade of the first quantity and having than first memory between the memorizer of the grades of many second quantity.

Logically and physically block structure

Fig. 8 example memory unit is managed by the memory manager as the component software being present in controller.Memorizer 200 is organized as block, and every module unit is the least unit of erasing.Depending on implementation, accumulator system can utilize the unit of the most substantial amounts of erasing formed by block being polymerized to " unit's block " and also have " multiple units block " to operate.For convenience, this describes and the unit of erasing will be referred to as unit's block, although it is understood that some systems utilize the biggest the clashing unit and operate such as being formed " unit's block " by the polymerization of unit's block.

Memorizer 200 is accessed when main frame 80 must be applied under the file system operating in operating system.Generally, host computer system address each sector of wherein typing store 512 bytes data logic sector unit in data.And, main frame is generally read or write to accumulator system by the unit of Logic Cluster, and each Logic Cluster is made up of one or more logic sectors.In some host computer systems, optional host computer side memory manager can be there is to carry out the lower level memorizer management at main frame.In most of the cases, during read or write operation, main frame 80 actually sends order to accumulator system 90 and reads or the write packet section containing the data of a string logic sector with continuation address.

The memory manager 300 of memory side realizes in the controller 100 of accumulator system 90 to manage the storage of the data of the host logic sector between first block of flash memory 200 and to fetch.Memory manager includes foreground system 310 and background system 320.Foreground system 310 includes HPI 312.Background system 320 includes the multiple software modules for managing the unit's erasing of block, reading and write operation.Memory manager also maintains the System Control Data and catalogue data being associated with its operation between flash memory 200 and controller RAM130.

Fig. 9 illustrates the software module of background system.Background system mainly includes two functional modules: media management layer 330 and data stream and sequence layer 340.

Media management layer 330 is responsible for the logical data storage in tissue flash memory unit block structure.More details will be provided after a while in the part about " media management layer ".

The sequence of the sector of the data that data stream and sequence layer 340 are responsible between foreground system and flash memory and transmission.This layer includes order sorting unit 342, rudimentary sorting unit 344 and quick flashing key-course 346.More details will be provided after a while in the part about " low-level system explanation ".

Memory manager 300 preferred implementation is in controller 100.The logical address received from main frame is translated as the physical address in the memory array of wherein actual storage data by it, then grasps these address translation.

Figure 10 A(i)-10A(iii) schematic illustration logical groups and unit block between mapping.First block of physical storage has N number of physical sector of the data of the N number of logic sector for storing logical groups.Figure 10 A(i) illustrate from logical groups LG_iData, wherein logic sector presses continuous print logical order 0,1 ..., N-1.Figure 10 A(ii) illustrate that identical data are stored in unit's block by identical logical order.Unit's block is known as " order " when storing in this way.Generally, unit's block can have the data by different order storage, and in the case, unit is known as " non-sequential " or " confusion ".

Skew is there may be between the lowest address of the first block being mapped at lowest address and its of logical groups.In the case, logical sector address is unrolled the circulation at the top returning to logical groups as the bottom of logical groups in unit's block.Such as, at Figure 10 A(iii) in, unit's block stores in its primary importance started with the data of logic sector k.When reaching last logic sector N-1, it raps around to sector 0 the final data that storage is associated in its last physical sector with logic sector k-1.In a preferred embodiment, page label is used to identify the logical sector address of the beginning of the data of storage in the first physical sector of any skew, such as identification element block.When two block only page label differences, it will be considered that they have with its logic sector of similarly-ordered storage.

Mapping between Figure 10 B schematic illustration logical groups and unit's block.In addition to a small amount of logical groups that wherein data are currently being updated, each logical groups 380 is mapped to unique unit block 370.After logical groups has been updated, it can be mapped to different first blocks.Map information is maintained at logic and concentrates to physical directory, and this will be explained in greater detail in the following.

Adaptive controller - Memory interface

This part provides the use of feedback mechanism and processing unit, the transmission integrity of the internal controller-memory interface of its supervisory memory system, and can therefore adjust interface setting.This allows this system optimization interface capability.Such as, the power of this system can reduce or the bus clock of this interface can speed up, because this is typically internal performance bottleneck, so from the point of view of the outside (i.e. from main frame) of accumulator system, this allows the increase of performance.In case of transmission errors, the embodiment that helps and depend on fed back by interface integrity passes through other sensors or the help of parameter, and feedback processing unit may determine whether that adjusting interface arranges, is transmitted retrying or ignore this mistake.Discussion below also will be given in the context at storage card memory array being used to NAND framework as shown in Fig. 4 A, 4B and Fig. 5, but it is easy to internal interface, the memorizer of other forms and the Fei Ka get expanded to for other frameworks are similar to use, such as embedded system, SSD, etc..

Although following discussion can be based on each example embodiment to provide object lesson, but technology in this and structure go for having controller and the accumulator system of the multiple heaps that can be operating independently the most completely, wherein heap includes the still other kinds of nonvolatile memory of the same amount of either quick flashing that may be used for memory system data, and controller can use this system data to manage accumulator system.Except listed above other with reference in addition to, these can be included in the various accumulator systems that following United States Patent (USP), patent be open and provides in the patent No.: 7,840,766；US-2005-0154819-A1；US-2007-0061581-A1；US-2007-0061597-A1；US-2007-0113030-A1；US-2008-0155178-A1；US-2008-0155228-A1；US-2008-0155176-A1；US2008-0155177-A1；US-2008-0155227-A1；US-2008-0155175A1；12/348,819；12/348,825；12/348,891；12/348,895；12/348,899；12/642,584；12/642,611；US12/642,649；12/642,728；12/642,740 and 61/142,620.

Before example embodiment is discussed, this part is by by considering that the above problem overcome starts further.Controller-storage component part interface is used to come in controller (100, Fig. 1) and one or more NAND(example embodiment) transmission data between device (200, Fig. 1).(noting, this discusses the internal interface in accumulator system 90 relating between controller 100 and flash memory 200, and interface 110 is to control to make for the HPI with the PERCOM peripheral communication of accumulator system.) have been developed for different NAND Interface patterns and increase the interface capability compromise to speed, power consumption etc..Owing to this interface is typically performance bottleneck, so these interfaces have been pulled to the restriction for maximum system performance.In order to avoid error in data, interface arranges (such as voltage, frequency, driving intensity and conversion rate control) and is just being arranged to be used for the situation (extreme temperature, extreme load electric capacity, extreme voltage etc.) of worst condition.Thus, device is typically designed with worst condition safe clearance, and it becomes the big surplus under usual conditions.Under such usual conditions, interface arranges and can be optimized to much higher interface capability and not damage product reliability.Need not be such as in mechanism given below, storage component part will continue to operate at worst condition performance and arrange.

Such as, with 33MHz to accelerate 40MH to cross accelerate 50MHz and super cross accelerate 60MHz demarcate bus frequency time for respectively obtain simply comparing between the bursty data delivery time of 16 normal modes about 17%, 33% and 45% the great waiting time reduction.This illustrates in Table 1, and wherein row are frequency, corresponding cycle (t_cyc), transmit the time of 2142 byte datas and relative to the velocity rate of the speed when 33MHz.

In the prior art, for given product, flash interface performance is normally provided as fixed performance.Then, design is in view of worst case design.In some products, flash interface is arranged for " close to worst condition ", it is allowed to some interface capabilities optimize, but risk the risk of the error in data of some relatively low device outputs or increase.

This part provides feedback mechanism and processing unit, and this feedback mechanism and processing unit monitor interface capability integrity and adjust interface accordingly and arrange so that optimized interface performance.In case of transmission errors, feedback processing unit (fed back by interface integrity and may pass through other sensors or the help of parameter) may determine whether that adjusting interface arranges, is transmitted retrying or ignore this mistake.In the case of not having error of transmission, this feedback processing unit may decide that to stay interface to arrange same as before or revise interface and arranges to increase interface capability.Additionally, can design interface integrity feedback mechanism by this way: feedback processing unit can obtain different grades of information, the most binary pass through/unsuccessfully indicate, pass through/unsuccessfully plus the quantity of mistake or pass through/unsuccessfully plus the quantity of mistake plus errors present.

According to this embodiment, feedback mechanism can utilize existing period base structure or can be the most optimised by the dedicated mechanism of such as Hash engine.Such dedicated mechanism can realize with hardware, software or combinations thereof.Hash engine can also be supplemented by the error correction engine of error of transmission can be corrected.Such method, by allowing the bit error rate of interface one rank of reply, still reaches optimum performance simultaneously.Transmission calibration capability is valuable, because the design in the prior art for the ECC of NAND position fault only accounts for memorizer mistake itself, and does not considers the contingent interface error when data transmit between controller and storage component part.Along with interface capability raises, the probability of error of transmission raises.Make to leave over ECC and reduce and leave over ECC in performance and for the ability in terms of the probability of irrecoverable error tackling interface error.Design specialized interface error correction engine can allow " dividing and rule ", allow leave over ECC only focus on NAND produce mistake.(the other background detail about ECC can find in following United States Patent (USP), patent disclosure and number of patent application: 2009/0094482；7,502,254；2007/0268745；2007/0283081；7,310,347；7,493,457；7,426,623；2007/0065119；2007/0061502；2007/0091677；2007/0180346；2008/0181000；2007/0260808；2005/0213393；6,510,488；7,058,818；2008/0244338； 2008/0244367；2008/0250300 and 2008/0104312.)

But Figure 11 is to illustrate such feedback mechanism block diagram based on common prior art existing NAND/ controller base structure.This is by some in the concept involved by help further illustration and the alternative embodiment of offer compliant interface.In fig. 11, with this discussion relevant element is only had been explicitly shown, and deletes other elements to simplify this discussion.Is ASIC core 411, ECC circuit 413, output buffer 415, input buffer 425, transmission circuit 417 and reception circuit 427 on controller 100.Although being shown in which as separating, but can not be so in actual realization: and input or output buffer can be overlapping or can be identical；Transmitting and receive can be shared element or even can be identical；ECC circuit can be implemented as the software in ASIC core；Etc..In memory side 200, the element illustrated is reading circuit 431 and transmits circuit 441(they again can be partially or completely overlapping), Input Data Buffer 433 and output data buffer 443(similarly, they can be single buffer) and NAND core 435.Then controller 100 and memory circuitry are connected by bus structures 401.

It is through transmission circuit 417 and on bus structures 401 and to output data buffer 415 from ASIC core 411 for once receiving the general flow of master data set at controller 100.On memorizer 200, data are sent to Input Data Buffer 433 from bus by receiving circuit 431, are then written in NAND core 435.Subsequently, when main frame desires access to these data, these data are read into output data buffer 443 from NAND core 435, it is sent in bus structures 401 by transmission circuit 441, then by the Input Data Buffer 425 receiving circuit 427 and reading into from bus controller. accumulator system generally uses error-correcting code (ECC) to detect and correct the mistake possibly into data, its middle controller produces corresponding ECC, this corresponding ECC transmits together with data and writes in NAND core, then reads back together with data.Then ECC Engine 413 has these data and the access of corresponding ECC thereof, if desired, allow data be examined before being passed on main frame and correct.

Although ECC may be used for correction data mistake, but it only can correct limited amount mistake, and wherein this amount is design alternative.In these abilities, ECC Engine 413 can be just any mistake of accumulation during round trip, including error of transmission and mistake itself that be associated with NAND core 435, such as write error, read error and interference and the unknown losses of the data when storage；But, the selection of ECC is generally based only upon the consideration to the mistake relevant with NAND core 435.In some are arranged, in the such as layout with " strong ECC " disclosed in some of the list of references listed above for ECC, code is characteristic based on memorizer and how data mode is mapped in memorizer.Transmission between controller and memorizer is the most out in the cold and is not deemed to add mistake.Thus, interface needs to arrange accordingly, causes arranging parameter according to worst condition or close to worst condition, as mentioned above.

First embodiment collection is that element based on Figure 11 is to provide the feedback for optimized interface characteristic.Data set is sent to memorizer from controller in round trip together with corresponding ECC and returns to controller, writes followed by reading like above-described standard, except data (with corresponding ECC) are actually not written in memory core.When write transmission is just issued to memory circuitry 200 from controller 100, controller can use buffer latch 433 and 443 to these data of reading back.If this is represented by path 437, although input and output buffer system, then will not have the transmission of reality.Owing to this round trip removes the mistake that the array own with 435 is associated, so this has isolated the impact of transmission and has allowed ECC Engine 413 to determine the integrity of memory interface.Then can revise interface parameters and process can be re-emitted.Read as such, it is possible to optimize and write interface parameters.

Figure 12 is the block diagram illustrating another embodiment collection, but wherein feedback mechanism uses Hash engine and optional Data correction engine specific for interface.Do not relate to controller and memory chip, Figure 12 is given in terms of circuit in sender side 520 and receiver-side 530, because as described further below, depend on reading process or write process and both sides the need of symmetry, these any one can be controller and another be memorizer.

Sender side 520 will include write data buffer 521 and transmission interface circuit 529 again.Also will include hash value generator 525 and multiplexer 527.In transmission processes, data (523) to be write are sent to both hash value generators 525 and MUX527 from write buffer 520.Hash value generator 525 correspondingly produces cryptographic Hash from these data, and this cryptographic Hash is then passed to MUX527.Then the data which is followed by its cryptographic Hash are supplied to transmission interface circuit 529 by this multiplexer, are then increased in bus structures 550.

Receiver-side includes that receiver interface circuit and method for receiving correct framing and read data 535 are plus some other elements again.Reading interface circuit 532 after bus 550 obtains data and corresponding cryptographic Hash, de-multiplexing circuitry 533 is by cryptographic Hash and data separating, the data read are sent to buffer 535, and and also be sent to receiver-side hash value generator 539, this receiver-side hash value generator 539 from this data set produce cryptographic Hash.Then in comparison circuit 541, the cryptographic Hash that receiver-side produces is compared with the cryptographic Hash of reception.Depending on embodiment, result of the comparison can only determine whether these values mate or further determine that owing to transmission processes the amount of error caused.Data correction engine 537 may also be included in that in some embodiments with correct interface error and without carrying out data re-transmission.In the exemplary embodiment, hash generator (with the optional Data correction engine at receiver-side) separates with the ECC of the NAND core mistake for using, although it is overlapping to there are some in circuit；Further, it is true that both can be implemented on the identity logic circuit of controller, but realized by different firmware codes.Although (this is discussed and is considered to separate, but be discussed further below in more common embodiment this part of two error detection/cry can also be mutual.) generally, by entirety based on the information sent (user data, corresponding ECC, header information, etc.) and produce cryptographic Hash, but in an alternate embodiment, by such as removing various expense and can only use the user data for producing cryptographic Hash itself to produce cryptographic Hash from a part now.

Figure 12 also includes the feedback processing unit 560 connecting the output to receive Hash comparison circuit 541.Then analyzing this feedback 561, depend on embodiment, it is one or more that this can consider in the character that temperature, supply voltage level and the pretreatment of NAND core are relevant.563, then the result of this feedback may be used for adjusting transmission process and being accordingly connected to one or both of transmission interface circuit 529 and read interface circuit 531.For write operation (its middle controller is sender side), after sending to storage component part from controller and writing transmission, feedback processing unit relatively and being determined by this of cryptographic Hash produced that can only read back writes direction memory interface integrity.Based on this, interface write parameters can be revised and as wished to re-emit process.Symmetrically, can be that sender side is read direction and used identical operation to wherein memorizer.

Figure 13 is the figure illustrating the example for the cryptographic Hash by EBI transmission data and generation.As shown in top, corresponding cryptographic Hash invests data automatically, in order to when device is operated in this pattern, they will transmit together.In the second option shown in bottom, transmit data payload, receive side and ask corresponding cryptographic Hash, then produce and transmit this cryptographic Hash.This data payload can be predetermined length or random-length.If data payload length is predetermined, then as in the first option, cryptographic Hash can be attached to these data, or, this cryptographic Hash can send through request.If data payload length is random, then can send this cryptographic Hash after sending specific instructions.

Multiple changes are for being possible about the technology described in Figure 12 and corresponding circuit.About cryptographic Hash engine and cryptographic Hash, Hash engine can be parity check code (cyclic redundancy check or CRC), ECC, etc..It is, for example possible to use by passing back through/" binary system " embodiment of failure, it can set up and have the benefit that the low door for realizing counts based on error bit count (CRC).Or, " soft " embodiment can return error bit count (EBC), and can return to the position of fail bits with selection of land, and its can ECC code based on such as BCH or Reed Solomon code and set up, it is provided that more information is carried out help system and is determined accurately.Hash engine the most also has the complementary features of such as correction interface fault, is similar to correct the flip bit from memory core, as represented by the Data correction engine 537 of Figure 12.Based on from the feedback transmitted, system can repeatedly transmit.State can be transmitted based on binary system or retry based on soft transmission Determines transmission.Furthermore, it is possible to combination based on the quantity that transmission state and NAND are upset determines that transmission retries；Such as, if interface introduces N number of mistake and NAND introduces M mistake and controller error calibration capability is P, and P > N+M, then system may decide that and the most again transmits.

This system can also be configured by various alternate manners.Configuration can be symmetrical, wherein identical or symmetrical with the Hash engine of memory side at controller.In balanced configuration, different configurations is used for different transmission directions；For example, it is possible to relate to the most machine-processed for reading transmission, and design more reliable mechanism and be used for writing transmission.Even if furthermore, it should be noted that interface configures symmetrically, because arrange may change, so it may operate asymmetrically about given data set in the interim being originally written between reading subsequently of data.

Feedback processing unit 530 can be differently positioned on controller 100, is positioned on memorizer 200, on both or is distributed between the two.It is additionally formed on the circuit of separation.In numerous applications, realizing feedback processing unit on the controller will be most realistic, because controller circuitry generally includes the disposal ability of higher level and also because accumulator system is often formed by multiple memory chips, but technology given herein is not limited to so.In these any one changed, it is the responsibility of feedback processing unit for the inspection in data transfer state stage.

Consider that wherein feedback processing unit is positioned at the example of controller side further: reading direction, after aloft it reads data and cryptographic Hash, they will transmit through feedback mechanism, and controller by determine pass through/equipment state and can adjust accordingly (or not adjusting) interface arrange.Because controller have read data and cryptographic Hash, thus not for from the information of quick flashing side to determine needing further exist for of state because this can complete in the logic of controller.Writing direction, data payload and corresponding cryptographic Hash are sent to memory side, and then controller can operate in several different ways: read from memory side and pass through/status of fail；Cryptographic Hash of reading back determining passes through/failure；Read back error bit count (EBC) from memorizer；Read back EBC and errors present from NAND；Or read from memory side and pass through/the quantity of the position of status of fail and correction.

Feedback processing unit may decide that amendment interface is arranged.For example, it is possible to amendment is arranged with lower interface: drive intensity；Bus frequency or other timing parameters；Interface voltage；Interface modes (is such as switched to triggering pattern from normal/traditional mode)；Etc..Then can revise these interfaces by adaptive feedback mode to arrange.Because the factor of such as processing variation, supply voltage level and temperature affects the probability of interface error, these factors can also be included as the input to the feedback analysis 561 on Figure 12.

Bus frequency and other parameters are arranged can be based on alleviation (remission) not long ago, and calibrating parameters arranges and also can variously arrange.It is, for example possible to use have the look-up table (LUT) of the different value for different bus capacitys/NAND configuration.Such look-up table (LUT) can also have for different operation processing parameters, the different value of voltage supply level, temperature etc..Replacing in LUT predetermined, processing parameter, voltage supply level and temperature can also be variable by function (formula).

Optimization task can be set at consistency operation interface.The specific event that such as voltage supply or temperature change can be used for triggering interface and arranges training mission.Interface training mission can also use and stride across the transmission of NAND core and be not written to the known pattern of NAND core, such as above with respect to described in Figure 11 and path 437.Interface is arranged can also be different, and based on reading direction and can write direction, or keep requirement based on different data.

Described above mainly accumulator system is thought of as having controller and single memory device circuitry.More generally useful, this system can include using various bus topology to be connected to several memory chips of controller (if with feedback processing unit-it is the circuit separated).Such as, all memory chips can share individual system bus；Or each memory circuitry can have the controller-memory bus of their own；Or various mixed-arrangement can be used.The most different interface arrange can apply to these multiple NAND device (such as, if with several device interfaces, then this can complete concurrently).Based on being accessed for concrete NAND device, it is possible to use different interfaces is arranged, because interface properties can be load and/or the function of unit/block character of concrete NANF device).Additionally, in given storage component part, different interfaces arranges the block can also being applied in NAND core, because interface properties can be the function of the character of concrete block.

More details about the technology of above section can find in the U.S. Patent Application No. 12/835,292 that on July 13rd, 2010 submits to.

The dynamic optimization of background memory system interface

This part will be further considered controller-memorizer (or " backstage ") interface of accumulator system and be given for dynamically optimize be suitable for high speed memory systems, the backstage that includes having those systems of multiple memory data bus is read and the certain methods of write performance.As discussed above, accumulator system is typically designed with the error margins of certain amount；Although and this mistake possibly be present on controller-memorizer transmission process and physical storage storage and processes in both, but traditionally ECC is processed to the rear one only considering in both, and back office interface is generally optimised for eliminating or minimizing transmission channel mistake the most as far as possible.But, in many cases, processing the error in data (including reading and write error) obtained from storage may be well below the ECC ability of system.Such as, although the device being circulated throughout in a large number may need data available correction completely, but new device is likely to be of the most little mistake, leaves the error correction capability of surplus for system.This part is given by the method that the non-zero of this error correction capability is internally distributed to transmission channel by its accumulator system.This allows interface to operate with such as fair speed or lower-wattage, even if this will likely result in transmitting path error.When memory portion needs the error correction of higher amount, distribution can be dynamically adjusted.In supplementary aspect, this system can calibrate transmission path to determine the error of transmission amount obtained for different operating parameters, be then based on how much being allowed to and Selection parameter.

Considering the back office interface between controller and memory portion further, common accumulator system is made up of the storage component part of Memory Controller and such as NAND quick-flash memory module.Back office interface is the data/address bus between memorizer and controller thereof.This interface is generally set up in one of two modes.In first method, if controller and storage component part are discrete assemblies, then passing through to carry out connecting up (trace) on a printed circuit board (pcb) and set up back office interface, wherein these assemblies are arranged on this printed circuit board (PCB).In second method, controller and memorizer can be encapsulated in individual packaging, the system (SIP) such as packed or multi-chip packaging (MCP).In this second case, back office interface is set up by packaging substrate.

As discussed in previously part, the overall bit error rate (BER) in accumulator system can be by two principal element contributions: the reliability that the data in the storage component part of such as NAND quick-flash memory keep；And the defect of back office interface, this may cause error of transmission.Then error correction coding (ECC) can be used in accumulator system to tackle this overall BER.Figure 14 schematic illustration has contributor for the bit-errors in accumulator system.

As shown in figure 14, one of main source of overall bit error rate BER605.This mistake of causing due to the data degradation of the data of (from charge leakage, interference etc.) storage and be shown in NAND and keep 601 reading and write the impact of any mistake introduced in process.Traditionally, Data correction is used only to solve this factor, when data are read out observing this factor.The mistake caused due to channel imperfections is shown in 603, and these erroneous effects data are read and write both, but will again observe impact when reading.The source of channel effect mistake can include intersymbol interference (ISI), same data bus (in bus) crosstalk, total line-to-line crosstalk (in the bus design of many data), printed circuit board (PCB) (PCB) noise, silicon wafer noise, packaging noise etc..At opposite side, ECC607 can correct mistake and reach the mistake of certain level.

Along with the data transmission rate between controller and memorizer increases, back office interface becomes more prone to by the 603 contributive problems relevant with signal integrity, the crosstalk (crosstalk in memory data bus) between the signal in such as same data bus and intersymbol interference (ISI).It addition, the introducing of its middle controller memorizer topology (design of multi-memory data/address bus) that can simultaneously access multiple storage component part make back office interface experience between data/address bus while switching noise and crosstalk (crosstalk between memory data bus).In addition to bus speed, the factor of the voltage magnitude of such as data/address bus and temperature (environment temperature of PCB circuit and the system (SIP) of bag turn or the junction temperature of multi-chip packaging (MCP)) is likely to affect the signal integrity of back office interface.Therefore, the inherent shortcoming of back office interface becomes determining the bottleneck of the overall system performance of high speed memory systems.The pin electric capacity of storage component part increases along with the quantity of memory chips.The high capacity memory device constituted with multiple memory chips presents high capacitance in its data input/output (I/O), middle will damage peripheral speed and the signal integrity of data bus structure further.

The problem relevant with signal integrity that the interval can being separated each other by increasing signal line minimizes on signal line is to minimize crosstalk；But the method is limited by the usable area on PCB or substrate.This can also have the PCB material of low-k and low dissipation factor (loss angle tangent) by selection and reduce.Therefore despite the presence of being used in the way of the output reducing bus speed or infringement operator trunk parameter reduces this mistake, but these modes all subject shortcoming.

This part provides these problems of Signal Integrity for tackling in back office interface and also solves the dynamic optimization technique of processing variation between controller and storage component part.In addition to processing variation, the voltage that accumulator system operates under it is arranged and temperature is likely to change.Static scheme does not solve the change in process, voltage and temperature, it is thus possible to be not the best approach.

This part uses pseudo-echoplex mode dynamically to optimize the backstage performance of accumulator system, including the backstage performance of the accumulator system with multiple memory data bus.This can be by using predetermined Data Styles by completing in classification mechanism similar described in part before.Example embodiment will use pseudo-random bit pattern (PRBS).Dynamic optimization data/address bus arranges the reliability that can help to maximize the data transmission between controller and storage component part.This can allow accumulator system to distinguish error of transmission and the mistake caused on storage component part.These aspects are particularly advantageous for being equipped with the product of high-speed background memory interface and multiple memory data bus.

Connecting up (trace) on PCB or packaging substrate and have limited bandwidth, this causes intersymbol interference (ISI).The impact of ISI depends on peripheral speed (rise time and fall time), data rate and Data Styles.In digital communication, pseudo-random bit pattern (PRBS) pattern is occasionally used for developing the worst condition ISI impact of data link, because such pattern is abundant in terms of frequency component.PRBS pattern is to have the attribute similar with random sequence and for measuring shake and the repeat pattern of eye pattern mask (eye mask) of the data of the transmission during electrical data links.PRBS is typically expressed as 2X-1PRBS or PRBS-X, and wherein power (X) represents the shift register lengths for creating this pattern.It is desirable for the longest PRBS pattern of practicality, because it is applied with the pressure of maximum and provides the more preferable expression of random data signal link.

Although example embodiment uses pseudo-random bit pattern, but other patterns can be used, as long as system knows that be used to can the pattern of data set compared with the data returned at the ending that loopback processes.Example embodiment uses PRBS pattern, because it is similar to random character can maximize the ISI impact of signal link.In addition to PRBS pattern, other type of Data Styles can be utilized in the present invention, and each respective pattern can produce different results.

PRBS pattern can apply to each signal link in parallel back office interface.It is desirable that although pattern will ad infinitum repeat, this is the most infeasible in accumulator system, but if by using short pattern that this pattern is repeated enough number of times, this should not be major defect.Such as, if the page size of NAND quick-flash memory is 16kB, the PRBS-7 pattern of the pattern length with 127b can connect in each signal chains of 8 bit data bus and intactly repeat 129 times.Remaining bit (16384b-127bx129=1b) constitutes the incomplete copy of PRBS-7.This incomplete PRBS pattern in the end should be unable to cause serious problems, because great majority transmission connects impact and solved by 129 circulations of complete PRBS pattern.

Figure 15 may be used for the operation of the returning method being illustrated in back office interface.In fig .15, left side is flow process, and schematic illustration corresponding controller-memorizer in right side is mutual.701, controller cuts out its data scrambling and error correction coding (ECC) ability, and wherein on right side, this is illustrated by by these key elements beating X.Thus, that send out from controller and be transferred to all data of controller and there is no any scrambling or correction all in its unprocessed form.703, controller sends order to storage component part, informs that the data that storage component part will receive are stored and maintained in not transferring them to memory cell in its data latch detector.It is, this data set is not programmed in memory cell.705, the known Data Styles (being independent PRBS-7 pattern at this) in each data link in data bus structure is sent to storage component part by controller.These data are maintained in this data latch register until it becomes full by storage component part.

707, controller sends order to storage component part, informs that the data that storage component part will be stored in its data latch register send back continuously, until controller indicates it to stop.It is, after data latch register has been blanked the data of each all of 16kb chained, it sends back identical data again by starting.Therefore, PRBS-7 pattern connects repetition in each signal chains of data/address bus.The reason of continuous operation that example embodiment uses PRBS pattern to transmit be the bit-errors introduced by signal link be probability event.The data volume striding across link transmission is the biggest, and the transmission bit error rate (BER) as the statistical measurement of intrinsic switching performance is the most accurate and the most representative.709, controller receives the PRBS-7 pattern (or other Data Styles used) of the repetition connected in each signal chains of data/address bus.

711, control the controller data by reception compared with the Data Styles of transmission (being the PRBS-7 pattern of standard at this) and by any error reporting for transmitting BER.Then controller sends order to stop sending PRBS-7 pattern (713) and exiting pseudo-loop back mode (715) to storage component part.

Figure 16 is corresponding to the block 705 of Figure 15, and its middle controller sends Data Styles to storage component part, and Figure 17 corresponds to block 709.On this two width figure, it is shown that an object lesson of bus structures 811, wherein show on top that several lines, for order and control signal, and have been shown below a plurality of data lines.Again, CLE=order is latched and is enabled, and ALE=address latch enables, and RE=reads to enable, and WE=writes enable, DQS=data strobe, and there are eight input/output lines (IO0-IO7).In order to this purpose discussed simplifies these block diagrams, Memory Controller illustrate only ECC Block 805 and PRBS generator 803, only representing data register REG833 on storage component part 831, other elements (including the nonvolatile memory array on 831) are not explicitly depicted.When the controller 801 storage component part 831 in Figure 16 sends Data Styles, write enable signal and be selected with being assigned and often signal line will carry Data Styles.Again, every IO line carries independent pattern.Again, these are each copys all of PRBS, but can have different timings, as shown in its skew relatively in figure.On memorizer 831, then Data Styles is stored in depositor 833 when receiving, and in fig. 17, data stride across data structure 811 from depositor 833 and are sent back to controller 801, in order to read to enable signal and data strobe is assigned.Once Data Styles is complete round (and being not written in nonvolatile memory) and returns on controller 801, it is possible to check and check to there occurs how many errors for its primitive form to it.Although bus structures 811 are to have the parallel bus interface of many signal line, but this is only object lesson, and other bus structures may be used for transmission channel, and such as serial data is arranged.

The performance of accumulator system is carried out characterization by data transmission rate (bus operation frequency) relative to power consumption, and power consumption is the most relevant with data bus voltage.By voltage magnitude (being determined by the I/O of the device of driving data bus) and the data transmission rate of delta data bus, the 3-dimensional as simulation drawing (shmoo plot) can be created represent, transfer rate is drawn along x-axis, and data bus voltage is drawn along y-axis, and transmits BER and draw along z-axis.Again, data transmission rate can refer to the data transmission rate applied during write operation when data are sent to memory circuitry from controller circuitry, as in the 705 of Figure 15, or refer to the data transmission rate applied during read operation when data are sent to controller from memorizer, as in 709.Can measure, when each output driving impedance (driving intensity) and temperature, the data represented in such simulation drawing and cover worst condition, usual situation and best circumstance.Therefore, for the allowed error of transmission of specified rate, optimal point of operation may determine that at the given combination of the parameter of such as data bus voltage, output driving impedance, switching rate, line capacitance, transfer rate, temperature and power consumption.The example of simulation drawing illustrates in figure 18.

Figure 18 is the example of the simulation drawing of transmission BER relative data bus voltage and message transmission rate when fixing output driving impedance, switching rate, line capacitance and temperature illustrating the object lesson for accumulator system.Data bus voltage is the V on vertical axis_DD, and transfer rate is on the horizontal axis.The amount of transmission BER is represented by the color on figure, and comparison (key) is on the right side of figure.In this black and white represents, the expression of the lowest and the highest amount of error appears the same as, but the relatively low zone errors in master map are towards the left side of light color zoning, and higher zone errors are towards right side.Based on these type of data, for the transmitted data amount allowed, can be with the combination of selection manipulation parameter, wherein as generally, this will be usually directed to trade off.For example, if it is desired to the allowed BER of amount is 10^-5If maximal rate is main consideration, then V_DDAbout 3.1-3.2V will be taken as, it is allowed to the transfer rate of about 170-180Mb/s.If power consumption is prior consideration, then can use lower V_DDValue, such as 2.8V, then the transfer rate of about 150Mb/s will be allowed for identical transmission BER.If based on such as memorizer circulated how many or simply to the contribution of the combination of BER just close to the maximum capacity of system, the BER distributing to transmit signal has been reallocated different values, then may then based on this data from controller and adjust the operating parameter of bus system.

Thus, after calibrating system by catching the data in each output driving impedance, switching rate, line capacitance, temperature etc. represented in simulation drawing, accumulator system can operate according to various situations.Such as, provide desired transmission BER, then optimum data bus voltage, message transmission rate, output driving impedance and switching rate are searched and selected to accumulator system.(these data from calibration process may remain in the storage space (RAM) in nonvolatile memory or in controller circuitry.) such as, it can select to obtain the minimum data bus voltage of desired transmission BER, the highest data transmission rate and the output driving impedance arrived most.In another example, providing the concrete combination of data bus voltage, message transmission rate, output driving impedance, switching rate, line capacitance and temperature, accumulator system is until acting to it is expected to which type of BER.Or, accumulator system can select to balance all factor data bus voltages, message transmission rate, output driving intensity and the operating condition of transmission BER.

Because controller may be different with the design of the I/O buffer in storage component part, so optimal reading of accumulator system can determine respectively with write performance.In addition to the difference obtained due to different accumulator system designs, due to technique change and the difference of operating condition, also will there is difference in each example for identity unit.In order to solve change of device aging, operating condition etc., it is also possible to recalibration processes.For example, it is possible to initially calibrated before device dispatches from the factory when test, then controller periodically or can recalibrate system in response to such as period circulation, error result, the obvious change etc. of operating condition.Therefore, in addition to distributing to the change of the ratio of total mistake of transmission signal, the corresponding operating parameter for given distribution can dynamically change.

As set forth above, it is possible to optimize performance during reading and writing process.Returning to Figure 15, the performance optimization during reading for memorizer, 705, system fills it up with the transfer rate of the Data Styles in the data latch register being just written to storage component part to maximize the integrity of the transmission of this Data Styles.Such as, with the transfer rate of 10MHz, will take for 1.6ms to fill up the data latch register of 16kb.709 and 711, the transmission BER that systematic survey causes during read operation, wherein the I/O of storage component part is driver, and controller is receptor.Then simulation drawing data illustrate the relation between the I/O voltage of storage component part and reading frequency.

For writing the performance optimization of period at memorizer, 705, this system change voltage and the transfer rate of the Data Styles in being just written to the data latch register of storage component part.709, system then by the transfer rate of the data slowed down from storage component part to controller in case stop-pass crosses signal link injects other bit-errors.Then the transmission BER measured is the transmission BER caused during the write operation in 705.Thus the simulation drawing data river I/O voltage that represents controller and the relation of writing between frequency.

Up to the present, the most wherein this be only single bus between controller circuitry and single memory circuit context in give various aspects given herein.But, accumulator system can include multiple devices with multiple data topology, and when there is multiple bus, may cause other error source alternately between these buses.Technology in this can provide and each signal in the data/address bus in back office interface links the ability being displaced to given resolution, such as 100ps.Such excursion capability can be introduced by the controller in driver or receptor or memorizer.Introducing skew in data/address bus allows the length of the holding wire in system balance PCB or packaging substrate not mate.Introduce skew and can reduce the impact of the proximally and distally crosstalk in back office interface, thus reduce transmission BER.Relate to two kinds of crosstalk: crosstalk in memory data bus；And crosstalk between memory data bus.Such crosstalk causes the shake in data/address bus.Common accumulator system uses the clock that sent by driver to be engraved in parallel data bus line, when identical, each single signal of sampling.Therefore, the increase increased causing transmitting BER of the shake on each signal in data/address bus.Stride across the data of a plurality of memory data bus so that their misalignment relative to each other by skew, crosstalk between memory data bus can be reduced.

Figure 19 is the block diagram of this crosstalk in the accumulator system having illustrated the bus structures a plurality of memory data bus of use.This accumulator system include controller 901 and by respective bus 911-1,911-2,911-3,911-4 be connected to controller multiple, be four storage component parts 931-1,931-2,932-3,931-4 at this.For every bus 911, they will have as being shown specifically the one or more IO line for IO1 to IOX.Entering trade-before, these each bar buses can be parallel, serials or operate the IO line of the various quantity for transmitting data by these combinations.This kind of multibus is arranged and is often implemented in SSD types of devices (for example, see United States Patent (USP) 7, 376, 034, United States Patent (USP) 7, 763, 339 or paper " A High Performance Controller for NAND Flash-based Solid Sate Disk (NSSD) " Park et al., Samsung, nonvolatile semiconductor seminar, 2006, IEEE, NVSMW2000, 21st, vol.no., 17-20 page, 12-16 day in February, 2006) to improve performance, but also in some storage cards and other accumulator system, find that this kind of multibus is arranged.In addition to crosstalk in this kind of memory data bus between the IO line of given bus, in different wordline, also will there is now crosstalk signal between memory data bus.When the use with above-mentioned PRBS pattern and pseudo-loop back mode is combined, provide certain combination of data bus voltage, transfer rate, temperature, output driving impedance, switching rate, line capacitance and power consumption, it may be determined that produce minimum crosstalk and thus produce the optimized migration of minimum transmission BER.

Various aspects given herein provide and there is the least cost solution optimizing back office interface performance under various problems of Signal Integrity.By " untapped " ECC ability is dynamically assigned to transmission process, performance can be improved as described.As it has been described above, some accumulator systems use a type of " by force " ECC of the attribute of exploitation multistate memory device, in the case, it is sent for using the error correction capability of transmission channel to transmit in a 1-to-1 manner.It is further noted that, although accumulator system is incorporated to ECC carrys out offset data mistake, but for ordering the most identical outfit, and storage component part generally will not accept vicious order, although so that mistake may be allowed the most wittingly, this situation also be there will be no for order.Thus, although providing these mechanism may allow the higher transfer rate for data, but slower, the safer setting for transfer rate (or other parameter) can be incorporated to not cause mistake for control signal.

Conclusion

In order to purpose of illustration and description has been given by the discussed in detail above of the present invention.It is not intended to limit or limits the invention to disclosed precise forms.According to teachings above, many modifications and variations are possible.Choose described embodiment the principle of the present invention and actual application thereof to be most preferably described, so that those skilled in the art in various embodiments and can most preferably utilize the present invention by being suitable for desired specifically used various amendments.It is intended to the scope of the present invention limited by the claim investing this.

Claims (29)

1. the method operating Nonvolatile memory system, this Nonvolatile memory system includes: Controller circuitry, has memory interface；Memory circuitry, has the battle array of Nonvolatile memery unit Row and control unit interface；And bus structures, be connected to described controller circuitry memory interface and The control unit interface of described memory circuitry, for described controller circuitry and described memory circuitry it Between transmit data and order, wherein said accumulator system can be tolerated and transmits to write from controller from data To memory array until data are read back at controller from memory array subsequently and to be received as Only the first amount of error of the non-zero of accumulation, the method includes:

By described controller circuitry between described controller circuitry and described memory circuitry via bus The sub data transmission of structure joins the Part I of the non-zero of the first amount of error, the residue of described first amount of error Part be assigned on described memory circuitry data write, store and read；And

Transmission between described controller circuitry and described memory circuitry is set by described controller circuitry special Property is to operate the mistake allowing up to described Part I.

2. method as claimed in claim 1, wherein said transmission characteristic includes described bus-structured voltage amplitude Value.

3. method as claimed in claim 1, wherein said transmission characteristic includes the data in described bus structures Transfer rate.

4. method as claimed in claim 1, wherein said transmission characteristic includes that signal drives intensity.

5. method as claimed in claim 1, wherein said transmission characteristic includes signal switching rate.

6. method as claimed in claim 1, wherein said accumulator system includes error code and correction (ECC) Circuit, and described first amount of error is ability based on ECC circuit.

7. method as claimed in claim 6, wherein ECC circuit is on described controller circuitry.

8. method as claimed in claim 6, the method also includes:

The described data from main frame are received at described controller circuitry；

Produce the corresponding ECC code for these data；

According to described transmission characteristic in described bus structures by these data and corresponding ECC code from described control Device circuit transmission processed is to described memory circuitry；And

Deposit described in subsequently the described data received at described memory circuitry and corresponding ECC code being write In the array of storage unit.

9. method as claimed in claim 1, also includes:

Subsequently by described controller circuitry between described controller circuitry and described memory circuitry via The Part II of described first amount of error is redistributed in the transmission of described bus-structured data；And

Transmission between described controller circuitry and described memory circuitry is set by described controller circuitry special Property is to operate the mistake allowing up to described Part II.

10. method as claimed in claim 9, the programming-erasing wherein experienced in response to described memory circuitry The quantity of circulation, the Part I of described first amount of error is redistributed as described by described controller circuitry The Part II of the first amount of error.

11. methods as claimed in claim 9, wherein in response at the number read back from described memory array The amount of error detected according to, the Part I of described first amount of error is divided by described controller circuitry again Join the Part II for described first amount of error.

12. methods as claimed in claim 1, wherein said accumulator system maintains to be tied for described bus The value of one or more operating parameters of structure and between described controller circuitry and described memory circuitry Via the correspondence between the amount of error obtained of described bus-structured data transmission, it is provided with described Transmission characteristic includes:

It is the one or more operating parameter selective value by described controller circuitry based on described correspondence.

The method of 13. such as claim 12, wherein said correspondence is used for multiple operating parameters, and selects Select the value for the plurality of operating parameter to include allowing up to according to one or more pre-determined characteristics standards Choose between multiple combinations of the plurality of parameter of the mistake of described Part I.

The method of 14. such as claim 13, wherein said operating parameter includes described bus-structured voltage Message transmission rate in amplitude and described bus structures.

The method of 15. such as claim 13, wherein said operating parameter includes that signal drives intensity.

The method of 16. such as claim 13, wherein said operating parameter includes signal switching rate.

The method of 17. such as claim 12, also includes:

Selecting before the described value of the one or more operating parameter, by described controller circuitry Set up described correspondence.

The method of 18. such as claim 17, wherein sets up correspondence and includes:

For described value each of operating parameter, by described bus structures from described controller circuitry to Described memory circuitry transmits the data of known pattern and is transmitted back to and does not write that data to non-volatile depositing In the array of storage unit, and the number of data and the transmission returned will be received at described controller circuitry Compare according to pattern.

The method of 19. such as claim 17, wherein said accumulator system includes multiple memory circuitry, And described bus structures include that corresponding multiple bus, the most each memory circuitry are connected respectively to control Device circuit, and wherein set up correspondence by described controller circuitry and include determining total line-to-line crosstalk mistake.

20. 1 kinds of methods operating Nonvolatile memory system, this Nonvolatile memory system has Controller circuitry and memory circuitry, this memory circuitry includes the array of Nonvolatile memery unit, The method includes:

By described controller circuitry by the bus structures connecting described controller and described memory circuitry Each multiple values each of one or more operating parameters be processed to be transmitted mistake school Standard, this process includes:

By the data set of given data pattern from described controller through described controller transmission electricity Road is transferred to described bus structures；

Received from described bus-structured data by the reception circuit on described memory circuitry Collection；

The data set of reception is stored in the buffer storage on described memory circuitry；

Will be stored in the data set in the described buffer storage on described memory circuitry by described Transmission circuit on memory circuitry is transferred to described bus structures and is not written to described array In；

Received from described bus-structured data set by the reception circuit on described controller；

Carry out received data collection to compare with the data set of known pattern；And

Compare based on this, the one or more parameter determinations used are associated with transmission process Amount of error；And

Operate described accumulator system subsequently to allow between described controller circuitry and memory circuitry The first amount of error of non-zero in the transmission of described data, wherein said controller circuitry based on determined by phase Associated errors amount selects the value of described operating parameter according to error of transmission calibration process.

The method of 21. such as claim 20, wherein said operating parameter includes bus-structured voltage magnitude.

The method of 22. such as claim 20, wherein said operating parameter includes that the data in bus structures pass Defeated speed.

The method of 23. such as claim 20, wherein said operating parameter includes that signal drives intensity.

The method of 24. such as claim 20, wherein said operating parameter includes signal switching rate.

The method of 25. such as claim 20, also includes:

Operate subsequently described accumulator system with allow described controller circuitry and described memory circuitry it Between data transmission in the second amount of error, wherein said controller circuitry based on determined by be associated Amount of error carrys out the value of selection manipulation parameter according to error of transmission calibration process.

The method of 26. such as claim 20, also includes:

Re-start error of transmission calibration process subsequently.

The method of 27. such as claim 20, wherein be transmitted improper correction process after, described in deposit Its result is stored in the nonvolatile memory by reservoir system.

The method of 28. such as claim 20, wherein carries out described error of transmission school for multiple operating parameters Standard, and described controller circuitry allowing up to described according to one or more predetermined performance standards Choose between multiple combinations of multiple operating parameters of one amount of error.

The method of 29. such as claim 20, wherein said accumulator system includes multiple memory circuitry, And described bus structures include corresponding multiple bus, each point of the most the plurality of memory circuitry It is not connected to described controller circuitry, and wherein the data set of transmission given data pattern includes transmitting use In the data determining total line-to-line crosstalk mistake.