CN103092253A - Reference voltage generation circuit - Google Patents

Abstract

Provided is a reference voltage generation circuit. The reference voltage generation circuit comprises a current mirror unit, a first resistance, a second resistance and a temperature coefficient compensation unit. The temperature coefficient compensation unit comprises a first N-channel metal oxide semiconductor (NMOS) tube, a second NMOS tube and a third NMOS tube. A grid electrode and a drain electrode of the first NMOS tube are connected with each other, and are connected with a second end of the first resistance, and a source electrode of the first NMOS tube is connected with the ground. A grid electrode and a drain electrode of the second NMOS tube are connected with each other, and are connected with a first node of the current mirror unit, and a source electrode of the second NMOS tube is connected with the ground. A grid electrode and a drain electrode of the third NMOS tube are connected with each other, and are connected with a second end of the second resistance, and a source electrode of the third NMOS tube is connected with the ground. The first NMOS tube, the second NMOS tube and the third NMOS tube work in a subthreshold region or a saturation region. A first end of the first resistance is connected with a second node of the current mirror unit. A first end of the second resistance is connected with a third node of the current mirror unit. A work voltage range of the reference voltage generation circuit is wide, and energy consumption of the reference voltage generation circuit is low.

Description

Generating circuit from reference voltage

Technical field

The present invention relates to technical field of integrated circuits, particularly a kind of generating circuit from reference voltage.

Background technology

In recent years, occupy increasing share along with portable type electronic product on market, the demand of the reference voltage source of low-voltage, low-power consumption is increased greatly.Reference voltage plays vital effect in electronic circuit or electronic system, stable reference voltage generally has two specific characters, and the one, to the high stability of temperature; The 2nd, to the high resistibility of mains voltage variations.The energy gap reference voltage circuit is widely used on analog/digital converter, digital/analog converter and voltage rectifier isoelectronic series system with its high stability.

Fig. 1 shows existing a kind of generating circuit from reference voltage.With reference to figure 1, described generating circuit from reference voltage comprises: error amplifier OPA, PMOS pipe M11, PMOS pipe M12, PMOS pipe M13, the first triode Q11, the second triode Q12, the 3rd triode Q13, resistance R 11 and resistance R 12.The concrete connected mode of each device does not repeat them here as shown in Figure 1.

Continuation is with reference to figure 1, and the clamping action due to error amplifier OPA makes V _XWith V _YThe voltage of 2 is substantially equal, i.e. V _X=V _Y=V _BE2, V _BE2Be the base stage of described the second triode Q12 and the voltage difference between emitter; Simultaneously, the electric current in the circuit of both sides is also equal, namely $I_X=I_Y=\frac{V_{\mathrm{BE}2}-V_{\mathrm{BE}1}}{R_1}=\frac{V_T\ln N}{R_1}.---\left(a\right)$

In formula (a), R1 refers to the resistance of resistance R 11, V _BE1Be the base stage of the first triode Q11 and the voltage difference between emitter, due to

Electric current for being proportional to absolute temperature (Proporational To Absolute Temperature, PTAT) electric current, becomes the bias current of whole chip after the mirror image of this electric current through current mirror.

(a) can draw according to formula, reference voltage $\mathrm{Vref}=I_X{R}_2=\frac{R_2}{R_1}{V}_T\ln N+V_{\mathrm{BE}3}.---\left(b\right)$

In formula (b), R2 refers to the resistance of resistance R 12, V _BE3Be the base stage of the 3rd triode Q13 and the voltage difference between emitter, because VT is positive temperature coefficient (PTC), and V _BE3Be negative temperature coefficient, reasonably adjustment factor

Size, can realize at a certain temperature that just the reference voltage variation with temperature is zero, thereby provide one to vary with temperature very little reference voltage for whole chip.

But circuit shown in Figure 1 also is not suitable for the application of low-power consumption, and this is because when if the electric current of the error amplifier OPA that flows through only has 100 ~ 200nA, described error amplifier OPA can't normal operation.At first, described error amplifier OPA unsettled phenomenon of easy appearance under little current conditions; Secondly, namely allow to solve the stability of described error amplifier OPA when little electric current, the breadth length ratio of so described error amplifier OPA also will be very little, and this can affect the precision of circuit.In addition, the operating voltage range of circuit shown in Figure 1 is also smaller.

Fig. 2 shows existing another kind of generating circuit from reference voltage.With reference to figure 2, the difference part of this generating circuit from reference voltage and circuit shown in Figure 1 is: form current mirror with NMOS pipe N11 and NMOS pipe N12 and come the substitution error amplifier.Although generating circuit from reference voltage shown in Figure 2 has lower power consumption, the scope of its operating voltage still is restricted.

Particularly, when supply voltage VDD higher (being for example 6V), the voltage that B is ordered will be far away higher than ground wire GND(for example, may reach 5.5V).At this moment NMOS manages the drain electrode (drain) of N11 and the voltage difference V between substrate (bulk) _DBLarger, simultaneously, the drain electrode (D) of NMOS pipe N11 and the voltage difference V between source electrode (S) _DSAlso larger, thus make between the drain electrode of NMOS pipe N11 and substrate because hot carrier's effect (hot carrier effect) forms larger leakage current.The existence of this leakage current will affect the degree of accuracy of circuit.

By above analysis as can be known, the operating voltage range that how to enlarge generating circuit from reference voltage just becomes one of those skilled in the art's problem demanding prompt solution.More contents about reference circuits can be the Chinese patent application of CN102354245A with reference to publication number.

Summary of the invention

What technical solution of the present invention solved is the little problem of the operating voltage range of generating circuit from reference voltage in prior art.

For addressing the above problem, the invention provides a kind of generating circuit from reference voltage, comprising: current lens unit, the first resistance, the second resistance and tc compensation unit, wherein,

Described current lens unit comprises first node, Section Point and the 3rd node, the electric current at the electric current at described first node place, Section Point place and the electric current of the 3rd Nodes be proportional relation respectively, and described the 3rd node is as the output terminal of described generating circuit from reference voltage;

Described tc compensation unit comprises: a NMOS pipe, the 2nd NMOS pipe and the 3rd NMOS pipe, the grid of a described NMOS pipe and the second end that drains and be connected and be connected described the first resistance, source ground; The grid of described the 2nd NMOS pipe and the first node that drains and be connected and be connected described current lens unit, source ground; The grid of described the 3rd NMOS pipe and the second end that drains and be connected and be connected described the second resistance, source ground; A described NMOS pipe, the 2nd NMOS pipe and the 3rd NMOS pipe are operated in sub-threshold region or saturation region;

The first end of described the first resistance connects the Section Point of described current lens unit;

The first end of described the second resistance connects the 3rd node of described current lens unit.

Alternatively, described current lens unit comprises:

The first electron current mirror unit comprises a PMOS pipe, the 2nd PMOS pipe and the 3rd PMOS pipe, and the source electrode of a described PMOS pipe, the 2nd PMOS pipe and the 3rd PMOS pipe all is connected to supply voltage, and grid all is connected to the drain electrode of described the 3rd PMOS pipe; The drain electrode of a described PMOS pipe is as the 3rd node of described current lens unit;

The second electron current mirror unit comprises: the 4th NMOS pipe and the 5th NMOS pipe, and the grid of described the 4th NMOS pipe is connected with drain electrode, and is connected to the drain electrode of described the 2nd PMOS pipe; The source electrode of described the 4th NMOS pipe is as the first node of described current lens unit; The grid of described the 5th NMOS pipe connects the grid of described the 4th NMOS pipe, and drain electrode couples the drain electrode of described the 3rd PMOS pipe, and source electrode is as the Section Point of described current lens unit.

Alternatively, described current lens unit also comprises: a ZMOS pipe, the drain electrode of described the 5th NMOS pipe connect the drain electrode of described the 3rd PMOS pipe by a described ZMOS pipe.

Alternatively, the grid of a described ZMOS pipe connects the grid of described the 4th NMOS pipe, and source electrode connects the drain electrode of described the 5th NMOS pipe, and drain electrode connects the drain electrode of described the 3rd PMOS pipe.

Compared with prior art, the generating circuit from reference voltage of technical solution of the present invention has the following advantages at least:

Substitute triode in available circuit with the NMOS pipe in the generating circuit from reference voltage of technical solution of the present invention.When working in sub-threshold region or saturation region due to the NMOS pipe, the voltage difference between its grid and source electrode is very little, and is less than base stage and the voltage difference between emitter of triode in prior art.Therefore, compared with prior art, the generating circuit from reference voltage of technical solution of the present invention can be applicable to lower supply voltage, thereby has enlarged the scope of the operating voltage of this circuit.

In addition, in possibility, current lens unit also comprises a ZMOS pipe, and the drain electrode of the 5th NMOS pipe in described current lens unit connects the drain electrode of described the 3rd PMOS pipe by a described ZMOS pipe.By increasing a described ZMOS pipe, make the grid of described the 5th NMOS pipe and the voltage difference between drain electrode equal the grid of a described ZMOS pipe and the voltage difference between source electrode, again due to the grid of a described ZMOS pipe and the voltage difference between source electrode is very little and its grid voltage is lower, therefore, the drain voltage of described the 5th NMOS pipe is lower, thereby the drain electrode of described the 5th NMOS pipe and the voltage difference between substrate, with and drain electrode and source electrode between voltage difference all smaller.Like this, even when supply voltage is higher, can there be larger leakage current in described the 5th NMOS pipe yet, thereby makes this generating circuit from reference voltage go for again than under high power supply voltage, thereby has further enlarged the operating voltage range of circuit.

Further, owing to using current lens unit to substitute existing error amplifier in technical solution of the present invention, therefore also reduced the power consumption of this generating circuit from reference voltage.

Description of drawings

Fig. 1 is the circuit diagram of generating circuit from reference voltage one embodiment in prior art;

Fig. 2 is the circuit diagram of another embodiment of generating circuit from reference voltage in prior art;

Fig. 3 is the circuit diagram of the first embodiment of generating circuit from reference voltage of the present invention;

Fig. 4 is the circuit diagram of the second embodiment of generating circuit from reference voltage of the present invention;

Fig. 5 is the circuit diagram of the 3rd embodiment of generating circuit from reference voltage of the present invention;

Fig. 6 is the emulation schematic diagram of the NMOS pipe of tc compensation unit in generating circuit from reference voltage shown in Figure 5 when working in sub-threshold region;

Fig. 7 is the emulation schematic diagram of the NMOS pipe of tc compensation unit in generating circuit from reference voltage shown in Figure 5 when working in the saturation region.

Embodiment

For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.

Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can be in the situation that do similar popularization without prejudice to intension of the present invention.Therefore the present invention is not subjected to the restriction of following public embodiment.

Fig. 3 shows the circuit diagram of the first embodiment of generating circuit from reference voltage of the present invention.With reference to figure 3, described generating circuit from reference voltage comprises: current lens unit 100, the first resistance R 21, the second resistance R 22 and tc compensation unit 200, wherein,

Described current lens unit 100 comprises first node C, Section Point D and the 3rd node E, the electric current at the electric current at the electric current at described first node C place, Section Point D place and the 3rd node E place is proportional relation respectively, described the 3rd node E is as the output terminal of described generating circuit from reference voltage, output reference voltage Vref;

Described tc compensation unit 200 comprises: a NMOS pipe NM1, the 2nd NMOS pipe NM2 and the 3rd NMOS pipe NM3.Particularly, the grid and the second end that drains and be connected and be connected described the first resistance R 21, source ground GND of a described NMOS pipe NM1; The grid and the first node C that drains and be connected and be connected described current lens unit, source ground GND of described the 2nd NMOS pipe NM2; The grid and the second end that drains and be connected and be connected described the second resistance R 22, source ground GND of described the 3rd NMOS pipe NM3; A described NMOS pipe NM1, the 2nd NMOS pipe NM2 and the 3rd NMOS pipe NM3 are operated in sub-threshold region or saturation region;

The first end of described the first resistance R 21 connects the Section Point D of described current lens unit 100;

The first end of described the second resistance R 22 connects the 3rd node E of described current lens unit 100.

Need to prove, in actual applications, can be according to the actual requirements the proportionate relationship between the electric current at the electric current at the electric current at the first node C place of described current lens unit 100, Section Point D place, the 3rd node E place be suitably arranged, for example, can be 1:1:1 with the ratio setting between the electric current at the electric current at the electric current at first node C place, Section Point D place and the 3rd node E place.Certainly, only for illustrating, it should not limit protection scope of the present invention to this set.

Continuation is with reference to figure 3, and in the present embodiment, described current lens unit 100 comprises: the first electron current mirror unit 101 and the second electron current mirror unit 102.

Described the first electron current mirror unit 101 comprises a PMOS pipe MP1, the 2nd PMOS pipe MP2 and the 3rd PMOS pipe MP3, the source electrode of a described PMOS pipe MP1, the 2nd PMOS pipe MP2 and the 3rd PMOS pipe MP3 all is connected to supply voltage VDD, and grid all is connected to the drain electrode of described the 3rd PMOS pipe MP3; The drain electrode of a described PMOS pipe MP1 is as the 3rd node E of described current lens unit 100;

The second electron current mirror unit 102 comprises: the 4th NMOS pipe NM4 and the 5th NMOS pipe NM5, and the grid of described the 4th NMOS pipe NM4 is connected with drain electrode, and is connected to the drain electrode of described the 2nd PMOS pipe MP2; The source electrode of described the 4th NMOS pipe NM4 is as the first node C of described current lens unit 100; The grid of described the 5th NMOS pipe NM5 connects the grid of described the 4th NMOS pipe NM4, and drain electrode connects the drain electrode of described the 3rd PMOS pipe MP3, and source electrode is as the Section Point D of described current lens unit 100.

In the present embodiment, the breadth length ratio of the breadth length ratio of the breadth length ratio of a described PMOS pipe MP1, the 2nd PMOS pipe MP2 and the 3rd PMOS pipe MP3 equates.In addition, the breadth length ratio of the breadth length ratio of described the 4th NMOS pipe NM4 and the 5th NMOS pipe NM5 equates.Certainly, in other embodiments, can also do corresponding adjustment to the breadth length ratio of above-mentioned metal-oxide-semiconductor according to the actual requirements, it should not limit protection scope of the present invention.

The below is described in further details the principle of work of the generating circuit from reference voltage of the present embodiment more by reference to the accompanying drawings.

In the first situation, a NMOS pipe NM1, the 2nd NMOS pipe NM2 and the 3rd NMOS pipe NM3 in described tc compensation unit 200 all work in sub-threshold region (inversion regime namely).

Should be understood that, when the NMOS pipe is operated in sub-threshold region, its drain current I _DSatisfy following formula (1):

$I_D=\frac{W}{L}\mathrm{\μ}{V_T}^2{I}_{D0}{e}^{\left(\frac{V_{\mathrm{GS}}-V_{\mathrm{th}}-V_{\mathrm{off}}}{\mathrm{\ϵ}{V}_T}\right)}---\left(1\right)$

In formula (1), W/L is the breadth length ratio of this NMOS pipe; μ is the mobility of charge carrier in raceway groove; The constant that ε determines for the technological parameter by the NMOS pipe, ε=1.5 usually; I _D0Characteristic current for this NMOS pipe; V _offIt is a constant term; V _thThreshold voltage for the NMOS pipe; V _GSBe the grid of NMOS pipe and the voltage difference between source electrode.

Further, as the drain current I of NMOS pipe _DDuring for fixed value, the grid of NMOS pipe and the voltage difference V between source electrode _GSAnd the relation between temperature T satisfies formula (2):

$V_{\mathrm{GS}}\left(T\right)=V_{\mathrm{th}}\left(T\right)+V_{\mathrm{off}}+\frac{\mathrm{\ϵ}\left(T\right)}{\mathrm{\ϵ}\left(T0\right)}\×[V_{\mathrm{GS}}\left(T0\right)-V_{\mathrm{th}}\left(T0\right)-V_{\mathrm{off}}]\frac{T}{T0}---\left(2\right)$

In conjunction with following formula (3):

$V_{\mathrm{th}}\left(T\right)=V_{\mathrm{th}}\left(T0\right)+\mathrm{\α}{V}_T(T-T0)=V_{\mathrm{th}}\left(T0\right)+\mathrm{\α}{V}_{T}T0(\frac{T}{T0}-1)=V_{\mathrm{th}}\left(T0\right)+K_T(\frac{T}{T0}-1)---\left(3\right)$

Can draw the threshold voltage V of NMOS pipe _thBe negative temperature coefficient.Suppose that ε (T) does not change with temperature, can draw so: $V_{\mathrm{GS}}\left(T\right)\≈V_{\mathrm{GS}}\left(T0\right)+[K_T+V_{\mathrm{GS}}\left(T0\right)-V_{\mathrm{th}}\left(T0\right)-V_{\mathrm{off}}](\frac{T}{T0}-1).$ Can draw V by this formula _GSBe negative temperature coefficient, and V _GSThe V of triode in temperature variant characteristic and prior art _BE(voltage difference between base stage and emitter) similar.Therefore in the present embodiment, the NMOS pipe that works in sub-threshold region substitutes triode of the prior art.

Similar with prior art, the electric current of first resistance R 21 of flowing through

V _GS1Be the grid of a NMOS pipe NM1 and the voltage difference between source electrode; V _GS2Be the grid of the 2nd NMOS pipe NM2 and the voltage difference between source electrode; Wherein, r1 is the resistance value of described the first resistance R 21, and V _GS2With V _GS1Between voltage difference delta V _GSBe positive temperature coefficient (PTC).Therefore, electric current I ₁Be positive temperature coefficient (PTC).

Continuation connects the 3rd node E of described current lens unit 100 with reference to figure 3 due to the first end of the second resistance R 22, therefore, and the electric current I of second resistance R 22 of flowing through ₂With electric current I ₁Become certain proportionate relationship (being for example 1:1), therefore described electric current I ₂Also be positive temperature coefficient (PTC).And the Voltage Reference of the present embodiment produces the reference voltage V of circuit output _ref=I ₂* r2+V _GS3, V _GS3Be the grid of the 3rd NMOS pipe NM3 and the voltage difference between source electrode.Due to electric current I ₂Be positive temperature coefficient (PTC), and V _GS3Be negative temperature coefficient, therefore, can make by the parameters such as resistance of adjusting the first resistance R 21 and the second resistance R 22 temperature coefficient of reference voltage V ref is zero, thereby realizes the compensation of temperature coefficient, and the reference voltage V ref that makes output is variation with temperature and changing not.

In addition, should be understood that, when the NMOS pipe is operated in sub-threshold region, the voltage difference V between its grid (G) and source electrode (S) _GSVery little (usually greatly about 200mV ~ 300mV), than the base stage (B) of the triode that is operated in sub-threshold region and the voltage difference V between emitter (E) _BE(be generally 300mV ~ 800mV) little.Therefore, after substituting triode with the NMOS pipe, this generating circuit from reference voltage can work under lower supply voltage, thereby has enlarged the scope of this circuit voltage.

In addition, in the present embodiment, described generating circuit from reference voltage only comprises three branch roads, and described current lens unit 100 comprises the first electron current mirror unit 101 and the second electron current mirror unit 102.Described the second electron current mirror unit 102 comprises the 4th NMOS pipe NM4 and the 5th NMOS pipe NM5.This circuit simple in structure, device count is few, so the power consumption of this circuit is very little.

In the second situation, a NMOS pipe NM1, the 2nd NMOS pipe NM2 and the 3rd NMOS pipe NM3 in described tc compensation unit 200 all work in the saturation region.

When the NMOS pipe is operated in the saturation region, its drain current I _DSatisfy formula (4):

$I_D=\frac{1}{2}(W/L)\mathrm{\μCox}{(V_{\mathrm{GS}}-V_T)}^2---\left(4\right)$

Wherein, W/L is the breadth length ratio of NMOS pipe; μ is the mobility of charge carrier in raceway groove; Cox is the parasitic capacitance value of the oxide layer between raceway groove and grid in the NMOS pipe; V _GSBe the voltage difference between this NMOS tube grid and source electrode.After being changed, formula (4) draws:

$V_{\mathrm{GS}}=V_T+\sqrt{\frac{2I_D}{(W/L)\mathrm{\μCox}}}$

Should be understood that, can make by the parameter (for example W/L) of adjusting the NMOS pipe V of the NMOS that works in the saturation region _GSBe negative temperature coefficient; And make V _GS2(grid of the 2nd NMOS pipe NM2 and the voltage difference between source electrode) and V _GS1Voltage difference delta V between (grid of a NMOS pipe NM1 and the voltage difference between source electrode) _GSBe positive temperature coefficient (PTC).

By aforementioned analysis as can be known, as Δ V _GSDuring for positive temperature coefficient (PTC), the electric current I of first resistance R 21 of flowing through ₁Be positive temperature coefficient (PTC), the I of second resistance R 22 of flowing through ₂Also be positive temperature coefficient (PTC), and V _ref=I ₂* r2+V _GS3Therefore, in this case, the parameters such as resistance that also can be by adjusting the first resistance R 21 and the second resistance R 22 are so that the temperature coefficient of reference voltage V ref is zero.

When the NMOS pipe is operated in the saturation region, the voltage difference V between its grid (G) and source electrode (S) _GSUsually only has 100mV ~ 500mV, than the base stage (B) of the triode that is operated in sub-threshold region and the voltage difference V between emitter (E) _BE(300mV ~ 800mV) be much smaller as the aforementioned usually.With to work in sub-threshold region similar, when the NMOS pipe of tc compensation unit worked in the saturation region, generating circuit from reference voltage also can normal operation under extremely low supply voltage, thereby had enlarged the operating voltage range of this circuit.

Fig. 4 shows the circuit diagram of generating circuit from reference voltage the second embodiment of the present invention.With reference to figure 4, to compare with the first embodiment, the difference part of the present embodiment generating circuit from reference voltage is: described current lens unit 100 comprises the first electron current mirror unit 101 and clamp units 300.

Described the first electron current mirror unit 101 comprises a PMOS pipe MP1, the 2nd PMOS pipe MP2 and the 3rd PMOS pipe MP3, and the grid of a described PMOS pipe MP1, the 2nd PMOS pipe MP2 and the 3rd PMOS pipe MP3 is connected, and source electrode all is connected to supply voltage VDD; The drain electrode of described the 2nd PMOS pipe MP2 is as the first node C of described current lens unit 100, and the drain electrode of described the 3rd PMOS pipe MP3 is as the Section Point D of described current lens unit 100; The drain electrode of a described PMOS pipe MP1 is as the 3rd node E of described current lens unit 100;

Described clamp units 300 comprises error amplifier 301, and the negative input of described error amplifier 301 connects the drain electrode of the 2nd PMOS pipe MP2, and positive input connects the drain electrode of the 3rd PMOS pipe MP3, and output terminal connects the grid of a described PMOS pipe MP1.

Similar with the first embodiment, in the present embodiment, described generating circuit from reference voltage substitutes triode in prior art with the NMOS pipe.Thereby make this circuit can be operated under lower supply voltage, and then enlarged the scope of the operating voltage of this circuit.

Fig. 5 shows the circuit diagram of generating circuit from reference voltage the 3rd embodiment of the present invention.With reference to figure 5, be with the difference part of the first embodiment: described current lens unit 100 also comprises a ZMOS pipe Z1.The drain electrode of described the 5th NMOS pipe NM5 connects the drain electrode of described the 3rd PMOS pipe MP3 by a described ZMOS pipe Z1.

Particularly, in the present embodiment, the grid of a described ZMOS pipe Z1 connects the grid of described the 4th NMOS pipe NM4; Source electrode connects the drain electrode of described the 5th NMOS pipe NM5; Drain electrode connects the drain electrode of described the 3rd PMOS pipe MP3.

For convenience, the grid that a described ZMOS is managed Z1 is defined as node J, and the source electrode of a described ZMOS pipe Z1 is defined as node K.

In the present embodiment, the voltage difference between node J and node K is the grid of described ZMOS pipe Z1 and the voltage difference V between source electrode _GSShould be understood that, the threshold voltage of ZMOS pipe is low than common metal-oxide-semiconductor.Therefore, when described ZMOS pipe Z1 was in same working current with common metal-oxide-semiconductor, described ZMOS managed the grid of Z1 and the voltage difference V between source electrode _GSSmaller.So the voltage at node K place is lower, thus the drain electrode of the 5th NMOS pipe NM5 and the voltage difference V between substrate _DBSmaller, the drain electrode of simultaneously described the 5th NMOS pipe NM5 and the voltage difference V between source electrode _DSAlso smaller, and then avoided forming larger leakage current between the drain electrode of described the 5th NMOS pipe NM5 and substrate.

In other words, even when supply voltage VDD is higher, a described ZMOS pipe Z1 still can make the drain voltage (being the voltage at node K place) of the 5th NMOS pipe NM5 be in electronegative potential, thereby avoids described the 5th NMOS pipe NM5 to have larger leakage current.That is to say, the generating circuit from reference voltage of the present embodiment can be operated under higher supply voltage; By aforementioned analysis as can be known, substituted triode due in the tc compensation unit with the NMOS pipe, therefore, this circuit also can be operated under lower supply voltage, and therefore, the operating voltage range of circuit shown in Figure 5 has obtained enlarging further.

Similar with the first embodiment, the generating circuit from reference voltage of the present embodiment adopts the second electron current mirror unit 102 to substitute error amplifier of the prior art, has reduced the power consumption of circuit.

The inventor has carried out emulation to the generating circuit from reference voltage of the 3rd embodiment, and when the NMOS of tc compensation unit 200 pipe all worked in sub-threshold region, the reference voltage V ref of generation as shown in Figure 6.With reference to figure 6, ordinate represents is the reference voltage value (mV) of circuit output, horizontal ordinate represents be temperature (℃).Respectively corresponding 10 the different supply voltage values of curve L11 ~ L20.Particularly, the supply voltage VDD that curve L11 ~ curve L20 is corresponding is followed successively by 1.50V, 2.00V, 2.50V, 3.00V, 3.50V, 4.00V, 4.50V, 5.00V, 5.50V, 6.00V.

As seen from Figure 6, generating circuit from reference voltage shown in Figure 5 all can work when low supply voltage (for example 1.50V) reaches than high power supply voltage (for example 6.00V), and the reference voltage of its output is all very accurate.Can't be operated in problem under low supply voltage thereby overcome generating circuit from reference voltage in the prior art, and then enlarge the operating voltage range of circuit.

In addition, the threshold voltage V of a described ZMOS pipe Z1 _thAlso very little (only have 100mV ~ 300mV) usually, voltage difference between the drain voltage of the drain voltage of described the 4th NMOS pipe NM4 and described the 5th NMOS pipe NM5 also only has the hundreds of millivolt, so, flow through the first resistance R 21 and the second resistance R 22 electric current also very little (for example, 100nA).Therefore, the fluctuation of the reference voltage V ref of this generating circuit from reference voltage output is little, and then has improved the precision of reference voltage.

Further, because generating circuit from reference voltage shown in Figure 5 only is comprised of three branch roads, so the power consumption of this circuit is very little.

When a described NMOS pipe NM1, the 2nd NMOS pipe NM2 and the 3rd NMOS pipe NM3 all worked in the saturation region, the inventor carried out emulation and forms Fig. 7 the generating circuit from reference voltage of the 3rd embodiment.With reference to figure 7, ordinate represents is the reference voltage value (V) of this circuit output, horizontal ordinate represents be temperature (℃).Respectively corresponding 10 the different supply voltage values of curve L21 ~ L30.Particularly, the supply voltage VDD that curve L21 ~ curve L30 is corresponding is followed successively by 1.60V, 2.09V, 2.58V, 3.07V, 3.56V, 4.04V, 4.53V, 5.02V, 5.51V, 6.00V.

Can be drawn by Fig. 7, the operating voltage range of the generating circuit from reference voltage of the present embodiment is 1.60V ~ 6.00V, and this scope is much wider than the working range of generating circuit from reference voltage in prior art; The reference voltage value of (for example 1.60V) the time output under low supply voltage of the generating circuit from reference voltage in the present embodiment is also very accurate, can satisfy the demand of subsequent conditioning circuit.

In sum, the generating circuit from reference voltage of technical solution of the present invention has following beneficial effect at least: after substituting existing triode with the NMOS pipe, the generating circuit from reference voltage of technical solution of the present invention can be operated under lower supply voltage, has therefore enlarged the scope of its operating voltage; Preferably, current lens unit also comprises a ZMOS pipe, by increasing this ZMOS pipe, makes this circuit can also be operated under higher supply voltage, therefore, has further enlarged the operating voltage range of this generating circuit from reference voltage.And, owing to having substituted error amplifier of the prior art with current lens unit in this circuit, reduced the power consumption of circuit when exporting reference voltage accurately.

Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection domain of technical solution of the present invention according to technical spirit of the present invention.

Claims (8)

1. a generating circuit from reference voltage, is characterized in that, comprising: current lens unit, the first resistance, the second resistance and tc compensation unit, wherein,

Described current lens unit comprises first node, Section Point and the 3rd node, the electric current at the electric current at described first node place, Section Point place and the electric current of the 3rd Nodes be proportional relation respectively, and described the 3rd node is as the output terminal of described generating circuit from reference voltage;

Described tc compensation unit comprises: a NMOS pipe, the 2nd NMOS pipe and the 3rd NMOS pipe, the grid of a described NMOS pipe and the second end that drains and be connected and be connected described the first resistance, source ground; The grid of described the 2nd NMOS pipe and the first node that drains and be connected and be connected described current lens unit, source ground; The grid of described the 3rd NMOS pipe and the second end that drains and be connected and be connected described the second resistance, source ground; A described NMOS pipe, the 2nd NMOS pipe and the 3rd NMOS pipe are operated in sub-threshold region or saturation region;

The first end of described the first resistance connects the Section Point of described current lens unit;

The first end of described the second resistance connects the 3rd node of described current lens unit.

2. generating circuit from reference voltage as claimed in claim 1, is characterized in that, described current lens unit comprises:

The first electron current mirror unit comprises a PMOS pipe, the 2nd PMOS pipe and the 3rd PMOS pipe, and the source electrode of a described PMOS pipe, the 2nd PMOS pipe and the 3rd PMOS pipe all is connected to supply voltage, and grid all is connected to the drain electrode of described the 3rd PMOS pipe; The drain electrode of a described PMOS pipe is as the 3rd node of described current lens unit;

The second electron current mirror unit comprises: the 4th NMOS pipe and the 5th NMOS pipe, and the grid of described the 4th NMOS pipe is connected with drain electrode, and is connected to the drain electrode of described the 2nd PMOS pipe; The source electrode of described the 4th NMOS pipe is as the first node of described current lens unit; The grid of described the 5th NMOS pipe connects the grid of described the 4th NMOS pipe, and drain electrode couples the drain electrode of described the 3rd PMOS pipe, and source electrode is as the Section Point of described current lens unit.

3. generating circuit from reference voltage as claimed in claim 2, is characterized in that, the breadth length ratio of the breadth length ratio of a described PMOS pipe, the 2nd PMOS pipe and the breadth length ratio of the 3rd PMOS pipe equate.

4. generating circuit from reference voltage as claimed in claim 2, is characterized in that, the breadth length ratio of described the 4th NMOS pipe equates with the breadth length ratio of the 5th NMOS pipe.

5. generating circuit from reference voltage as claimed in claim 2, is characterized in that, described current lens unit also comprises: a ZMOS pipe, the drain electrode of described the 5th NMOS pipe connect the drain electrode of described the 3rd PMOS pipe by a described ZMOS pipe.

6. generating circuit from reference voltage as claimed in claim 5, is characterized in that, the grid of a described ZMOS pipe connects the grid of described the 4th NMOS pipe, and source electrode connects the drain electrode of described the 5th NMOS pipe, and drain electrode connects the drain electrode of described the 3rd PMOS pipe.

7. generating circuit from reference voltage as claimed in claim 1, is characterized in that, described current lens unit comprises: the first electron current mirror unit and clamp units;

Described the first electron current mirror unit comprises a PMOS pipe, the 2nd PMOS pipe and the 3rd PMOS pipe, and the grid of a described PMOS pipe, the 2nd PMOS pipe and the 3rd PMOS pipe is connected, and source electrode all is connected to supply voltage; The drain electrode of described the 2nd PMOS pipe is as the first node of described current lens unit, and the drain electrode of described the 3rd PMOS pipe is as the Section Point of described current lens unit; The drain electrode of a described PMOS pipe is as the 3rd node of described current lens unit;

Described clamp units comprises error amplifier, and the negative input of described error amplifier connects the drain electrode of the 2nd PMOS pipe, and positive input connects the drain electrode of the 3rd PMOS pipe, and output terminal connects the grid of a described PMOS pipe.

8. generating circuit from reference voltage as claimed in claim 1, is characterized in that, the proportionate relationship between the electric current at the electric current at the first node place of described current lens unit, Section Point place and the electric current of the 3rd Nodes is 1:1:1.

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