CN103078698B - A kind of channel delay compensation method - Google Patents
A kind of channel delay compensation method Download PDFInfo
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- CN103078698B CN103078698B CN201210580867.XA CN201210580867A CN103078698B CN 103078698 B CN103078698 B CN 103078698B CN 201210580867 A CN201210580867 A CN 201210580867A CN 103078698 B CN103078698 B CN 103078698B
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Abstract
The present invention relates to one channel delay compensation method the quickest, high-precision, main website end transmission time encoding information, after SDH network, arrives slave station end, is encoded by slave station end time of return, return to main website end after via the SDH network of symmetric path.And main website end is in time sending time encoding, open FPGA high-frequency clock enumerator, stop after encoding to the time of receipt (T of R), passage two-way transmission time T1 can be measured.After the repeated multiple times Measurement channel time, according to Frequency Synchronization principle, count value is compensated and can draw accurate channel time delay, apply in terms of time unification for SDH ground synchronous net and provide a kind of reference.
Description
Technical field
Concrete scheme when the present invention relates to based on ultimate principle during SDH symmetric path service channel pair and utilize SDH to realize accurate pair, is specifically related to one channel delay compensation method the quickest, high-precision.
Background technology
Clock synchronization system is that one can receive external time reference signal, and time precision outside output time synchronizing signal as requested and the system of temporal information.It can make in network other clock alignment and synchronize, popular for time synchronized take technical measures that network internal clock is implemented high accuracy " to table " exactly.Time synchronized is widely used in various information system, especially in the Complex Information System of time-sensitive.As a example by intelligent substation of electric power system, all kinds of devices require time for synchronizing, and to ensure that all kinds of device action order is correct and adapts to the environmental condition that the signal of telecommunication runs with the light velocity, if time irreversibility, likely will result in systemic breakdown under serious conditions.
Additionally, time synchronized is the most critically important in many fields, as in financial transaction, follow the trading rules of " price priority, time priority "；User's charging was linked up with the most completely with the time in a communications system；The Transaction Information of accurate recording client is needed in large-scale distributed business database；Above-mentioned all kinds of phenomenon is closely related with precise synchronization invariably.According to whole nation power technical market association it is expected that before 2012, holding is not less than the growth rate of 40% by clock synchronization system.Along with State Grid Corporation of China's intelligent grid construction plan, the intellectuality of equipment, measuring and control data gathers, the networking of transmission, the precision of time service is had higher requirement, will further enhance the measurement to links such as generating, transmission of electricity, distribution, scheduling and monitoring, this needs to set up unified clock synchronization, the Synchronization Network of unified time service at the whole network simultaneously.Power system stability is run by time synchronized, monitoring protection, fault analysis and handling etc. are significant.Therefore, clock synchronization system is one of most important basic guarantee of intelligent grid, and currently mainly uses spacebased system (GPS or the Big Dipper) synchronization scenario, is affected the biggest by weather, region, environment and anthropic factor.Any spacebased system signal is all easily subject to interference, and including artificial (as military) and natural (such as solar flare, weather etc.), reliability cannot ensure, risk is self-evident.The Time Synchronizing based on SDH introduced herein, it is possible to use existing SDH network realizes time synchronized, effectively backs up as GPS solution, the safety and reliability of significant increase system.
China uses the E1 standard in Europe, and the data transfer rate of E1 is exactly 2.048Mbit/s.One time division multiplex frame (its length T=125us) of E1 is divided into 32 equal time slots altogether, the numbered CH0-CH31 of time slot.Wherein time slot CH0 is used as frame synchronization use, and time slot CH16 is used for transmitting signaling, and remaining CH1-CH15 and CH17-CH31 totally 30 time slots are used as 30 speech channels.Each time slot transmits 8bit, therefore shares 256bit.8000 frames of transmission per second, therefore the data transfer rate of PCM primary group E1 is exactly 2.048Mbit/s.
SDH network is the digital transport network of a Frequency Synchronization, the grade master-slave synchronisation of the i.e. three-layer network of Frequency Synchronization.SDH equipment has clock interface and module, subordinate's clock tracing locking upper level clock during normal work, synchronizing datum signal can be transmitted by STM-N stream line, it is possible to receive external timing signal or external timing signal is provided, and clock switch the most automatically can be carried out according to clock quality.Therefore, SDH is the user of frequency synchronization signal, is again the biography loser of frequency synchronization signal.
Increase in existing SDH system peripherals and be responsible for sending and accepting time coding signal with E1 interface time synchronizer.By transmitting terminal receive external clock reference (gps satellite, BD satellite, IRIG-BDC, PTP etc.) obtain temporal information encode and send reference time signal input host node, it is issued to the SDH network equipment receiving terminal from node by the SDH network equipment of host node again, is realized the transmission of time by the 2ME1 interconnecting channel between master and slave node.While receiving terminal resolves the temporal information received, the time encoding received is sent back to transmitting terminal via SDH network equipment, measure for communication channel delay.Due to SDH network equipment room Frequency Synchronization, then receiving terminal and transmitting terminal conjunction measuring go out accurate communication channel delay, thus the most just can recover precise time information.
The most general channel delay compensation method is two dimensional method, and this two dimensional method also has application, optical-fiber longitudinal difference circuit relay protection system to commonly use two dimensional method calculating channel time delay in power system；Traditional trapezoidal two dimensional method is to use most algorithms at present, but these algorithms all also exist defect error.
Summary of the invention
It is an object of the invention to overcome above-mentioned deficiency, it is provided that one channel delay compensation method the quickest, high-precision.
Realize the technical measures of above-mentioned purpose:
Main website end transmission time encoding information, after SDH network, arrives slave station end, is encoded by slave station end time of return, return to main website end after via the SDH network of symmetric path.And main website end is in time sending time encoding, open FPGA high-frequency clock enumerator, stop after encoding to the time of receipt (T of R), passage two-way transmission time T1 can be measured.After the repeated multiple times Measurement channel time, according to Frequency Synchronization principle, count value is compensated and can draw accurate channel time delay.This measuring method is be applicable to way symmetric SDH network.After measuring in real time, being calculated channel time delay, delay time is sent by the time encoding of next second, after slave station end time of receipt (T of R) coding, resolve and i.e. can get channel time delay, and according to real-Time Compensation algorithm, calculate offset.In pulse-recovery module in write FPGA, high-precision pulse signal can be recovered.
If θ (t) is the phase function of main website end time standard function, 0≤θ (t) ＜ 2 π.
Then θ (t1) is that main website sends the phase place from node time canonical function of n-th frame moment t1 to slave station；
θ (t2) is the phase place that slave station end receives the main website end time standard function of n-th frame moment t2；
θ (t3) is the phase place that main website end receives the main website end time standard function of the Frame moment t3 that slave station end returns；
δ 1 is the n-th frame main website end transmission delay to slave station end；
δ 2 n-th frame slave station end returns to the propagation delay time of main website end；
θ e is the phase contrast of main website end advanced slave station end time standard function.
If the phase contrast that α is t1 Yu the t3 moment, obtain α=2n π+θ (t3)-θ (t1)
β is the phase contrast in t2 Yu t3 moment, obtains β=2m π+φ (t3)-φ (t2)
Loop time delay δ 1+ δ 2=α ω 2-β ω----------------------(1) can be obtained
If δ 2=p δ 1
Obtain θ e=2k π+θ (t1)-φ (t2)+11+p (α-ω 1 ω 2 β)----(2)
In (2) formula, θ (t) measures at main website end.Therefore, the accuracy that θ e can reach depends on main website end clock accuracy.And the basis that slave station end recovers pulse is exactly θ e.Clock synchronization accuracy depends entirely on the clock accuracy that main website end is used with slave station end.
After using the channel delay compensation method of the present invention, the pulse accuracy after obtained master-slave synchronisation is greatly improved, close to the Time Transmission precision of navigational satellite system.
Accompanying drawing explanation
Fig. 1 is the operation principle schematic diagram of existing two dimensional method.
Fig. 2 is the schematic diagram of the channel delay compensation method that the present invention uses.
Fig. 3 is Intelligent Recognition software processing flow figure.
Schematic diagram when Fig. 4 is pair.
Fig. 5 for pair time realize block diagram.
Detailed description of the invention
Below in conjunction with the accompanying drawings the preferred embodiments of the present invention are described in detail, so that advantages and features of the invention can be easier to be readily appreciated by one skilled in the art, thus protection scope of the present invention are made apparent clear and definite defining.
Fig. 4,5 for pair time schematic diagram and pair time realize block diagram, Fig. 1 is the operation principle schematic diagram of existing two dimensional method, this two dimensional method also have in power system application, optical-fiber longitudinal difference circuit relay protection system commonly use two dimensional method calculate channel time delay；Traditional trapezoidal two dimensional method is to use most algorithms at present.
Fig. 2 is the schematic diagram of the channel delay compensation method that the present invention uses, time encoding information is sent after SDH network by main website end unlike Fig. 1, arrive slave station end, encoded by slave station end time of return the most again, after via the SDH network of symmetric path, return to main website end.And main website end is in time sending time encoding, open FPGA high-frequency clock enumerator, stop after encoding to the time of receipt (T of R), passage two-way transmission time T1 can be measured.After the repeated multiple times Measurement channel time, according to Frequency Synchronization principle, count value is compensated and can draw accurate channel time delay.This measuring method is be applicable to way symmetric SDH network.After measuring in real time, being calculated channel time delay, delay time is sent by the time encoding of next second, after slave station end time of receipt (T of R) coding, resolve and i.e. can get channel time delay, and according to real-Time Compensation algorithm, calculate offset.In pulse-recovery module in write FPGA, high-precision pulse signal can be recovered.
Fig. 3 is the schematic diagram of phase difference measurement algorithm, is used for the phase contrast measuring main website end with slave station end time standard function.As it is shown on figure 3, top half is that the time standard function (angular frequency is ω 1) that produces of main website end, main website end are sent to the 2.048Mbit/s Frame of slave station end and main website terminates the Frame from slave station end received in figure.In figure, the latter half is time standard function (angular frequency is ω 2), 2.048Mbit/s Frame that slave station end is sent to main website end and the Frame carrying out autonomous node that receives from node that slave station end produces.
If θ (t) is the phase function of main website end time standard function, 0≤θ (t) ＜ 2 π.
Then θ (t1) is that main website sends the phase place from node time canonical function of n-th frame moment t1 to slave station；
θ (t2) is the phase place that slave station end receives the main website end time standard function of n-th frame moment t2；
θ (t3) is the phase place that main website end receives the main website end time standard function of the Frame moment t3 that slave station end returns；
δ 1 is the n-th frame main website end transmission delay to slave station end；
δ 2 n-th frame slave station end returns to the propagation delay time of main website end；
θ e is the phase contrast of main website end advanced slave station end time standard function.
If the phase contrast that α is t1 Yu the t3 moment, obtain α=2n π+θ (t3)-θ (t1)
β is the phase contrast in t2 Yu t3 moment, obtains β=2m π+φ (t3)-φ (t2)
Loop time delay δ 1+ δ 2=α ω 2-β ω----------------------(1) can be obtained
If δ 2=p δ 1
Obtain θ e=2k π+θ (t1)-φ (t2)+11+p (α-ω 1 ω 2 β)----(2)
In (2) formula, θ (t) measures at main website end.Therefore, the accuracy that θ e can reach depends on main website end clock accuracy.And the basis that slave station end recovers pulse is exactly θ e.Clock synchronization accuracy depends entirely on the clock accuracy that main website end is used with slave station end.
| Byte number | Explanation | Remarks |
| 0 | 0x9B | Synchronous head |
| 1 | 0x7E | Synchronous head |
| 2 | 0x5d | Function code |
| 3 | 0x8f | Function code |
| 4 | Year | Year-2000 |
| 5 | Month | Month |
| 6 | Day | Day |
| 7 | Time | Time |
| 8 | Point | Point |
| 9 | Second | Second |
| 10 | Temporal quality | 0-f |
| 11 | Clock source type | 0X10-GPS/0X30-BD/0X50-IRIG-B |
| 12 | XX-LL | Communication channel delay 0-7bit |
| 13 | XX-L | Communication channel delay 8-15bit |
| 14 | XX-H | Communication channel delay 16-23bit |
| 15 | XX-HH | Communication channel delay 23-31bit |
| 16 | CRC-L | Verification low byte |
| 17 | CRC-H | Verification high byte |
Data-frame times coding schedule
Embodiment
The system of this embodiment is made up of master device and slave station equipment, uses Guangzhou power supply administration existing SDH optical fiber ring network E1 designated lane transmission timing signal between main website and slave station equipment.
Master device possesses GPS and the ability of big-dipper satellite time signal of simultaneously receiving, and is integrated with the constant-temperature crystal oscillator (± 2e-8) of high stability.Master device provides E1 passage G.703 interface based on SDH, provides standard time service and communication channel delay to measure in point-to-point mode for slave station and supports service with revising.
Slave station equipment passes through E1 passage G.703 interface based on SDH; it is integrated with the constant-temperature crystal oscillator (± 2e-8) of high stability; the time reference signal that main website provides is received in point-to-point mode; communication channel delay is measured and is revised; possess dynamic delay compensation and the most punctual function, it is possible to other equipment (power grid time such as substation configuration synchronizes system, protection device etc.) for slave station provide in high precision and the timing signal of high stability.
Test result
In test process, main website terminates into GPS pulse as clock source.Starting test after 30 minutes locks in time, the testing time is 2 hours.Test result: slave station end output pulse per second (PPS) accuracy such as following table:
Laboratory closed loop test result table
Field loop test result table
From prototype experiment data it can be seen that pulse accuracy≤± 500ns after master-slave synchronisation, close to the Time Transmission precision of navigational satellite system.
Note: experimental data reflects constant-temperature crystal oscillator not through situation about taming.
Above example, the simply present invention more preferably one of detailed description of the invention, the those skilled in the art's usual variations and alternatives in the range of the solution of the present invention all should comprise within the scope of the present invention.
Claims (1)
1. a channel delay compensation method, it is characterised in that
Main website end sends time encoding information after SDH network, arrive slave station end, encoded by slave station end time of return the most again, main website end is returned to after via the SDH network of symmetric path, and main website end is in time sending time encoding, open FPGA high-frequency clock enumerator, stop after encoding to the time of receipt (T of R), passage two-way transmission time T1 can be measured；After the repeated multiple times Measurement channel time, according to Frequency Synchronization principle, count value is compensated and can draw accurate channel time delay；
Corresponding backoff algorithm is:
If θ (t) is the phase function of main website end time standard function, 0≤θ (t) ＜ 2 π；
Then θ (t1) is that main website sends the phase place from node time canonical function of n-th frame moment t1 to slave station；
θ (t2) is the phase place that slave station end receives the main website end time standard function of n-th frame moment t2；
θ (t3) is the phase place that main website end receives the main website end time standard function of the Frame moment t3 that slave station end returns；
δ 1 is the n-th frame main website end transmission delay to slave station end；
δ 2 n-th frame slave station end returns to the propagation delay time of main website end；
θ e is the phase contrast of main website end advanced slave station end time standard function；
If the phase contrast that α is t1 Yu the t3 moment, obtain α=2n π+θ (t3)-θ (t1)
β is the phase contrast in t2 Yu t3 moment,
Loop time delay δ 1+ δ 2=α ω 2-β ω----------------------(1) can be obtained
If δ 2=p δ 1
?
In (2) formula, θ (t) measures at main website end, and therefore, the accuracy that θ e can reach depends on main website end clock accuracy, and the basis that slave station end recovers pulse is exactly θ e, clock synchronization accuracy depends entirely on the clock accuracy that main website end is used with slave station end；
When being applied in way symmetric SDH network, after measuring in real time, being calculated channel time delay, delay time is sent by the time encoding of next second, after slave station end time of receipt (T of R) coding, resolve and i.e. can get channel time delay, and according to real-Time Compensation algorithm, calculate offset；And write in the pulse-recovery module in FPGA, high-precision pulse signal can be recovered.
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| CN115047743B (en) * | 2022-08-16 | 2022-11-01 | 中国船舶重工集团公司第七0七研究所 | Time-consuming end high-precision time delay compensation method based on feedback |
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| CN1698295A (en) * | 2003-01-30 | 2005-11-16 | 三星电子株式会社 | Apparatus and method for measuring and compensating delay between main base station and remote base station interconnected by an optical cable |
| WO2008139064A2 (en) * | 2007-04-06 | 2008-11-20 | Centre National D'etudes Spatiales (C.N.E.S.) | Clock extraction device with digital phase lock, requiring no external control |
| CN101499871A (en) * | 2008-02-03 | 2009-08-05 | 大唐移动通信设备有限公司 | Time delay detection method for SDH time delay, time clock synchronization method, master and slave time clock entity and SDH network element |
| CN101557258A (en) * | 2009-02-27 | 2009-10-14 | 工业和信息化部通信计量中心 | Method for using synchronous digital hierarchy (SDH) to realize high-accuracy time synchronization, system and time delay measuring device |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1394012A (en) * | 2001-06-30 | 2003-01-29 | 华为技术有限公司 | Phase compensation method and device for uplink burst control of TDM/TDMA system |
| CN1698295A (en) * | 2003-01-30 | 2005-11-16 | 三星电子株式会社 | Apparatus and method for measuring and compensating delay between main base station and remote base station interconnected by an optical cable |
| WO2008139064A2 (en) * | 2007-04-06 | 2008-11-20 | Centre National D'etudes Spatiales (C.N.E.S.) | Clock extraction device with digital phase lock, requiring no external control |
| CN101499871A (en) * | 2008-02-03 | 2009-08-05 | 大唐移动通信设备有限公司 | Time delay detection method for SDH time delay, time clock synchronization method, master and slave time clock entity and SDH network element |
| CN101557258A (en) * | 2009-02-27 | 2009-10-14 | 工业和信息化部通信计量中心 | Method for using synchronous digital hierarchy (SDH) to realize high-accuracy time synchronization, system and time delay measuring device |
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