CN103067310A - Interconnection device and method supporting UTOPIA MASTER port - Google Patents

Abstract

The invention discloses an interconnection device and a method supporting UTOPIA MASTER port. The interconnection device comprises the following modules, a UTOPIA SLAVE controller, a memory controller, and a random access memory (RAM). The UTOPIA SLAVE controller is connected with the UTOPIA MASTER port and the memory controller. An asynchronous transfer mode (ATM) cell sent by the UTOPIA MASTER is received by the UTOPIA SLAVE controller; the memory controller controls the reading and writing of the ATM cell. And the cell is sent to the UTOPIA MASTER at the other end after caching. After the processing, a chip is capable of achieving the port interconnection of the UTOPIA MASTER.

Description

A kind of support UTOPIA MASTER interface interconnection device and method

Technical field

The present invention relates to communication network field, relate in particular to a kind of support UTOPIA MASTER interface interconnection device and method.

Background technology

ATM (Asynchronous Transfer Mode, asynchronous transfer mode) is a kind of High-Speed Communication Technique that comprises the technology contents such as transmission, networking and exchange.ATM communication with fixed-length cell (Cell) as base unit multiplexing and exchange, long 53 bytes of ATM cell, wherein 5 bytes are as header, 48 bytes are as information field.Each bit in cell is that the mode with continuous crossfire transmits in transmission path, and cell can correspond to the transmission path of a reality.

UTOPIA (Universal Test ﹠amp; Operations PHY Interface for ATM, Universal Test ﹠ Operations PHY Interface for ATM), be the interface that connects ATM layer and physical layer, allow physical layer to carry out transfer of data with different speed at different mediums.UTOPIA is used for transmitting the ATM cell of fixed length, can connect a plurality of equipment, a plurality of equipment can share a cover bus and carry out exchanges data, in mutual process, initiate for the poll (Polling) from equipment as main equipment, and then finish the mutual of data.

The mode of operation of UTOPIA can be divided into 2 two kinds of Level 1 and Level.The mode of operation of UTOPIALevel 1 is 1MASTER-1SLAVE; And the mode of operation of UTOPIA Level 2 is divided into four kinds of (1) 1MASTER-1SLAVE (2) 1MASTER-MultiSLAVE (3) Multi MASTER-1 SLAVE (4) Multi MASTER-MultiSLAVE.Mostly only support 1 MASTER-Multi SLAVE at the chip that UTOPIA Level 2 interfaces are provided on the market now.So now just be illustrated as an example of UTOPIA Level 2 (2) 1MASTER-Multi SLAVE example.

See also Fig. 1, be display standard UTOPIA Level 2 interfaces between 1MASTER-Multi SLAVE, the transmission of MASTER101 and receive signal.MASTER 101 is having TxClk aspect transmission (Tx) signal, TxAddr, and TxEnb, TxData, TxSOC offer Multi SLAVE102; Multi SLAVE102 then has TxClav to MASTER101 aspect transmitted signal.Wherein, the TxClk:MASTER101 tranmitting data register is so that Multi SLAVE102 is synchronous with it; The address of TxAddr:5 bit sends to the SLAVE102 poll or with the TxEnb amalgamation SLAVE102 to be done to send appointment by MASTER101; TxEnb:MASTER101 send enable signal (state of Enable in order to indicate the MASTER101 cell to send, and and the TxAddr amalgamation specify with the transmission of making SLAVE102; TxData:MASTER101 sends data; TxSOC: the index signal TxClav:SLAVE102 of cell initial bits is in order to respond the signal of MASTER101 poll.

MASTER101 is having RxClk aspect reception (Rx) signal, and RxAddr, RxEnb offer Multi SLAVE102; Mufti SLAVE102 is then having RxData, RxSOC, RxClav to MASTER101 aspect the reception signal.RxClk:MASTER101 sends synchronised clock so that Mufti SLAVE102 is synchronous with it; The address of RxAddr:5 bit sends to the SLAVE102 poll or with the RxEnb amalgamation SLAVE102 to be done to receive appointment by MASTER101; RxEnb:MASTER101 sends enable signal, in order to the state of indicating the MASTER101 cell to receive, and with the RxAddr amalgamation SLAVE is done reception and specifies; The RxData:MASTER101 receive data; RxSOC: the index signal of cell initial bits; RxClav:SLAVE102 is in order to respond the signal of MASTER101 poll.

Summary of the invention

Because UTOPIA Level 2 interfaces of standard are not supported the 1MASTER-MultiMASTER pattern, the invention provides a kind of support UTOPIA MASTER interface interconnection device, this device comprises UTOPIA SLAVE controller 210, Memory Controller Hub 230, RAM240, it is characterized in that: also comprise cell receiver module 211 and cell sending module 212.

UTOPIA SLAVE controller 210 receives the ATM cell that UTOPIA MASTER220 sends, and ATM cell is sent to Memory Controller Hub 230; The ATM cell of 230 pairs of receptions of Memory Controller Hub is carried out buffer memory and cell is sent to another UTOPIASLAVE controller 210, and the ATM cell among the Memory Controller Hub 230 control RAM240 reads and write operation; UTOPIA SLAVE controller 210 receives the ATM cell of Memory Controller Hub 230, and sends to UTOPIA MASTER220.

UTOPIA SLAVE controller 210: be used for finishing UTOPIA MASTER220 and the signaling interface that installs inner Memory Controller Hub 230.UTOPIA SLAVE controller 210 comprises cell receiver module 211 and cell sending module 212.

Cell receiver module 211 is used for receiving the ATM cell that UTOPIA MASTER220 sends.

Cell sending module 212 is used for sending ATM cell to UTOPIA MASTER220.

Memory Controller Hub 230: the ATM cell that is used for control RAM240 reads and write operation, finishes carrying out buffer memory from the ATM cell of UTOPIA SLAVE controller 210 and ATM cell being sent to the operation of another UTOPIA SLAVE controller 2l0.

RAM240: be used for the buffer memory ATM cell.

The present invention also provides a kind of support UTOPIA MASTER interface interconnecting method, may further comprise the steps:

1. be in idle condition after device resets, when detect TxAddr effectively after, provide SLAVE and send the matching addresses indication;

2. judge that RAM is whether full, discontented then to enable TxClav effective, reply MASTER220 and can send cell, and prepare the reception cell;

3. work as TX ENB and enable, when TX SOC is effective, begin to receive cell, and cell is stored among the RAM240;

4. when detect RxAddr effectively after, provide the indication of SLAVE receiver address coupling;

5. judge whether RAM240 is empty, and the not empty RxClav that then enables is effective, replys MASTER220 and prepares to receive cell, the cell among the RAM240 is sent to the UTOPIA MASTER of the other end.

Description of drawings

Fig. 1 is the schematic diagram of standard UTOPIA Level 2 interface sending/receiving signals.

Fig. 2 is the electric principle logic block-diagram that the present invention supports UTOPIA MASTER interface interconnection device.

Fig. 3 is the workflow diagram that the present invention supports the interconnection of UTOPIA MASTER interface.

Embodiment

Below in conjunction with accompanying drawing the described technical scheme of the embodiment of the invention is described in further detail.

With reference to Fig. 2, a kind of support UTOPIA MASTER interface interconnection device connects two UTOPIA MASTER220 by the UTOPIA interface, finishes interconnect function between the two.

Specifically comprise:

UTOPIA SLAVE controller 210: be used for finishing UTOPIA MASTER220 and the signaling interface that installs inner Memory Controller Hub 230.

Cell receiver module 211 is used for receiving the ATM cell that UTOPIA MASTER220 sends.

Cell sending module 212 is used for sending ATM cell to UTOPIA MASTER220.

Memory Controller Hub 230: the ATM cell that is used for control RAM240 reads and write operation, finishes carrying out buffer memory from the ATM cell of UTOPIA MASTER220 and ATM cell being sent to the operation of another UTOPIA MASTER220.

RAM240: be used for the buffer memory ATM cell, buffer area is divided into a plurality of zones, 1 ATM cell can be stored in every zone.

The inbound port 1 of UTOPIA SLAVE controller 210 is connected with the outbound port 2 of UTOPIA MASTER220, and UTOPIA SLAVE controller 210 receives the ATM cell that UTOPIAMASTER220 sends; The outbound port 2 of UTOPIA SLAVE controller 210 is connected with the inbound port 1 of Memory Controller Hub 230, and Memory Controller Hub 230 receives the ATM cell of UTOPIASLAVE controller 210; The outbound port 4 of UTOPIA SLAVE controller 210 is connected with the inbound port 1 of UTOPIA MASTER220, is used for sending ATM cell to UTOPIAMASTER220; The inbound port 3 of UTOPIA SLAVE controller 210 is connected with the outbound port 2 of Memory Controller Hub 230, the cell among the RAM240 that UTOPIA SLAVE controller 210 reception Memory Controller Hub 230 are read; The port 3 of Memory Controller Hub 230 is connected with RAM240, the read-write of Memory Controller Hub 230 control ATM cell.

With reference to Fig. 3, the described a kind of support UTOPIA MASTER interface interconnecting method of the embodiment of the invention comprises step:

1. be in idle condition after device resets, when detecting TxAddr for after presetting effective address, provide SLAVE and send the matching addresses indication;

2. judge that RAM240 is whether full, discontented then to enable TxClav effective, reply MASTER220 and can send ATM cell, and prepare the reception cell;

3. work as TX_ENB and enable, when TX_SOC was effective, cell receiver module 211 began to receive new ATM cell, and sent to Memory Controller Hub 230; Memory Controller Hub 230 stores ATM cell among the RAM240 into;

4. when detecting RxAddr for after presetting effective address, provide the indication of SLAVE receiver address coupling;

5. judge whether RAM240 is empty, and the not empty RxClav that then enables is effective, replys MASTER220 and prepares to receive cell, reads in order the ATM cell among the RAM240, sends cell to the UTOPIA MASTER220 of the other end.

Claims (3)

1. support UTOPIA MASTER interface interconnection device for one kind, it is characterized in that: this device includes UTOPIA SLAVE controller (210), Memory Controller Hub (230), RAM (240).Wherein the inbound port 1 of UTOPIA SLAVE controller (210) is connected with the outbound port 2 of UTOPIA MASTER (220), and UTOPIA SLAVE controller (210) receives the ATM cell that UTOPIA MASTER (220) sends; The outbound port 2 of UTOPIASLAVE controller (210) is connected with the inbound port 1 of Memory Controller Hub (230), and Memory Controller Hub (230) receives the ATM cell of UTOPIA SLAVE controller (210); The outbound port 4 of UTOPIA SLAVE controller (210) is connected with the inbound port 1 of UTOPIA MASTER (220), is used for sending ATM cell to UTOPIA MASTER (220); The inbound port 3 of UTOPIA SLAVE controller (210) is connected with the outbound port 2 of Memory Controller Hub (230), the cell among the RAM (240) that UTOPIA SLAVE controller (210) reception Memory Controller Hub (230) is read; The port 3 of Memory Controller Hub (230) is connected with RAM (240), the read-write of Memory Controller Hub (230) control ATM cell.

2. support UTOPIA MASTER interface interconnection device according to claim 1, it is characterized in that: UTOPIA SLAVE controller (210) comprises cell receiver module (211) and cell sending module (212), wherein the inbound port 1 of cell receiver module (211) is connected with the outbound port 2 of UTOPIA MASTER (220), and cell receiver module (211) receives the ATM cell that UTOPIA MASTER (220) sends; The outbound port 2 of cell receiver module (211) is connected with the inbound port 1 of Memory Controller Hub (230), and Memory Controller Hub (230) receives the ATM cell of cell receiver module (211); The inbound port 1 of cell sending module (212) is connected with the outbound port 2 of Memory Controller Hub (230), the cell among the RAM (240) that cell sending module (212) reception Memory Controller Hub (230) is read; The outbound port 2 of cell sending module (212) is connected with the inbound port 1 of UTOPIA MASTER (220), is used for sending ATM cell to UTOPIA MASTER (220).

3. support UTOPIA MASTER interface interconnecting method for one kind, it is characterized in that comprising step:

1. be in idle condition after device resets, when detect TxAddr effectively after, provide SLAVE and send the matching addresses indication;

2. judge that RAM (240) is whether full, discontented then to enable TxClav effective, reply MASTER (220) and can send cell, and prepare the reception cell;

3. work as TX_ENB and enable, when TX_SOC is effective, begin to receive cell, and cell is stored among the RAM (240);

4. when detect RxAddr effectively after, provide the indication of SLAVE receiver address coupling;

5. judge whether RAM (240) is empty, and the not empty RxClav that then enables is effective, replys MASTER (220) and prepares to receive cell, the cell among the RAM (240) is sent to the UTOPIAMASTER of the other end.

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