CN103064223B - Array substrate and display panel - Google Patents
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- CN103064223B CN103064223B CN201310004002.3A CN201310004002A CN103064223B CN 103064223 B CN103064223 B CN 103064223B CN 201310004002 A CN201310004002 A CN 201310004002A CN 103064223 B CN103064223 B CN 103064223B
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Abstract
The invention discloses an array substrate and a display panel which are used for realizing no height difference in binding areas in a double-layer wired display and avoiding defective display generated by poor binding uniformity. A non-display area of the array substrate comprises a data signal input end inputting signals into the non-display area. The data signal input end comprises a plurality of first leads and second leads which correspond to data lines of a display area and are arranged at intervals. Each first lead comprises a first grating lead and a first data line lead, a first via hole and a second via hole are formed above the first grating lead and the first data line lead, and the first grating lead and the first data line lead are conducted through a first conducting layer. The second leads and the data lines in the display area share the same layer to form second data line leads, and third via holes and a second conducting layer are formed above the second data line leads. A driving circuit is bound on the first conducting layer above the first data line leads and on the second conducting layer above the second data line leads.
Description
Technical field
The present invention relates to display technique field, particularly relate to a kind of array base palte and a kind of display panel.
Background technology
The display apparatus modules such as Thin Film Transistor-LCD connect driving circuit by active array panel usually, and the external circuit then connecting other necessity is formed.Wherein the connection of driving circuit and arraying bread board needs to carry out binding realizing at the signal input part of arraying bread board usually, i.e. integrated circuit or thin film chip is integrated, flexible PCB etc. is crimped on panel by anisotropy conductiving glue signal input part, thus realize the conducting of signal.At present, in some small sizes or high-resolution product, due to the increase of wiring density on arraying bread board, signal input part adopts grid metal level and data wire metal layer double layer of metal to realize usually.As shown in Figure 1, the non-display area of panel comprises data signal input A and signal input end B, for receiving signal input or data-signal input.Wherein, data signal input A comprises the region A1 bound with driving circuit, concrete, as shown in Figure 2: the region A1 of binding comprises multiple the first binding district 010 and the second binding district 020 replaced, the data-signal that first binding district 010 and the second binding district 020 difference receiving integrate circuit pin export, transmits along corresponding cabling then.
The sectional view of district 020 along b-b ' direction is bound along the sectional view and second in a-a ' direction by the first binding district 010 that array base palte shown in Fig. 3 is respectively in corresponding diagram 2.Corresponding first binding side, district 010, as shown in Figure 3, this array base palte comprises glass substrate 100, grid line 110, first insulation course 130, data line 120, the second insulation course 140, conductive layer 150, and wherein, on grid line 110, be provided with the first binding area 0 10; Corresponding second binding side, district 020, as shown in Figure 3, array base palte comprises and on lower, comprises glass substrate 100, first insulation course 130 successively, active layer 160, data line 120, second insulation course 140 and conductive layer 150, wherein, the second binding district 020 is provided with on data line 120.
Due to the difference of materials and process, inevitably produce certain difference in height in binding district.First binding district 010 height be 4-1. with 4-2., second binding district 020 height be 4-3. with 4-4..Due to the difference of thicknesses of layers, if 4-h2 in Fig. 3 is higher than 4-h1, so 4-1. ≠ 4-3., 4-2. ≠ 4-4..Because the first binding district is different with the height in the second binding district, homogeneity difference when causing integrated circuit to crimp with array base palte between line.Therefore the risk that display that is that produce is bad because binding homogeneity is poor is considerably increased.
Summary of the invention
Embodiments provide a kind of array base palte, in order to realize binding district in the display of two-layer wiring without difference in height, and then avoid the bad problem of display because binding homogeneity difference produces.
A kind of array base palte that the embodiment of the present invention provides, comprise viewing area, non-display area and driving circuit, wherein said viewing area comprises a plurality of data lines and many grid lines, described non-display area comprises the data signal input of the data line input signal to described viewing area, described data signal input comprise corresponding with described viewing area data line and spaced many first go between and second to go between; Wherein said first lead-in wire comprises the first data cable lead wire going between with the first grid that layer is formed with the grid line of described viewing area and formed with layer with the data line of described viewing area, be formed with the first via hole and the second via hole above described first grid lead-in wire and described first data cable lead wire, described first grid lead-in wire and described first data cable lead wire are by covering the first conductive layer conducting of described first via hole and the second via hole; Second data cable lead wire of described second lead-in wire for being formed with layer with the data line of described viewing area, is provided with the 3rd via hole and covers described 3rd via hole and the second conductive layer formed with layer with described first conductive layer above described second data cable lead wire; Described driving circuit is bundled on the first conductive layer above described first data cable lead wire and the second conductive layer above the second data cable lead wire.
A kind of display panel that the embodiment of the present invention provides, comprises above-mentioned array base palte.
The array base palte that the embodiment of the present invention provides, the region that data signal input in non-display area and integrated circuit are bound, the height of conductive layer distance glass substrate is identical, thus the difference producing crimped status between line when being connected with integrated circuit can not be caused, avoid the problem that display that is that produce is bad because binding homogeneity is poor.
Accompanying drawing explanation
Fig. 1 is the binding schematic diagram of glass-chip integrated (Chip on Glass) technology in prior art;
Fig. 2 is the vertical view of the structure of binding in prior art;
Fig. 3 is the cross-sectional view in the first binding district 010 and the second binding district 020 in the structure shown in Fig. 2;
The schematic top plan view of a kind of data signal input that Fig. 4 provides for the embodiment of the present invention;
Fig. 5 is the cross-sectional view of the first lead-in wire and the second lead-in wire in the structure shown in Fig. 4;
The structural representation of grid line pattern is prepared in the preparation method of Fig. 6 (a) for the array base palte of structure shown in Fig. 5;
Fig. 6 (b) for preparing the structural representation after active layer and data line layer on the substrate shown in Fig. 6 (a);
Fig. 6 (c) is the structural representation after prepare insulation course on the substrate shown in Fig. 6 (b);
Fig. 6 (d) is the structural representation after prepare via hole on the substrate shown in Fig. 6 (c);
Fig. 6 (e) is the structural representation after prepare conductive layer on the substrate shown in Fig. 6 (d);
The another kind first that Fig. 7 provides for the embodiment of the present invention goes between and the second cross-sectional view gone between;
The structural representation of grid line pattern is prepared in the preparation method of Fig. 8 (a) for the array base palte shown in Fig. 7;
Fig. 8 (b) is the structural representation after prepare data line layer on the substrate shown in Fig. 8 (a);
Fig. 8 (c) is the structural representation after prepare insulation course on the substrate shown in Fig. 8 (b);
Fig. 8 (d) is the structural representation after prepare via hole on the substrate shown in Fig. 8 (c);
Fig. 8 (e) is the structural representation after prepare conductive layer on the substrate shown in Fig. 8 (d).
Embodiment
Embodiments provide a kind of array base palte, in order to realize binding district in the display of two-layer wiring without difference in height, and then avoid the bad problem of display because binding homogeneity difference produces.
A kind of array base palte that the embodiment of the present invention provides, comprise viewing area, non-display area and driving circuit, wherein said viewing area comprises a plurality of data lines and many grid lines, described non-display area comprises the data signal input of the data line input signal to described viewing area, described data signal input comprise corresponding with described viewing area data line and spaced many first go between and second to go between; Wherein said first lead-in wire comprises the first data cable lead wire going between with the first grid that layer is formed with the grid line of described viewing area and formed with layer with the data line of described viewing area, be formed with the first via hole and the second via hole above described first grid lead-in wire and described first data cable lead wire, described first grid lead-in wire and described first data cable lead wire are by covering the first conductive layer conducting of described first via hole and the second via hole; Second data cable lead wire of described second lead-in wire for being formed with layer with the data line of described viewing area, is provided with the 3rd via hole and covers described 3rd via hole and the second conductive layer formed with layer with described first conductive layer above described second data cable lead wire; Described driving circuit is bundled on the first conductive layer above described first data cable lead wire and the second conductive layer above the second data cable lead wire.
Preferably, described first grid lead-in wire top is provided with the first insulation course and the second insulation course successively, be respectively arranged with the first insulation course and active layer below described first data cable lead wire and the second data cable lead wire, above described first data lead and the second data lead, be provided with the second insulation course.
Preferably, described first grid lead-in wire top is provided with the first insulation course and the second insulation course successively, obtain being provided with the first insulation course below the first data cable lead wire and the second data cable lead wire, above described first data cable lead wire and the second data cable lead wire, be provided with the second insulation course.
Below in conjunction with the drawings and specific embodiments, the present invention will be described.
Embodiment 1
A kind of array base palte that the embodiment of the present invention 1 provides, comprise viewing area, non-display area and driving circuit, wherein said viewing area comprises a plurality of data lines and many grid lines, described non-display area comprises the data signal input of the data line input signal to described viewing area, herein can equally with reference to shown in accompanying drawing 1.
Below in conjunction with accompanying drawing, data signal input is described in detail.See Fig. 4, described data signal input comprise corresponding with described viewing area data line and spaced many first go between and 200 and second go between 300; Wherein said first lead-in wire 200 comprises and to go between 211 and the first data cable lead wire 212 of being formed with layer with the data line of described viewing area with the first grid that layer is formed with the grid line of described viewing area, be formed with the first via hole 221 and the second via hole 222 above described first grid lead-in wire 211 and described first data cable lead wire 212, described first grid lead-in wire 211 and described first data cable lead wire 212 are by covering the first conductive layer 231 conducting of described first via hole 221 and the second via hole 222; Described second lead-in wire 300 is the second data cable lead wire 312 formed with layer with the data line of described viewing area, is provided with the 3rd via hole 321 and covers described 3rd via hole and the second conductive layer 331 formed with layer with described first conductive layer above described second data cable lead wire; Described driving circuit (not shown) is bundled on the first conductive layer 231 above described first data cable lead wire and the second conductive layer 331 above the second data cable lead wire.
Further, for c-c ' in figure and d-d ' position, its cross-section structure is with reference to shown in Fig. 5, for the first via hole 221 position side in the first lead-in wire 200, array base palte comprises from bottom to up successively: glass substrate 100, first insulation course 130, active layer 160 and the first data cable lead wire 212, second insulation course 140, and the first via hole 221 being arranged in the second insulation course 140, cover the first conductive layer 231 of the first via hole and the second insulation course, for the second via hole 222 position side in the first lead-in wire 200, array base palte comprises successively on lower: this glass substrate of glass substrate 100(is the substrate of whole array base palte), first grid lead-in wire 211, first insulation course 130, second insulation course 140, and etching the first insulation course and the second insulation course and the second via hole 222 of obtaining, cover the first conductive layer 231 of the second via hole and the second insulation course, wherein this first conductive layer covers the first via hole and the second via hole, the first data cable lead wire be positioned under the first via hole is connected with the first grid lead-in wire be positioned under the second via hole simultaneously.For the second lead-in wire 300, array base palte comprises successively on lower: glass substrate 100, first insulation course 130, active layer 160, second data cable lead wire 312, second insulation course 140, the 3rd via hole 321 obtained by etching the second insulation course 140, and the second conductive layer 331 covering the 3rd via hole.Wherein, the conductive layer 231 be positioned at above the first via hole 221 above the first data cable lead wire is bound with driving circuit, the conductive layer 331 be positioned at above the 3rd via hole 321 above the second data cable lead wire is bound with driving circuit, as can be seen from Figure 5, 4. 2. conductive layer 231 above first via hole 221 be 4-h2 with the conductive layer 331 above the 3rd via hole 321 apart from the height 24-at the bottom of glass substrate apart from the height 24-at the bottom of glass substrate is equal, conductive layer 231 simultaneously on the second insulation course 140 of the first via hole 221 is 1. 3. equal apart from the height 24-at the bottom of glass substrate with the conductive layer 331 on the second insulation course 140 of the 3rd via hole 321 apart from the height 24-at the bottom of glass substrate.So, to the data signal input of viewing area data line input data signal when binding with driving circuit, when can ensure to bind, the height in data signal input binding district is consistent, can not cause because the height in binding district is uneven that display that is that cause is bad.
The array base palte that the embodiment of the present invention 1 provides, is prepared, see Fig. 6 (a) to 6(e by 4 patterning processes), this preparation method comprises:
On the glass substrate, grid line and each first grid lead-in wire 211 is formed by metal deposition, exposure, development and etching, as shown in Figure 6 (a);
Depositing first insulator layer 130 on the substrate forming above-mentioned pattern, material is silicon nitride normally, also can use monox and silicon oxynitride etc.;
The substrate forming above-mentioned pattern deposits active layer 160 and data line layer, and data line layer comprises data line and the first data cable lead wire 212 and the second data cable lead wire 312.And then by exposure, development and etching, form data line layer and active layer pattern; Herein, the active layer below the data line layer being positioned at non-display area is retained, and other place is etched away, as shown in Figure 6 (b); Be positioned at the pattern of viewing area, then include the pattern (not shown) of data line and tft array;
The substrate forming data line layer and active layer pattern deposits the second insulation course 140, and material is silicon nitride or transparent organic resin material normally, as shown in Figure 6 (c);
The substrate of formation second insulation course 140 forms multiple via hole by exposing and etching again, wherein the second insulation course of the second via hole 222 and the first insulation course are all etched, second insulation course at the first via hole 221 and the 3rd via hole 321 place is etched, as shown in Fig. 6 (d);
Depositing conducting layer on the substrate forming multiple via hole, material is ITO, and then by exposure, development and etching formation first conductive layer 231 and the second conductive layer 331ITO pattern, as shown in Figure 6 (e).
Through above-mentioned technique, the array base palte realizing the object of the invention can be obtained.
Embodiment 2
A kind of array base palte that the embodiment of the present invention 2 provides, the array base palte difference provided with embodiment 1 is, array base palte described in the present embodiment 2 is made by 5 patterning processes, as shown in Figure 7, between the first insulation course 130 and the first data cable lead wire 212, between the first insulation course 130 and the second data cable lead wire 312, there is no active layer.But identical with embodiment, the first conductive layer bound with driving circuit and the second conductive layer are that same layer makes, and are highly 5-h2, therefore to avoid the display that causes because binding district's difference in height equally bad.
Concrete, see Fig. 8 (a) to Fig. 8 (e), its preparation method comprises:
On the glass substrate, the pattern comprising grid line and each first grid lead-in wire 211 is formed by metal deposition, exposure, development and etching, as shown in Figure 8 (a);
Depositing first insulator layer 130 on the substrate forming above-mentioned pattern;
The substrate of formation first insulation course 130 deposits active layer, by exposure, development and etching, the active layer be positioned at below the data line layer of non-display area is all etched away herein;
Next on substrate, form data line pattern by metal deposition, exposure, development and etching, comprise the first data cable lead wire 212 and the second data cable lead wire 312 of data line and the non-display area being positioned at viewing area, as shown in Figure 8 (b) shows;
The substrate forming above-mentioned pattern deposits the second insulation course 140, as shown in Fig. 8 (c);
The substrate of formation second insulation course 140 forms multiple via hole by exposing and etching again, wherein second insulation course at the second via hole place 222 and the first insulation course are all etched, second insulation course at the first via hole and the 3rd via hole place is etched, as shown in Fig. 8 (d);
Depositing conducting layer on the substrate forming multiple via hole, such as material is transparent conductive oxide film ITO, and then by exposure, development and the pattern etching formation first conductive layer 231 and the second conductive layer 331ITO, as shown in Fig. 8 (e).
Preferably, adopt the structure of array base palte provided by the invention, in driving process, the data-signal sent by integrated circuit is transferred on panel by the first conductive layer and the second conductive layer, then data-signal transfers to each data line of viewing area along corresponding cabling connected mode, thus according to the control of sweep signal, show.Particularly, data signal data exports from integrated circuit, at the first lead-in wire place, is received, be transferred to the first data cable lead wire 212, enter viewing area by the first via hole 221 by the first conductive layer 231 be positioned at above the first via hole 221; At the second lead-in wire place, the second conductive layer 331 receives and is transferred to the second data cable lead wire 312 below it by the 3rd via hole 321, enters viewing area.
In sum, the array base palte that the embodiment of the present invention provides, identical with the height of the conductive layer distance glass substrate that driving circuit is bound in data signal input in non-display area, thus the difference producing crimped status between line when being connected with integrated circuit can not be caused, avoid the problem that display that is that produce is bad because binding homogeneity is poor.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (4)
1. an array base palte, comprise viewing area, non-display area and driving circuit, wherein said viewing area comprises a plurality of data lines and many grid lines, described non-display area comprises the data signal input of the data line input signal to described viewing area, it is characterized in that: described data signal input comprise corresponding with described viewing area data line and spaced many first go between and second to go between; Wherein said first lead-in wire comprises the first data cable lead wire going between with the first grid that layer is formed with the grid line of described viewing area and formed with layer with the data line of described viewing area, be formed with the first via hole and the second via hole above described first grid lead-in wire and described first data cable lead wire, described first grid lead-in wire and described first data cable lead wire are by covering the first conductive layer conducting of described first via hole and the second via hole; Second data cable lead wire of described second lead-in wire for being formed with layer with the data line of described viewing area, is provided with the 3rd via hole and covers described 3rd via hole and the second conductive layer formed with layer with described first conductive layer above described second data cable lead wire; Described driving circuit is bundled on the first conductive layer above described first data cable lead wire and the second conductive layer above the second data cable lead wire.
2. array base palte according to claim 1, it is characterized in that: described first grid lead-in wire top is provided with the first insulation course and the second insulation course successively, be respectively arranged with the first insulation course and active layer below described first data cable lead wire and the second data cable lead wire, above described first data cable lead wire and the second data cable lead wire, be provided with the second insulation course.
3. array base palte according to claim 1, it is characterized in that: described first grid lead-in wire top is provided with the first insulation course and the second insulation course successively, be provided with the first insulation course below described first data cable lead wire and the second data cable lead wire, above described first data cable lead wire and the second data cable lead wire, be provided with the second insulation course.
4. a display panel, is characterized in that, comprises the array base palte as described in claim as arbitrary in claims 1 to 3.
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| CN201310004002.3A CN103064223B (en) | 2013-01-07 | 2013-01-07 | Array substrate and display panel |
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| CN201310004002.3A CN103064223B (en) | 2013-01-07 | 2013-01-07 | Array substrate and display panel |
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| CN103064223B true CN103064223B (en) | 2015-02-11 |
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Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103680317B (en) * | 2013-12-20 | 2015-09-23 | 合肥京东方光电科技有限公司 | A kind of array base palte and manufacture method thereof and display device |
| CN105096753A (en) | 2015-09-01 | 2015-11-25 | 京东方科技集团股份有限公司 | Array base plate, manufacturing method of array base plate and display device |
| CN108231692A (en) * | 2018-01-02 | 2018-06-29 | 京东方科技集团股份有限公司 | A kind of array substrate and preparation method thereof, display panel and display device |
| CN108493194B (en) * | 2018-03-28 | 2020-07-24 | 京东方科技集团股份有限公司 | Array substrate and display panel |
| CN108663865A (en) * | 2018-07-24 | 2018-10-16 | 武汉华星光电技术有限公司 | Tft array substrate and its manufacturing method and flexible liquid crystal panel |
| CN110133929B (en) * | 2019-06-28 | 2022-04-22 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, display panel and display module |
| CN113516910B (en) * | 2020-04-09 | 2022-09-23 | 上海和辉光电股份有限公司 | Display panel and binding region planarization method thereof |
| CN111999947A (en) * | 2020-08-11 | 2020-11-27 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| CN112255849A (en) | 2020-11-10 | 2021-01-22 | 合肥京东方光电科技有限公司 | Display substrate and electronic device |
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