CN103063232A - One-chip latch type Hall sensor - Google Patents
One-chip latch type Hall sensor Download PDFInfo
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- CN103063232A CN103063232A CN2011103241364A CN201110324136A CN103063232A CN 103063232 A CN103063232 A CN 103063232A CN 2011103241364 A CN2011103241364 A CN 2011103241364A CN 201110324136 A CN201110324136 A CN 201110324136A CN 103063232 A CN103063232 A CN 103063232A
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Abstract
The invention relates to a one-chip latch type Hall sensor which comprises a Hall counter electrode, an amplifier, a switched capacitance circuit and a comparator, wherein the Hall counter electrode, the amplifier, the switched capacitance circuit and the comparator are sequentially connected. The one-chip latch type Hall sensor further comprises a voltage reference circuit which is connected with the switched capacitance circuit, wherein the Hall counter electrode is controlled by a first clock signal and a second clock signal, the first clock signal and the second clock signal are input from outside, the switched capacitance circuit comprises a first capacitor, a second capacitor, a third capacitor and a fourth capacitor, the first capacitor, the second capacitor, the third capacitor and the fourth capacitor are respectively provided with an upper counter electrode and a lower counter electrode, and the first clock and the second clock signal are two-phase clock signals which are non-overlapped. Due to the fact that the second capacitor and the third capacitor sample a Hall signal which is amplified by the amplifier, the first capacitor and the fourth capacitor sample reference voltages which are output by the voltage reference circuit, and meanwhile a third clock signal is introduced under the condition of sampling of the first capacitor, the second capacitor, the third capacitor and the fourth capacitor, influence of a charge injection effect and a clock feed through effect on signal establishing accuracy in the moment of switching a sampling switch is avoided.
Description
Technical field
The present invention relates to a kind of single-chip latch type Hall sensor.
Background technology
In recent years, the application of dc brushless motor in the fields such as aerospace system, national defense and military equipment, scientific instrument, industrial automation equipment, medicine equipment, the civilian consumer products of household electrical appliances is more and more extensive, is considered to the electronically controlled motor of the most rising and wide application prospect of 21 century.Hall element conduct core component wherein, its effect is also more and more obvious, and to a great extent, the performance of Hall element has directly determined the quality of dc brushless motor.
The development of semiconductor technology is made to the one chip Hall element of high integration and has been brought possibility, but because some inevitable factors in semiconductor fabrication process and the chip package process, can cause Hall element to have higher fixedly offset voltage, offset voltage tends to reach several millivolts to tens millivolts; In addition, signal amplification circuit is because the factors such as device mismatch also can be introduced fixedly offset voltage, and this voltage is also in the millivolt rank; And the Hall element sensitivity of adopting semiconductor technology to make often only has about 0.1mV/mT, so if do not adopt special circuit methods that this offset voltage is removed, hall signal then can be submerged in the offset voltage, causes signal to read.
US Patent No. 7425821 has proposed a kind of method that adopts wave chopping technology to eliminate Hall element and amplifier offset voltage, its principle is based on wave chopping technology, adopt the secondary modulation mode, at first hall signal is modulated to sample frequency, and the offset voltage of Hall pole plate and amplifier remains unchanged, signal is being used same frequency sampling again after amplifying, signal is modulated once again, hall signal is got back to fundamental frequency through after the secondary modulation like this, and offset voltage has been placed to the position of sample frequency owing to only modulated once, through behind the anti-aliasing low-pass filter, offset voltage is filtered, finally remaining hall signal only.The benefit of this method be system response time fast, eliminate the offset voltage successful, the signalling channel noise is high, shortcoming is that circuit scale is larger, the power consumption of chip, area are all larger.
Chinese patent CN101833073 has proposed a kind of method of eliminating offset voltage, and the signal modulation system of Hall pole plate is identical with US7425821, and different is: added sampling capacitance C between amplifier out and comparator input terminal
1, C
2, utilize Correlated Double Sampling disappear the offset voltage of Hall pole plate and amplifier, circuit as shown in Figure 1: two reference voltage V
1, V
2, provided by peripheral reference circuit (not shown); Switch M1, M2 control respectively reference voltage V
2, V
1Be loaded into sampling capacitance C
1, C
2Top crown; When clock signal clk is in sample states, sampling capacitance C
1, C
2Top crown connect respectively reference voltage V
2, V
1When clock signal clk was in hold mode, switch M1, M2 closed, sampling capacitance C
1, C
2Top crown be in vacant state; By principle of charge conservation as can be known, at this moment, sampling capacitance C
1, C
2The voltage difference of top crown satisfies: V
b-V
a=(V
2-V
1)+(-2AV
H), the A in this formula is the gain of amplifier 1 ', V
HBe hall signal.Can find out that this method has also obtained hall signal V when eliminating offset voltage
HStagnant regions between V
2-V
1Although this method can with the offset voltage of comparatively simple circuit for eliminating Hall pole plate and amplifier, still exist some not enough:
At first, switch M1, M2 directly are connected on sampling capacitance C
1, C
2Top crown, at switch M1, M2 shutdown moment, because the impact of charge injection and clock feed-through effect can directly cause the precision of setting up of sampled signal deviation to occur;
Secondly, switch M1, M2 switch kicking back noise (kickback noise) and can returning reference voltage V by direct-coupling of moment
2, V
1On, cause reference voltage to switch moment at switch M1, M2 and change, if release time is inadequate, also can affect the precision of setting up of signal;
At last, because the sensitivity meeting of Hall pole plate reduces with the rising of temperature, thereby can reduce between stagnant regions stability with temperature.
For these reasons, need to improve this type of one chip Hall element at present.
Summary of the invention
In order to overcome the shortcoming that exists in the above-mentioned prior art, the present invention aims to provide a kind of single-chip latch type Hall sensor, with comparatively simple circuit for eliminating offset voltage, avoid switching on the impact of signal amplification precision, reduce noise effect and also obtain better temperature stability.
A kind of single-chip latch type Hall sensor of the present invention, it comprises Hall pole plate, amplifier, switched-capacitor circuit and the comparer that connects successively, also comprise the voltage reference circuit that is connected with described switched-capacitor circuit, wherein, described Hall pole plate is by first, second clock signal control of periphery input, described voltage reference circuit comprises the first divider resistance and second divider resistance of series connection
Described switched-capacitor circuit comprise all have on, first to fourth electric capacity of bottom crown, wherein, first, the top crown of the second electric capacity is connected to the positive input terminal of described comparer, the 3rd, the top crown of the 4th electric capacity is connected to the negative input end of described comparer, first, the bottom crown of the 4th electric capacity is connected to respectively negative output terminal and the positive output end of described voltage reference circuit, and first, the capacitance of the 4th electric capacity equates, second, the bottom crown of the 3rd electric capacity is connected to respectively positive output end and the negative output terminal of described amplifier, and second, the capacitance of the 3rd electric capacity equates;
Described first, second clock signal is the non-overlapping clock signal of two-phase, when the first clock signal is high level, the sampling switch that the 3rd clock signal that described voltage reference circuit passes through to be inputted by the periphery is controlled is to the top crown output common mode level of described first to fourth electric capacity, and the negative edge of described the 3rd clock signal is with respect to negative edge t pre-set time of the first clock signal.
In above-mentioned single-chip latch type Hall sensor, the top crown of described first to fourth electric capacity is connected between described the first divider resistance and the second divider resistance by sampling switch.
In above-mentioned single-chip latch type Hall sensor, be connected with voltage buffer between described voltage reference circuit and the described sampling switch.
In above-mentioned single-chip latch type Hall sensor, the positive input terminal of described voltage buffer is connected between described the first divider resistance and the second divider resistance, and its negative input end and its output terminal are connected to described sampling switch.
In above-mentioned single-chip latch type Hall sensor, described voltage reference circuit comprises the temperature compensation module of connecting with described the first divider resistance.
In above-mentioned single-chip latch type Hall sensor, described temperature compensation module comprises the thermo-compensator with positive temperature coefficient (PTC).
In above-mentioned single-chip latch type Hall sensor, the scope of described time t is 100-1000 nanosecond.
Owing to adopted technique scheme, the present invention is by adopting novel switched electric capacity sampling, amplifying technique, make two groups of sampling capacitances, namely second, the 3rd electric capacity and first, the 4th electric capacity is sampled respectively through the reference voltage of the hall signal of amplifier amplification and voltage reference circuit output, and utilize charge conservation and charge redistribution principle to realize amplification and the fixedly elimination of offset voltage of hall signal, under the sample states of first to fourth electric capacity, introduce simultaneously special sampling time sequence, i.e. the 3rd clock signal, thus avoided sampling switch to switch the charge injection effect of moment and clock feed-through effect is set up precision on signal impact.The present invention has also added voltage buffer between voltage reference circuit and switched-capacitor circuit, that has avoided sampling switch switching moment generation kicks back noise to the impact of reference voltage.In addition, also set up temperature compensation module in the voltage reference circuit among the present invention, resnstance transformer by this positive temperature coefficient (PTC) the hysteresis voltage of sensor interval, so that the hysteresis voltage interval reduces with the rising of temperature, and then the Hall coefficient that has compensated the Hall pole plate reduces so that the Sensitivity Temperature of chip is floated effect with the effect that the rising of temperature reduces.
Description of drawings
Fig. 1 is the schematic diagram of the offset cancellation circuit of existing Hall element;
Fig. 2 is the structured flowchart of single-chip latch type Hall sensor of the present invention;
Fig. 3 is the sequential control synoptic diagram of Hall pole plate among the present invention;
Fig. 4 is the timing diagram of first, second clock signal among the present invention;
Fig. 5 is the fundamental diagram of Hall pole plate when the first clock signal is high level among the present invention;
Fig. 6 is the fundamental diagram of Hall pole plate when the second clock signal is high level among the present invention;
Fig. 7 is the structured flowchart of voltage reference circuit among the present invention;
Fig. 8 is the temperature compensation curve design sketch of voltage reference circuit among the present invention;
Fig. 9 is the structure principle chart of switched-capacitor circuit among the present invention;
Figure 10 is the timing diagram of second, third clock signal among the present invention;
Figure 11 is the fundamental diagram of switched-capacitor circuit when the first clock signal is high level among the present invention;
Figure 12 is the fundamental diagram of switched-capacitor circuit when the second clock signal is high level among the present invention.
Embodiment
The below provides preferred embodiment of the present invention and alternate embodiment, and is described in detail with reference to the accompanying drawings, enables to understand better function of the present invention, characteristics.
As shown in Figure 2, the present invention, be a kind of single-chip latch type Hall sensor, comprise mu balanced circuit 1, voltage reference circuit 2, voltage buffer 3, Hall pole plate 4, amplifier 5, switched-capacitor circuit 6, comparer 7, oscillator 8, Digital Logic control circuit 9 and output power pipe 10.
The voltage transitions that mu balanced circuit 1 is used for external power source 11 is internal electric source V
REGVoltage, and respectively to voltage reference circuit 2, voltage buffer 3, Hall pole plate 4, amplifier 5, comparer 7, oscillator 8 and 9 power supplies of Digital Logic control circuit, this internal electric source V
REGVoltage be not subjected to the impact of applications environment, have lower noise and higher stability, and when externally the voltage of power supply 11 changes in the scope of 6V～30V, maintain about 5V all the time.
As shown in Figure 3, four lead-out terminal A, B, C and D of Hall pole plate 4 link to each other with the positive and negative input end of amplifier 5 respectively by the sequence switch that first, second clock signal C KP, CKN by the periphery input control, wherein, first, second clock signal C KP, CKN are the non-overlapping clock signal of two-phase, and their sequential relationship can be as shown in Figure 4.
Suppose to have fixedly offset voltage V on the Hall pole plate 4
OS_H, amplifier 5 has fixedly offset voltage V
OS_A, amplifier 5 is used for amplifying the hall signal V of Hall pole plate 4 outputs
HALLWith fixing offset voltage V
OS_H, V
OS_A, and to switched-capacitor circuit 6 output signal V
AMP_P, V
AMP_N
As shown in Figure 5, when the first clock signal C KP is high level, when second clock signal CKN was low level, the direction of current in the Hall pole plate 4 was for to flow to lead-out terminal C from lead-out terminal A, generation hall signal V between lead-out terminal B, the D
HALL, and lead-out terminal B is connected with the positive input terminal of amplifier 5, and lead-out terminal D is connected with the negative input end of amplifier 5; According to left-hand rule, this moment amplifier 5 output signal V
AMP_P_1, V
AMP_N_1Satisfy:
V
AMP_P_1-V
AMP_N_1＝-A
VHALL-A(V
OS_H+V
OS_A) (1)，
In the formula, A is the gain of amplifier 5.
As shown in Figure 6, when the first clock signal C KP is low level, when second clock signal CKN was high level, the direction of current in the Hall pole plate 4 was for to flow to lead-out terminal B from lead-out terminal D, generation hall signal V between lead-out terminal A, the C
HALL, and lead-out terminal A is connected with the negative input end of amplifier 5, and lead-out terminal C is connected with the positive input terminal of amplifier 5; According to left-hand rule, this moment amplifier 5 output signal V
AMP_P_2, V
AMP_N_2Satisfy:
V
AMP_P_2-V
AMP_N_2＝A
VHALL-A(V
OS_H+V
OS_A) (2)。
As shown in Figure 7, voltage reference circuit 2 comprises and is connected on successively internal electric source V
REGAnd the temperature compensation module between the ground 21, the first divider resistance R
1With the second divider resistance R
2, wherein, temperature compensation module 21 adopts the thermo-compensator R with positive temperature coefficient (PTC)
TEMP, it specifically acts on hereinafter and introduces.
By thermo-compensator R
TEMP, the first divider resistance R
1With the second divider resistance R
2The dividing potential drop effect obtain first, second reference voltage V
F1, V
F2, this first, second reference voltage V
F1, V
F2By two groups of sequence switch control gatings, wherein, one group of sequence switch is by first, second clock signal C KP, CKN control, and another group sequence switch is by logical signal C
F_P, C
F_NControl, this logical signal C
F_P, C
F_NBy the output signal V of Digital Logic control circuit 9 according to comparer 7
CMPAnd produce.The first reference voltage V
F1By after the sequence switch control as the output signal V of the positive output end of voltage reference circuit 2
RP, the second reference voltage V
F2By after the sequence switch control as the output signal V of the negative output terminal of voltage reference circuit 2
RN
As shown in Figure 9, the output signal V of 6 pairs of amplifiers 5 of switched-capacitor circuit
AMP_P, V
AMP_NCarry out amplifier, and utilize Correlated Double Sampling disappear the fixedly offset voltage V of Hall pole plate 4 and amplifier 5
OS_H, V
OS_ASpecifically, switched-capacitor circuit 6 comprises first to fourth capacitor C that all has upper and lower pole plate
1To C
4, wherein:
First, second capacitor C
1, C
2Top crown be connected to the positive input terminal of comparer 7, the 3rd, the 4th capacitor C
3, C
4Top crown be connected to the negative input end of comparer 7, thereby make comparer 7 at the clock amplification stage to first to fourth capacitor C
1To C
4On voltage compare;
The first, the 4th capacitor C
1, C
4Bottom crown be connected to respectively negative output terminal and the positive output end of voltage reference circuit 2, be used for the sampling reference voltage signal, i.e. the output signal V of receiver voltage reference circuit 2 respectively
RN, V
RP, and the first, the 4th capacitor C
1, C
4Capacitance equate, thereby avoid signal imbalance (this is that characteristic by difference channel determines) in amplification process, can occur;
Second, third capacitor C
2, C
3Bottom crown be connected to respectively positive output end and the negative output terminal of amplifier 5, be used for the output signal of sampling amplifier 5, i.e. the output signal V of reception amplifier 5 respectively
AMP_P, V
AMP_N, and second, third capacitor C
2, C
3Capacitance equate, thereby avoid signal in amplification process, imbalance can occur.
First to fourth capacitor C
1To C
4Top crown also be connected to the first divider resistance R by the sampling switch by the 3rd clock signal C KP_C control of periphery input
1With the second divider resistance R
2Between, namely be subjected to the 3rd clock signal C KP_C control ground to receive the second reference voltage V
F2, this second reference voltage V
F2Be common mode electrical level, be used to switched-capacitor circuit 6 to provide dc point in sample phase; The negative edge of the 3rd clock signal C KP_C is with respect to negative edge t pre-set time of the first clock signal C KP, and the scope of time t is 100-1000 nanosecond; In the present embodiment, the quantity of sampling switch is two, is connected to first, second capacitor C
1, C
2Top crown and the 3rd, the 4th capacitor C
3, C
4Top crown.
In the present embodiment, voltage buffer 3 is connected between voltage reference circuit 2 and the above-mentioned sampling switch, and specifically, the positive input terminal of voltage buffer 3 is connected to the first divider resistance R
1With the second divider resistance R
2Between, its negative input end and its output terminal are connected to sampling switch.Because the isolation of voltage buffer is arranged, and the change action of sampling switch can not be directly coupled in the voltage reference circuit 2, therefore can be to first, second reference voltage V
F1, V
F2Exert an influence.
When the first clock signal C KP is high level, the common mode electrical level that voltage reference circuit 2 produces, i.e. the second reference voltage V
F2Be sent to first to fourth capacitor C by voltage buffer 3 and by the 3rd clock signal C KP_C with controlling
1To C
4Top crown.
Because the negative edge of the 3rd clock signal C KP_C has certain hour t in advance (sequential relationship is as shown in figure 10) with respect to the negative edge of the first clock signal C KP, therefore, when the first clock signal C KP when negative edge switches, because first to fourth capacitor C
1To C
4Top crown be in advance vacant state, do not enter the output signal V of the positive and negative output terminal of voltage reference circuit 2 thereby do not have electric charge
RP, V
RNVoltage dithering will can not affect first to fourth capacitor C
1To C
4Sampling precision; And the charge injection of introducing when switching for the negative edge of the 3rd clock signal C KP_C, because the circuit that connects of the positive and negative input end of comparer 7 is full symmetrics, therefore, this charge injection can not exert an influence to the differential input signal of comparer 7.
Specifically, the working method of switched-capacitor circuit 6 is as follows:
Suppose among Fig. 7 the logical signal C that Digital Logic control circuit 9 produces
F_PBe high level, logical signal C
F_NBe low level, then when the first clock signal C KP is high level (this moment second clock signal CKN be low level), the real work circuit of switched-capacitor circuit 6 as shown in figure 11, at this moment, first, second capacitor C
1, C
2On total electrical charge Q
1Satisfy:
Q
1＝(V
F1-V
F2)C
1+(V
AMP_P_1-V
F2)C
2 (3)；
Three, the 4th capacitor C
3, C
4On total electrical charge Q
2Satisfy:
Q
2＝(V
F2-V
F2)C
4+(V
AMP_N_1-V
F2)C
3 (4)。
And when second clock signal CKN is high level (this moment the first clock signal C KP be low level), the real work circuit of switched-capacitor circuit 6 as shown in figure 12, at this moment, first, second capacitor C
1, C
2On total electrical charge Q
1' satisfy:
Q
1’＝(V
F2-V
CMP_P)C
1+(V
AMP_P_2-V
CMP_P)C
2 (5)，
In the formula, V
CMP_PInput signal for the positive input terminal of comparer 7;
Three, the 4th capacitor C
3, C
4On total electrical charge Q
2' satisfy:
Q
2’＝(V
F1-V
CMP_N)C
4+(V
AMP_N_2-V
CMP_N)C
3 (6)，
In the formula, V
CMP_NInput signal for the negative input end of comparer 7.
Because principle of charge conservation total electrical charge Q
1=Q
1', total electrical charge Q
2=Q
2', and the first, the 4th capacitor C
1, C
4Capacitance equate i.e. C
1=C
4, second, third capacitor C
2, C
3Capacitance equate i.e. C
2=C
3, therefore, convolution (1), formula (2) can be extrapolated, and this moment, the difference input voltage of comparer 7 was:
V
CMP_P-V
CMP_N＝2C
2A
VHALL/(C
1+C
2)-2C
1(V
F1-V
F2)/(C
1+C
2) (7)。
By that analogy, the logical signal C that produces when Digital Logic control circuit 9
F_PBe low level, logical signal C
F_NDuring for high level, the difference input voltage of comparer 7 is:
V
CMP_P-V
CMP_N＝2C
2A
VHALL/(C
1+C
2)+2C
1(V
F1-V
F2)/(C
1+C
2) (8)。
Can be found out that by formula (7), (8) direct current of Hall pole plate 4 and amplifier 5 is offset voltage V fixedly
OS_H, V
OS_AEliminate; Between the stagnant regions of circuit by 2C1 (V
F1-V
F2)/(C
1+ C
2) determine that sluggish polarity is by logical signal C
F_PLevel just control; Hall signal V
HALLEnlargement factor be 2C
2A/ (C
1+ C
2).
When temperature raises, Hall pole plate 4 sensitivities, the induced voltage that the magnetic field of unit strength produces reduces, so must reduce between electric stagnant regions when temperature raises, just can make between the magnetic stagnant regions constant.And when temperature raises, thermo-compensator R
TEMPResistance value can increase, thereby so that the dividing potential drop branch current in the voltage reference circuit 2 reduces, and then reduce first, second reference voltage V
F1, V
F2Voltage difference V
F1-V
F2, since the stagnant regions of circuit between mainly by V
F1-V
F2Difference provide, this shows thermo-compensator R
TEMPCan make that variation with temperature reduces between stagnant regions, thereby reach the purpose of temperature compensation, first, second reference voltage V
F1, V
F2The voltage difference variation with temperature as shown in Figure 8.
In addition, the oscillator 8 in the present embodiment produces the required basic clock signal of whole sensor chip, and this clock signal is sent into Digital Logic control circuit 9; Digital Logic control circuit 9 is also according to the output signal V of comparer 7
CMPThe on off state of control output power pipe 10; Output power pipe 10 is used for the state of control sensor chip external fan coil.
Obviously, in the above teachings, may carry out multiple correction and modification to the present invention, and within the scope of the appended claims, the present invention can be embodied as the specifically described mode that is different from.
Claims (7)
1. single-chip latch type Hall sensor, it comprises Hall pole plate, amplifier, switched-capacitor circuit and the comparer that connects successively, also comprise the voltage reference circuit that is connected with described switched-capacitor circuit, wherein, described Hall pole plate is by first, second clock signal control of periphery input, described voltage reference circuit comprises the first divider resistance and second divider resistance of series connection, it is characterized in that
Described switched-capacitor circuit comprise all have on, first to fourth electric capacity of bottom crown, wherein, first, the top crown of the second electric capacity is connected to the positive input terminal of described comparer, the 3rd, the top crown of the 4th electric capacity is connected to the negative input end of described comparer, first, the bottom crown of the 4th electric capacity is connected to respectively negative output terminal and the positive output end of described voltage reference circuit, and first, the capacitance of the 4th electric capacity equates, second, the bottom crown of the 3rd electric capacity is connected to respectively positive output end and the negative output terminal of described amplifier, and second, the capacitance of the 3rd electric capacity equates;
Described first, second clock signal is the non-overlapping clock signal of two-phase, when the first clock signal is high level, the sampling switch that the 3rd clock signal that described voltage reference circuit passes through to be inputted by the periphery is controlled is to the top crown output common mode level of described first to fourth electric capacity, and the negative edge of described the 3rd clock signal is with respect to negative edge t pre-set time of the first clock signal.
2. single-chip latch type Hall sensor as claimed in claim 1 is characterized in that, the top crown of described first to fourth electric capacity is connected between described the first divider resistance and the second divider resistance by sampling switch.
3. single-chip latch type Hall sensor as claimed in claim 1 or 2 is characterized in that, is connected with voltage buffer between described voltage reference circuit and the described sampling switch.
4. single-chip latch type Hall sensor as claimed in claim 3 is characterized in that, the positive input terminal of described voltage buffer is connected between described the first divider resistance and the second divider resistance, and its negative input end and its output terminal are connected to described sampling switch.
5. single-chip latch type Hall sensor as claimed in claim 3 is characterized in that, described voltage reference circuit comprises the temperature compensation module of connecting with described the first divider resistance.
6. single-chip latch type Hall sensor as claimed in claim 5 is characterized in that, described temperature compensation module comprises the thermo-compensator with positive temperature coefficient (PTC).
7. single-chip latch type Hall sensor as claimed in claim 1 is characterized in that, the scope of described time t is 100-1000 nanosecond.
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| CN103326702A (en) * | 2013-05-31 | 2013-09-25 | 北京经纬恒润科技有限公司 | Hall switch circuit |
| CN105807832A (en) * | 2014-12-30 | 2016-07-27 | 中国科学院深圳先进技术研究院 | Standard voltage stabilizing circuit |
| CN107356890A (en) * | 2017-06-19 | 2017-11-17 | 宁波中车时代传感技术有限公司 | The adjustable proframmable linear Hall sensor chip of benchmark |
| CN109698687A (en) * | 2019-02-25 | 2019-04-30 | 成都芯进电子有限公司 | A kind of magnetic signal detection sequential control circuit and control method |
| CN109765828A (en) * | 2019-02-25 | 2019-05-17 | 成都芯进电子有限公司 | A kind of reluctance type sensors chip sequential control circuit and control method |
| CN113114120A (en) * | 2021-04-12 | 2021-07-13 | 上海传泰电子科技有限公司 | Hall sensor signal processing circuit |
| CN113551589A (en) * | 2021-01-06 | 2021-10-26 | 南京能晶电子科技有限公司 | Angle sensor chip based on Hall device and use method thereof |
| CN114323083A (en) * | 2021-12-17 | 2022-04-12 | 上海艾为电子技术股份有限公司 | Hall sensing device and electronic equipment |
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| CN103326702A (en) * | 2013-05-31 | 2013-09-25 | 北京经纬恒润科技有限公司 | Hall switch circuit |
| CN103326702B (en) * | 2013-05-31 | 2015-11-11 | 北京经纬恒润科技有限公司 | A kind of Hall switch circuit |
| CN105807832A (en) * | 2014-12-30 | 2016-07-27 | 中国科学院深圳先进技术研究院 | Standard voltage stabilizing circuit |
| CN105807832B (en) * | 2014-12-30 | 2017-08-11 | 中国科学院深圳先进技术研究院 | Reference voltage-stabilizing circuit |
| CN107356890A (en) * | 2017-06-19 | 2017-11-17 | 宁波中车时代传感技术有限公司 | The adjustable proframmable linear Hall sensor chip of benchmark |
| CN109698687A (en) * | 2019-02-25 | 2019-04-30 | 成都芯进电子有限公司 | A kind of magnetic signal detection sequential control circuit and control method |
| CN109765828A (en) * | 2019-02-25 | 2019-05-17 | 成都芯进电子有限公司 | A kind of reluctance type sensors chip sequential control circuit and control method |
| CN109698687B (en) * | 2019-02-25 | 2023-08-15 | 成都芯进电子有限公司 | Magnetic signal detection time sequence control circuit and control method |
| CN109765828B (en) * | 2019-02-25 | 2023-08-25 | 成都芯进电子有限公司 | Magnetic resistance type sensor chip time sequence control circuit and control method |
| CN113551589A (en) * | 2021-01-06 | 2021-10-26 | 南京能晶电子科技有限公司 | Angle sensor chip based on Hall device and use method thereof |
| CN113114120A (en) * | 2021-04-12 | 2021-07-13 | 上海传泰电子科技有限公司 | Hall sensor signal processing circuit |
| CN114323083A (en) * | 2021-12-17 | 2022-04-12 | 上海艾为电子技术股份有限公司 | Hall sensing device and electronic equipment |
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Application publication date: 20130424 |