CN103051530A

CN103051530A - Method for optimizing multiple-network-interface transmission of message of intelligent substation

Info

Publication number: CN103051530A
Application number: CN2012105741006A
Authority: CN
Inventors: 杨志涛; 胡炯; 徐刚; 徐万方; 周涛; 刘涛
Original assignee: Beijing Sifang Automation Co Ltd
Current assignee: Beijing Sifang Automation Co Ltd; Beijing Sifang Engineering Co Ltd
Priority date: 2012-12-26
Filing date: 2012-12-26
Publication date: 2013-04-17
Anticipated expiration: 2032-12-26
Also published as: CN103051530B

Abstract

The invention relates to a method for optimizing multiple-network-interface transmission of a message of an intelligent substation. The method comprises the following steps: configuring a source MAC (media access control) address of each network interface to an FPGA (field programmable gate array) and preparing to transmit an Ethernet message which is a multi-packet message, wherein each packet of the message comprises a message packet head, message data and a message packet tail; generating an MAC effective zone bit by a CPU (central processing unit); transmitting the MAC effective zone bit, the message head, the message data and the message packet tail to the FPGA sequentially; unpacking the packet message by the FPGA; transmitting the message data of the MAC effective label to an MAC source address processing module of a corresponding MAC according to the analyzed MAC effect zone bit; and after inserting an source MAC address of the MAC in the message data to be transmitted through the MAC source address processing module, transmitting by the FPGA. The method for optimizing the multiple-network-interface transmission of the message of the intelligent substation, disclosed by the invention, has the advantages of improving the transmission efficiency of an interface, reducing the development difficulty of the CPU and reducing the received data quantity of the PFGA.

Description

A kind of Multi-netmouth for the intelligent substation message sends optimization method

Technical field

The invention belongs to technical field of power systems, relate to a kind of intelligent terminal, specially refer to the terminal equipment of intelligent substation.

Background technology

Along with development and the progress of transformer station's technology, more and more coming into one's own of intelligent substation progressively becoming the main flow direction of technical development at present.Wherein the web development speed of the digitlization of the primary equipment of transformer station and secondary device is very fast, and these all are the technological innovations that the application of digitizing technique brings.Digitizing technique can be with the employing Data Digital of process layer, information digitalization that transmits between the equipment etc., and these digitlizations improve monitoring and the management that is conducive to equipment state and network state in the intelligent substation, have promoted the reliability of substation equipment.

In intelligent substation, some digital device need to be managed a plurality of network interfaces simultaneously because design requirement, Digital Master Unit for example, and relaying protection computing equipment etc., its structure generally adopts more common CPU and FPGA architecture design as shown in Figure 1.In this equipment, CPU often sends form as shown in Figure 2 for the Ethernet message that different physical internet ports send.CPU need to wrap at each respectively and treat that an initial data front adds ethernet packet header, and the back adds the information such as Ethernet bag tail and verification, forms the complete message that meets Ethernet protocol.And for the message of different network interfaces, the packet header that CPU adds and bag tail also are different.Then, according to the communication protocol between FPGA and the CPU, by data/address bus whole packed whole messages are sent to FPGA by CPU, be responsible for forwarding work by FPGA.

When all management network ports or part network interface wait to send out initial data identical the time, be one group of identical initial data, in the time of need to sending to a plurality of network interface, the CPU of traditional method also need to be according to operation as above, identical data are added different packet header and bag tail, and then send to FPGA.This way is equivalent to that initial data is sent out in identical waiting and repeats to have sent multipass, has greatly wasted communication bus bandwidth between CPU and the FPGA, has reduced efficiency of transmission.

Summary of the invention

The object of the invention is to solve when CPU sends identical message content to different network interfaces, improve the bus efficiency between CPU and the FPGA, avoid sending repeating data.

In order to overcome the above problems, the present invention specifically by the following technical solutions:

A kind of Multi-netmouth for the intelligent substation message sends optimization method, the hardware structure that described intelligent substation ethernet communication adopts CPU and FPGA to jointly control, and wherein, CPU mainly does data and processes, and FPGA is responsible for interface operation and transceiving data; It is characterized in that, said method comprising the steps of:

(1) CPU is with the source MAC(MediaAccess Control of each network interface, i.e. media access control layer) address configuration is to FPGA;

(2) CPU prepares to wait to send out the Ethernet message, and described Ethernet message is multipacket message, and each packet voice comprises message packet header, message data, message bag tail;

(3) CPU generates MAC effective marker position, and MAC effective marker position is the data of a plurality of bytes, the corresponding MAC of its each byte, if this bit value is ' 1 ', expression MAC effective marker position is effective, needs to wrap data and sends to corresponding MAC; Otherwise, represent that then MAC effective marker position is invalid, do not need these bag data are sent to corresponding MAC;

(4) CPU is MAC effective marker position, message packet header, message data, and message bag tail sends to FPGA in order;

(5) after FPGA receives the packet voice with MAC effective marker position of CPU transmission, unpack, parse MAC effective marker position, packet header, message data, the bag tail of packet voice;

(6) FPGA inquires about the byte in the corresponding MAC effective marker of each MAC position according to the MAC effective marker position that parses, if the numerical value in this byte is ' 1 ', then this message data is changed over to the source MAC processing module of the corresponding MAC among the FPGA;

(7) the mac source address processing module is inserted the source MAC of this MAC in the civilian data of waiting to transmit messages;

(8) FPGA sends the MAC flag bit effectively and inserts the message data of corresponding source MAC.

According to aforesaid operations, identical but need to send to the message of a plurality of network interfaces for message content, only need to increase data seldom, expression target network interface sign just can successfully have been avoided the transmission that repeats of identical data.If message content does not need to repeat to send, only need the bit that guarantees corresponding MAC in the MAC effective marker position effectively to get final product, can not increase any unnecessary expense, guaranteed the reliability that sends.So the present invention has flexibility for the management that the Multi-netmouth message sends, can support the independence that message sends, when simultaneously having taken into account again identical message and sending to Multi-netmouth simultaneously, the high efficiency of avoiding identical data to repeat to send is conducive to the expansion demand of program.

The present invention has following beneficial effect:

Save the repeating data transmission between a large amount of CPU and the FPGA, improved interface transmission efficiency;

Simplify Multi-netmouth for identical Ethernet message process of transmitting, reduced the CPU development difficulty;

Save the process that CPU repeats to carry identical data, improved to a certain extent the operational efficiency of CPU;

FPGA avoids receiving identical data, only needs the data/address bus copy data to get final product, and has reduced the receive data difficulty of FPGA;

The Multi-netmouth Data Stream Processing has been simplified the development process of FPGA.

Description of drawings

Fig. 1 is intelligent substation intelligent terminal ethernet communication configuration diagram;

Fig. 2 is that CPU sends form for the Ethernet message that different physical internet ports send in the prior art;

Fig. 3 is the Multi-netmouth transmission optimization method flow chart that the present invention is used for intelligent substation;

Fig. 4 is that the Ethernet message that the present invention adopts sends form.

Embodiment

Below in conjunction with Figure of description, technical scheme of the present invention is described in further details.

As shown in Figure 3, the application discloses a kind of Multi-netmouth for the intelligent substation message and has sent optimization method, the hardware structure (as shown in Figure 1) that described intelligent substation ethernet communication adopts CPU and FPGA to jointly control, CPU is responsible for controlling and waits to send out multipacket message, then send to FPGA, after FPGA receives message data, parse the affiliated MAC port of every packet voice, then different messages is distributed to different MAC port, wherein, CPU mainly does data and processes, and FPGA is responsible for interface operation and transceiving data; Said method comprising the steps of:

(1) CPU disposes the source MAC of each network interface to FPGA;

Comprise source MAC in the Ethernet message, in the Multi-netmouth management equipment, the source MAC of each network interface is fixing but different, the source MAC of each network interface is then determined by CPU, and the source MAC of each MAC, then by FPGA with the fixing source MAC that sets before the CPU, be inserted in the relevant position of data flow.

(2) CPU prepares to wait to send out the Ethernet message, generally all is to prepare multipacket message, and each packet voice comprises message packet header, message data, message bag tail;

(3) CPU generates MAC effective marker position;

Generate principle: MAC effective marker position is the data of N bit, the corresponding MAC of its each bit, if this bit numerical value is ' 1 ', expression effectively needs to wrap data and sends to corresponding MAC; Otherwise, then invalid; CPU only need to arrange MAC effective marker position corresponding to every packet voice, and MAC effective marker position and data sent to FPGA together, be arranged to ' 1 ' by FPGA according to concrete which bit of this flag bit, go distribution, if a plurality of bit have been configured to ' 1 ', then can will should arrive a plurality of MAC by the bag Data dissemination;

(4) CPU is MAC effective marker position, message packet header, and message data, message bag tail sends to FPGA, as shown in Figure 4 in order;

The present patent application people has done detailed explanation and description in conjunction with Figure of description to embodiments of the invention; but those skilled in the art should understand that; above embodiment only is the preferred embodiments of the invention; detailed explanation is just in order to help the reader to understand better spirit of the present invention; and be not limiting the scope of the invention; on the contrary, any any improvement or modification of doing based on invention spirit of the present invention all should drop within protection scope of the present invention.

Claims

1. a Multi-netmouth that is used for the intelligent substation message sends optimization method, the hardware structure that described intelligent substation ethernet communication adopts CPU and FPGA to jointly control, and wherein, CPU mainly does data and processes, and FPGA is responsible for interface operation and transceiving data; It is characterized in that, said method comprising the steps of:

(1) CPU is with the source MAC(Media Access Control of each network interface, i.e. media access control layer) address configuration is to FPGA;