CN103018974B - Liquid crystal indicator, polysilicon array base palte and preparation method - Google Patents
Liquid crystal indicator, polysilicon array base palte and preparation method Download PDFInfo
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- CN103018974B CN103018974B CN201210505247.XA CN201210505247A CN103018974B CN 103018974 B CN103018974 B CN 103018974B CN 201210505247 A CN201210505247 A CN 201210505247A CN 103018974 B CN103018974 B CN 103018974B
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Abstract
The embodiment of the invention discloses liquid crystal indicator, polysilicon array base palte and preparation method, relate to field of liquid crystal display, simplify the interlayer structure of array base palte and the production technology of array base palte. Embodiment of the present invention polysilicon array base palte comprises multi-crystal TFT, also comprise: with same layer of pixel electrode arranging of active layer of multi-crystal TFT, same layer of public electrode arranging of grid with multi-crystal TFT, public electrode and pixel electrode are oppositely arranged, and the electrode that is positioned at top in public electrode and pixel electrode is slit-shaped electrode.
Description
Technical field
The present invention relates to field of liquid crystal display, relate in particular to a kind of liquid crystal indicator, polysiliconArray base palte and preparation method.
Background technology
In recent years, along with the application of liquid crystal display product is more and more extensive, lcd technology alsoMore and more perfect. TFT-LCD (ThinFilmTransistor-LiquidCrystalDisplay, thinFilm field-effect transistor-liquid crystal display) with image demonstration, low energy consumption, the environmental protection of its high-qualityEtc. advantage in demonstration field in occupation of critical positions very.
As a kind of novel manufacturing process of TFT-LCD, LTPS (LowTemperaturePoly-Silicon, low temperature polycrystalline silicon) technology utilizes quasi-molecule laser annealing technique by non-crystalline silicon(a-Si) thin layer changes polysilicon (Poly-Si) thin layer into. Compare amorphous silicon material, manyThe electron mobility of crystal silicon material has 100 times of above increases, therefore uses LTPS technology to makeTFT-LCD has the response time faster, has higher resolution ratio, better picture displyQuality. Use in addition LTPS technology, can reduce IC, simplification display unitPeriphery, realizes narrow frame technology.
As the another kind of novel manufacturing process of TFT-LCD, ADS (AdvancedSuperDimensionSwitch, senior super dimension field switch) technology utilizes gap electrode layer in same planeFringe field and the electric field of gap electrode layer and plate electrode interlayer produce and form multidimensional electricity, the liquid crystal molecule of all orientations between gap electrode and directly over electrode can both be produced and revolveTurn, thereby improved liquid crystal operating efficiency and increased light transmission efficiency.
In conjunction with above-mentioned two kinds of manufacturing process, the array base-plate structure of prior art LTPS is as Fig. 1Shown in, comprising: substrate 1 and be set in turn in cushion 2 on substrate 1, active layer 3,Gate insulator 5, gate electrode 7, interlayer insulating film 9, source electrode 10 and drain electrode 11,The via hole 114, connecting electrode 115, the public electrode that on organic layer 113, organic layer 113, arrange6, passivation layer 12, pixel electrode 4. The manufacture craft order of above-mentioned LTPS array base palte is comparatively multipleAssorted, need at least 10 composition techniques, therefore the cost of manufacture of whole display floater is higher.
Summary of the invention
Embodiments of the invention provide a kind of liquid crystal indicator, polysilicon array base palte and makingMethod, simplifies the interlayer structure of array base palte and the production technology of array base palte.
For solving the problems of the technologies described above, embodiments of the invention adopt following technical scheme:
The invention provides a kind of polysilicon array base palte, comprise multi-crystal TFT, also comprise:With same layer of pixel electrode arranging of active layer of described multi-crystal TFT, with described multi-crystal TFTGrid with layer arrange a public electrode, described public electrode and described pixel electrode are oppositely arranged,The electrode that is positioned at top in described public electrode and pixel electrode is slit-shaped electrode.
Further, described multi-crystal TFT is top gate type TFT, and described public electrode is slitShape electrode.
Further, described multi-crystal TFT is bottom gate type TFT, and described pixel electrode is slitShape electrode.
Preferably, above or below described public electrode, be provided with described common electrode contactPublic electrode wire.
Preferably, the thickness of described source electrode and described drain electrode is
On the other hand, the present invention also provides a kind of liquid crystal indicator, comprises above-mentioned array basePlate.
On the one hand, the present invention also provides a kind of preparation method of array base palte, comprising again:
Form polysilicon active layer and pixel electrode;
Form gate insulator;
Form grid and public electrode;
Form active layer doped region;
Hole, hole and pixel electrode via hole for drain electrode for the electrode of formation source;
Formation source electrode and drain electrode, described drain electrode and described pixel electrode are by described pixelElectrode via hole is connected.
Further, the preparation method of array base palte, is also included on described substrate and forms and cushionLayer.
Further, the preparation method of array base palte also comprises: described public electrode top or underSide is provided with the public electrode wire with described common electrode contact.
Further, after forming described source electrode and described drain electrode, also comprise: formPassivation layer, forms peripheral connecting hole by a composition technique.
Liquid crystal indicator, polysilicon array base palte and the preparation method of the embodiment of the present invention, logicalCross the interlayer position of adjusting the interior pixel electrode of polysilicon array base palte and public electrode, saved existingThere are organic layer and via structure in technology, simplified the interlayer structure of array base palte, simplified arrayThe production technology of substrate, has reduced cost of manufacture. In addition, public electrode and pixel electrode are positioned atSide's electrode is slit-shaped electrode, and the generation multi-dimensional electric field that makes to cooperatively interact between electrode, has improved arrayThe display effect of substrate.
Brief description of the drawings
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, belowThe accompanying drawing of required use during embodiment is described is briefly described, apparently, belowAccompanying drawing in description is only some embodiments of the present invention, comes for those of ordinary skill in the artSay, do not paying under the prerequisite of creative work, can also obtain the attached of other according to these accompanying drawingsFigure.
Fig. 1 is one of structural representation of prior art array base palte.
Fig. 2 a-2g is the array base palte decomposition texture schematic diagram of a kind of specific embodiment of the present invention, itsIn, Fig. 2 g is the final structure schematic diagram of this embodiment array base palte.
Fig. 3 a-3f is the array base palte decomposition texture schematic diagram of the another kind of specific embodiment of the present invention,Wherein, Fig. 3 f is the final structure schematic diagram of this embodiment array base palte.
Fig. 4 is one of schematic flow sheet of array base palte manufacture craft in the embodiment of the present invention.
Fig. 5 be array base palte manufacture craft in the embodiment of the present invention schematic flow sheet two.
Detailed description of the invention
The embodiment of the present invention provides a kind of liquid crystal indicator, polysilicon array base palte and makingMethod, in order to have simplified the interlayer structure of array base palte, has overcome array base palte life in prior artThe defect that production. art is comparatively complicated.
In below describing, in order to illustrate instead of in order limiting, to have proposed to tie such as particular systemThe detail of structure, interface, technology and so on, understands the present invention to thoroughly cut. But, this areaTechnical staff should be clear, in other embodiment that there is no these details, also can realizeThe present invention. In other situation, omission is detailed to well-known device, circuit and methodIllustrate, in order to avoid unnecessary details hinders description of the invention.
Below in conjunction with following accompanying drawing, the embodiment of the present invention is described in detail.
The present embodiment provides a kind of polysilicon array base palte, as Fig. 2 g or as shown in Fig. 3 f, and shouldArray base palte comprises: with same layer of pixel electrode 4 arranging of active layer 3 of multi-crystal TFT, with manyThe public electrode 6 that the grid 7 of crystal silicon TFT arranges with layer, wherein, public electrode 6 and pixel electricityThe utmost point 4 is oppositely arranged, and the electrode that is positioned at top in public electrode 6 and pixel electrode 4 is slit-shaped electricityThe utmost point.
Further, multi-crystal TFT is top gate type TFT, and public electrode is slit-shaped electrode.As a kind of detailed description of the invention of the present invention, top gate type TFT polysilicon array base palte, as figureShown in 2g: substrate 1 and be set in turn in cushion 2 on substrate 1, active layer 3, with havePixel electrode 4, gate insulator 5, public electrode 6 and public electrode that source layer 3 arranges with layer6 gate electrodes 7, public electrode wire 8, interlayer insulating film 9, source electrode 10 that arrange with layer andDrain electrode 11. Wherein, gate electrode 7 is positioned at the top of active layer 3, and public electrode 6 is positioned at pixelThe top of electrode 4, public electrode 6 is slit-shaped electrode, is provided with pixel electricity on pixel electrode 4Utmost point via hole, pixel electrode 4 is connected with drain electrode 11 by pixel electrode via hole. With the public affairs of slitCommon electrode 6 can produce multi-dimensional electric field with pixel electrode 4, utilizes multi-dimensional electric field to show in order to increaseThe visual angle of device.
Further, multi-crystal TFT is bottom gate type TFT, and pixel electrode is slit-shaped electrode.As another kind of detailed description of the invention of the present invention, bottom gate type TFT polysilicon array base palte, as figureShown in 3g, the top gate type TFT polysilicon array base palte in its structure and above-mentioned detailed description of the inventionStructure similar. Difference is wherein, in bottom gate type TFT polysilicon array base palte, and gridElectrode 7 is positioned at the below of active layer 3, and pixel electrode 4 is positioned at the top of public electrode 6, pixelElectrode 4 is slit-shaped electrode. Pixel electrode 4 with slit can produce multidimensional with public electrode 6Electric field, utilizes multi-dimensional electric field in order to increase the visual angle of display unit.
The polysilicon array base palte of the embodiment of the present invention, looks like by adjusting in polysilicon array base palteThe interlayer position of element electrode and public electrode, has saved organic layer of the prior art and via hole knotStructure, has simplified the interlayer structure of array base palte, has simplified the production technology of array base palte, has reducedCost of manufacture. In addition, it is slit-shaped electrode that public electrode and pixel electrode are positioned at upper electrode, makesThe generation multi-dimensional electric field that cooperatively interacts between electrode, improved the display effect of array base palte.
Further, above or below public electrode 6, be provided with described common electrode contactPublic electrode wire 8, public electrode wire 8 is in order to transmit public electrode 6 signals, certain, common electricalPolar curve 8 can according to circumstances arrange, can judge according to load signal the opportunity of use,Such as in the time that the size of liquid crystal indicator is larger, common electrode signal can arrange weak timePublic electrode wire 8. Can meet normally making of display unit and work as array base palte common electrode signalUsed time, public electrode wire 8 structures can be saved, in order to opening of further increase array base palteMouth rate.
Preferably, the thickness of source electrode 10 and drain electrode 11 is
The public electrode 6 of the embodiment of the present invention, preferred, employing ITO (IndiumTinOxides,Indium tin oxide) or IZO (IndiumZincOxides, indium-zinc oxide) material make.
The source electrode 10 of the embodiment of the present invention and drain electrode 11, preferred, employing Mo, Al,Any one or a few in Ti, Al-Nd (molybdenum, aluminium, titanium, aluminium neodymium alloy) material arbitrarilyCombination is made.
It should be noted that, active layer 3 in the array base palte of the embodiment of the present invention, as Fig. 2 g orAs shown in Fig. 3 f. The manufacturing process of active layer 3 can be described below: first deposit one deck non-crystalline siliconMaterial, then utilizes LTPS technology, by quasi-molecule annealing process, non-crystalline silicon is transformed into polycrystallineSilicon, then adulterates to form and mix respectively to this active layer 3 by composition technique and doping processAssorted region 101 and lightly doped region 102. The array base palte source electrode 10 of the embodiment of the present invention and leakageElectrode 11 is connected by the active layer 3 that is formed with doped region 101 and lightly doped region 102,Active layer 3 provides conductive channel for source electrode 10 and drain electrode 11, and the conducting of active layer 3 orPerson disconnects and controlling by controlling voltage in gate electrode 7. The doped region 101 and the light doping section that formThe electrology characteristic of active layer 3 can be improved in territory 102, for example, can suppress the phenomenons such as leakage current and produceAdverse effect.
In addition, the polysilicon array base palte of the embodiment of the present invention can also comprise passivation layer 12, shouldPassivation layer 12 is positioned at the top of source electrode 10 and drain electrode 11, for the protection of each structure sheaf (asFig. 2 g or as shown in Fig. 3 f). In passivation layer 12 peripheries, connecting hole can also be set, for battle arrayThe wiring of row substrate is used. It should be noted that, the design of connecting hole is in order further to meet arraySubstrate wiring is used. The specific design mode of connecting hole can be entered according to the architectural feature of array base palteDesign corresponding to row to be to meet actual needs, the position of this connecting hole design, number with and parameterFeature is not the restriction to technical solution of the present invention, and specific design mode can be with reference to existing skillArt, is not described in detail herein to this.
The polysilicon array base palte of the embodiment of the present invention, looks like by adjusting in polysilicon array base palteThe interlayer position of element electrode and public electrode, has saved organic layer of the prior art and via hole knotStructure, has simplified the interlayer structure of array base palte, has simplified the production technology of array base palte, has reducedCost of manufacture. In addition, it is slit-shaped electrode that public electrode and pixel electrode are positioned at upper electrode, makesThe generation multi-dimensional electric field that cooperatively interacts between electrode, improved the display effect of array base palte.
As a kind of detailed description of the invention of the present invention, a kind of preparation method of array base palte, usesIn forming above-mentioned top gate type TFT polysilicon array base palte, as shown in Figure 4, the method comprises:
Step S1, formation polysilicon active layer and pixel electrode.
It should be noted that, in the present invention, composition technique comprise gluing, exposure, development,The step such as etching, photoresist lift off.
Concrete, as shown in Figure 2 a, first on substrate 1, form one deck cushion 2, thenOn cushion 2, form one deck amorphous silicon layer, utilize low temperature polycrystalline silicon technology, swash by quasi-moleculeAmorphous silicon layer is converted into polysilicon layer by photo-annealing technique. Then, by a composition technique through coveringThe processing steps such as film, exposure, etching and photoresist removal form polysilicon active layer 3. Then,On cushion 2, form layer of transparent conductive layer, by composition technique through mask, exposure,The processing steps such as etching and photoresist removal form pixel electrode 4.
Further, step S1 also comprises: polysilicon active layer 3 is carried out to doping process processing.Polysilicon active layer 3 is carried out doping process and can be changed the threshold voltage of polysilicon active layer 3.It should be noted that, threshold voltage adjustment only, in order to optimize the electrical parameter of active layer 3, does not relate toAnd change in array base-plate structure and preparation method.
Step S2, on the substrate of completing steps S1, form gate insulator.
Concrete, as shown in Figure 2 b, first on the substrate of completing steps S1, form one deck exhaustedEdge layer, forms gate insulator 5.
Step S3, on the substrate of completing steps S2, form grid and public electrode.
Concrete, as shown in Figure 2 c, first on the substrate of completing steps S3, form one deck saturatingBright conductive layer, then, removes through mask, exposure, etching and photoresist by a composition techniqueForm slit-shaped public electrode 6 Deng processing step. Then, form one deck grid metal level, then logicalCross a composition technique and form patterned photoresist, utilize patterned photoresist to carve as maskErosion gate electrode layer, forms gate electrode 7.
The thickness of the public electrode 6 preferably, forming by composition technique in step S3 isPublic electrode 6 is with slit, and in public electrode 6, the quantity of slit is 2～5Individual, slit width is 2～5um, and between slit, the width of public electrode 6 is 2～5um.
Further, in step S3, also comprise: utilize composition technique one time, at public electrodeOn 6, form public electrode wire 8 through processing steps such as mask, exposure, etching and photoresist removals,Preferably, use with a composition technique and form public electrode wire 8 simultaneously and form gate electrode 7.Public electrode wire 8 is in order to transmit public electrode 6 signals, and certainly, public electrode wire 8 can basisSituation arranges, and can judge according to load signal the opportunity of use, such as working as liquid crystal displayThe size of device is when larger, and common electrode signal can arrange public electrode wire 8 weak time. AndIn the time that array base palte common electrode signal can meet the normal use of display unit, can be by common electricalPolar curve 8 structures are saved, in order to the aperture opening ratio of further increase array base palte.
Step S4, on the substrate of completing steps S3, form active layer doped region.
Concrete, as shown in Figure 2 d, first on the substrate of completing steps S3, utilize and form gridIt is heavily doped that the graphical photoresist of electrode 7 carries out N-type (negative) as mask to active layer 3Assorted PROCESS FOR TREATMENT forms doped region 101 in active layer 3. Then, photoresist is carried out to ashMetallization processes processing, removes a part of photoresist, and utilizes remaining photoetching offset plate figure as mask pairActive layer 3 carries out N-type (negative) light dope PROCESS FOR TREATMENT, in active layer 3, forms LDD(LightlyDopedDrain) lightly doped region 102.
Step S5, on the substrate of completing steps S4, form source electrode with hole, drain electrode is used holeAnd pixel electrode via hole.
Concrete, as shown in Figure 2 e, first on the substrate of completing steps S4, form one deck exhaustedEdge layer, forms interlayer insulating film 9. Then pass through a composition technique through mask, exposure, etchingWith the processing step such as photoresist removal, form respectively source electrode with hole 201, drain electrode is with hole 202And pixel electrode via hole 203. Wherein, the hole that source electrode uses with 201Wei source, hole electrode 10Hole, the hole that drain electrode uses for drain electrode 11 with hole 202, pixel electrode via hole 203 isThe hole that drain electrode 11 uses while being connected with pixel electrode 4.
Step S6, on the substrate of completing steps S5, form source electrode and drain electrode, drain electrodeBe connected by pixel electrode via hole with pixel electrode.
Concrete, as shown in Fig. 2 f, first on the substrate of completing steps S5, pass through a structureFigure technique, through processing steps such as mask, exposure, etching and photoresist removals, forms respectively source electrode10 and drain electrode 11. Wherein, drain electrode 11 is undertaken by pixel electrode via hole and pixel electrode 4Be connected.
As a kind of preferred embodiment of the present invention, the system of a kind of array base palte of the present embodimentMake method, also comprise:
Step S7, on the substrate of completing steps S6, form passivation layer, by a composition workSkill forms peripheral connecting hole.
Concrete, as shown in Figure 2 g, first on the substrate of completing steps S6, form one deck exhaustedEdge material, forms passivation layer 12. Passivation layer 12 is in order to protect structure and the device in array base palte,Then form peripheral connecting hole (not shown) by a composition technique.
The preparation method of array base palte provided by the invention, by adjusting in polysilicon array base palteThe interlayer position of pixel electrode and public electrode, has saved organic layer of the prior art and via holeStructure, has simplified the interlayer structure of array base palte, has simplified the production technology of array base palte, reducesCost of manufacture. In addition, it is slit-shaped electrode that public electrode and pixel electrode are positioned at upper electrode,The generation multi-dimensional electric field that makes to cooperatively interact between electrode, has improved the display effect of array base palte.
As another kind of detailed description of the invention of the present invention, a kind of preparation method of array base palte,Be used to form above-mentioned bottom gate type TFT polysilicon array base palte, as shown in Figure 5, the method comprises:
Step S1 ', formation grid and public electrode.
It should be noted that, in the present invention, composition technique comprise gluing, exposure, development,The step such as etching, photoresist lift off.
Concrete, as shown in Figure 3 a, first on substrate 1, form layer of transparent conductive layer, soAfter, by a composition technique through processing step shapes such as mask, exposure, etching and photoresist removalsBecome public electrode 6. Then, form one deck grid metal level, then form by a composition techniquePatterned photoresist, utilizes patterned photoresist as mask etching gate electrode layer, forms gridElectrode 7.
Further, on public electrode 6 through mask, exposure, etching and photoresist removal etc.Processing step forms public electrode wire 8, preferred, uses with a composition technique and forms public affairs simultaneouslyCommon-battery polar curve 8 and formation gate electrode 7.
Further, can adopt intermediate tone mask technique form simultaneously grid, public electrode wire andPublic electrode, specifically can, by first forming layer of transparent conductive layer, form grid metal level afterwards,Define public electrode, public electrode wire and grid by intermediate tone mask simultaneously, adopt the methodTime, be with the difference of Fig. 3 a, below grid 7, have partially transparent conducting film and exist.
Step S2 ', on the substrate of completing steps S1 ', form gate insulator, polysilicon hasSource layer and pixel electrode.
Concrete, as shown in Figure 3 b, first on the substrate 1 of completing steps S1 ', form gridInsulating barrier 5 then forms one deck amorphous silicon layer on gate insulator 5, utilizes low temperature polycrystalline siliconTechnology, is converted into polysilicon layer by quasi-molecule laser annealing technique by amorphous silicon layer. Then, logicalCross a composition technique and form polycrystalline through processing steps such as mask, exposure, etching and photoresist removalsSilicon active layer 3. Then, on gate insulator 5, form layer of transparent conductive layer, by onceComposition technique forms pixel electrode 4 through processing steps such as mask, exposure, etching and photoresist removals.
Further, step S2 ' also comprises: polysilicon active layer 3 is carried out to doping process placeReason. Polysilicon active layer 3 is carried out doping process and can be adjusted the threshold value electricity of polysilicon active layer 3Press. It should be noted that, threshold voltage adjustment is only in order to optimize the electrical parameter of active layer 3, andDo not relate to the change in array base-plate structure and preparation method.
Step S3 ', on the substrate of completing steps S2 ', form active layer doped region and interlayerInsulating barrier 9. Form structure as shown in Figure 3 c. It is active that this step mainly adopts doping process to formLayer doped region, forms one deck interlayer insulating film 9 afterwards again.
Step S4 ', on the substrate of completing steps S3 ', form source electrode with hole, drain electrode is usedHole and pixel electrode via hole. Form part-structure as shown in Figure 3 d.
Step S5 ', on the substrate of completing steps S4 ', form source electrode and drain electrode, electric leakageThe utmost point is connected by pixel electrode via hole with pixel electrode. Form part-structure as shown in Figure 3 e.
As a kind of preferred embodiment of the present invention, the system of a kind of array base palte of the present embodimentMake method, also comprise:
Step S6 ', on the substrate of completing steps S5 ', form passivation layer, by a compositionTechnique forms peripheral connecting hole. Form the part-structure as shown in Fig. 3 f.
Form the step S3 '～S6 ' of bottom gate type TFT polysilicon array substrate manufacturing method with upperThe technique of stating the step S4～S7 that forms top gate type TFT polysilicon array substrate manufacturing method is identical,Do not repeat at this.
The preparation method of array base palte provided by the invention, by adjusting in polysilicon array base palteThe interlayer position of pixel electrode and public electrode, has saved organic layer of the prior art and via holeStructure, has simplified the interlayer structure of array base palte, has simplified the production technology of array base palte, reducesCost of manufacture. In addition, it is slit-shaped electrode that public electrode and pixel electrode are positioned at upper electrode,The generation multi-dimensional electric field that makes to cooperatively interact between electrode, has improved the display effect of array base palte.
In the embodiment of the present invention, the specific implementation of each step, especially wherein about forming filmThe mode of layer and the description of rete shape, be only exemplary illustration, is not to technical schemeRestriction, those skilled in the art can set according to actual needs and select, each structure deviceThe figure of part can change along with the variation of display design, in the present embodiment in array base-plate structureListed situation is only situation preferably.
In addition, the present embodiment also provides a kind of liquid crystal indicator, comprises above-mentioned array base palte,Wherein, the same above-described embodiment of the structure of array base palte and operation principle, does not repeat them here. SeparatelyOutward, the structure of other parts of liquid crystal indicator can be with reference to prior art, no longer detailed herein to thisThin description.
The liquid crystal indicator that the embodiment of the present invention provides, described liquid crystal indicator can be: liquidCrystal panel, Electronic Paper, LCD TV, liquid crystal display, DPF, mobile phone, panel computerEtc. any product or parts with Presentation Function.
The liquid crystal indicator of the embodiment of the present invention, by adjusting pixel in polysilicon array base palteThe interlayer position of electrode and public electrode, has saved organic layer of the prior art and via hole knotStructure, has simplified the interlayer structure of array base palte, has simplified the production technology of array base palte, has reducedCost of manufacture. In addition, it is slit-shaped electrode that public electrode and pixel electrode are positioned at upper electrode, makesThe generation multi-dimensional electric field that cooperatively interacts between electrode, improved the display effect of array base palte.
The above be only the specific embodiment of the present invention, but protection scope of the present invention alsoBe not limited to this, any be familiar with those skilled in the art the present invention disclose technical scopeIn, can expect easily changing or replacing, within all should being encompassed in protection scope of the present invention. Therefore,Protection scope of the present invention should described be as the criterion with the protection domain of claim.
Claims (4)
1. a preparation method for array base palte, is characterized in that, comprising:
The first step, forms polysilicon active layer and pixel electrode; Wherein, described active layer and instituteStating pixel electricity level layer arranges with layer;
Second step, forms gate insulator;
The 3rd step, utilizes transparency conducting layer to form public electrode;
The 4th step, utilizes metal level to form grid; Wherein, described grid and described public electrodeLayer arranges with layer;
The 5th step, forms active layer doped region;
The 6th step, forms hole, hole and pixel electrode via hole for drain electrode for the electrode of source;
The 7th step, forms source electrode and drain electrode, and described drain electrode and described pixel electrode pass throughDescribed pixel electrode via hole is connected.
2. the preparation method of array base palte according to claim 1, is characterized in that, alsoBe included on described substrate and form cushion.
3. the preparation method of array base palte according to claim 1, is characterized in that, instituteState the public electrode wire being provided with above or below public electrode with described common electrode contact.
4. the preparation method of array base palte according to claim 1, is characterized in that,After forming described source electrode and described drain electrode, also comprise: form passivation layer, by a structureFigure technique forms peripheral connecting hole.
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| CN111640766B (en) * | 2020-06-22 | 2023-12-12 | 武汉华星光电技术有限公司 | Array substrate and manufacturing method thereof |
| CN114093241B (en) * | 2020-08-25 | 2023-08-15 | 合肥鑫晟光电科技有限公司 | Driving backboard, manufacturing method thereof and display device |
| CN114839817A (en) * | 2022-05-16 | 2022-08-02 | 广州华星光电半导体显示技术有限公司 | Display panel |
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| CN102629664A (en) * | 2012-01-04 | 2012-08-08 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, and display apparatus |
| CN102629589A (en) * | 2011-12-27 | 2012-08-08 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, and display apparatus |
| CN102651403A (en) * | 2012-04-16 | 2012-08-29 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate and manufacturing method of array substrate and display panel |
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| CN101750821A (en) * | 2008-12-03 | 2010-06-23 | 株式会社半导体能源研究所 | Liquid crystal display device |
| CN102629585A (en) * | 2011-11-17 | 2012-08-08 | 京东方科技集团股份有限公司 | Display device, thin film transistor, array substrate and manufacturing method thereof |
| CN102629589A (en) * | 2011-12-27 | 2012-08-08 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, and display apparatus |
| CN102629664A (en) * | 2012-01-04 | 2012-08-08 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, and display apparatus |
| CN102651403A (en) * | 2012-04-16 | 2012-08-29 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate and manufacturing method of array substrate and display panel |
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