CN102981801B - A kind of conversion method of local bus data bit width and device - Google Patents
A kind of conversion method of local bus data bit width and device Download PDFInfo
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- CN102981801B CN102981801B CN201210439679.5A CN201210439679A CN102981801B CN 102981801 B CN102981801 B CN 102981801B CN 201210439679 A CN201210439679 A CN 201210439679A CN 102981801 B CN102981801 B CN 102981801B
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Abstract
This application discloses a kind of conversion method and device of local bus data bit width, by the LOCAL utilizing the 32 bit operating instructions of CPU automatically can produce two 16 bits? the feature of BUS operational order, completed the conversion of 16 bit/32 Bit datas by the way of temporal data by programmable logic cells, to realize " writing " or " reading " peripheral hardware of high 16 bits and low 16 Bit datas simultaneously simultaneously, bit width conversion operational order is made not have perception concerning drive software.The narrow data bit width cpu local bus realized by this method, to the operational order of wide data bit width peripheral hardware chip, can reduce the workload of drive software further, improves CPU operational order efficiency, reduces system overhead.
Description
Technical field
The application relates to general central processor in data communication (CPU) system application, refers more particularly to conversion method and the device of a kind of local bus (Local Bus) data bit width.
Background technology
In some Embedded System Design, CPU is communicated by Local Bus bus to the peripheral hardware chip realizing specific function and manages.The Local Bus bus bit wide of CPU and peripheral hardware chip is likely asymmetric, generally takes one of the following two kinds mode to solve this problem in prior art:
Mode 1: again choose CPU or peripheral hardware chip, make both Local Bus buses symmetrical, the advantage of the method does not need additional chip bridge joint and additional any process, and CPU just can carry out processing instruction to peripheral hardware chip; But under normal circumstances, because CPU or peripheral hardware chip have certain specific function, can not be substituted, and again choose the man power and material that CPU or peripheral hardware chip need at substantial, cause project development to be delayed, the serious consequence such as make the product developed no longer effective.
Mode 2: select CPLD (CPLD, Complex Programmable Logic Device) or the programmable logic chip such as field programmable gate array (FPGA, Field-Programmable Gate Array) carry out bit width conversion.To be illustrated in figure 1 in certain system CPU to the hardware block diagram of peripheral hardware management of software ic.CPU 101 is connected by the LOCAL BUS bus that bit wide is 16 bits (bit) with CPLD 102, and CPLD 102 and peripheral hardware chip 103 are the LOCAL BUS bus of 32 bits by bit wide.When designing CPLD logic, usually still can require that driver is by 16 bit operating instructions: when write operation instruction, high 16 bit register and low 16 bit register can be provided to carry out the data of buffer memory 32 bits for driver, then CPLD writes peripheral hardware chip by the sequential of peripheral hardware chip requirement this 32 Bit data again, also requires that driver must wait this operational order to complete and just can carry out new read-write simultaneously; When read operation instruction, need CPLD first to send a read command to peripheral hardware chip, the data buffer storage of 32 bits in CPLD, then CPU reads back data come by height 16 bit register again.This processing mode has higher system overhead, causes the efficiency of CPU operational order not high.
Because in this, be necessary to propose a kind of new solution, solve existing CPU and the incompatible problem of peripheral hardware chip local bus.
Summary of the invention
This application provides a kind of conversion method and device of local bus data bit width, the workload of drive software can be reduced, improve CPU operational order efficiency, reduce system overhead.
The conversion method of a kind of local bus data bit width that the embodiment of the present application provides, comprising:
The write command of 32 bits received is converted to the 16 bit write operation instructions successively decreased by 16 bit aligned in two addresses by CPU;
Data in CPU first 16 bit write operation instruction and high address are kept in by programmable logic cells;
Programmable logic cells sends an external address termination signal/TA to CPU and stops first 16 bit write operation instruction;
CPU sends second 16 bit write operation instruction to programmable logic cells, and programmable logic cells is sent on the address signal pin of peripheral hardware chip after the low order address in the high address of first temporary 16 bit write operation instruction and second 16 bit write operation instruction is combined;
Data in first 16 bit write operation instruction that data in second 16 bit write operation instruction that programmable logic cells sends CPU and programmable logic cells are kept in are sent in 32 bit data bus of peripheral hardware chip, then wait for that peripheral hardware chip sends termination signal Dtack_n;
Programmable logic cells stops write operation instruction after receiving the Dtack_n that peripheral hardware chip sends immediately, sends second 16 bit write operation instruction of one/TA signal terminating CPU to CPU simultaneously.
Preferably, the method that data in the write operation instruction of CPU first 16 bit and high address are kept in is by described programmable logic cells: 16 bit high addresses in CPU first 16 bit write operation instruction allow in the address register of end ale signal write programmable logic cells temporary by programmable logic cells by address latch, and low 16 Bit datas in first 16 bit write command are then by chip selection signal CSn with write useful signal WRn and write in the data register of programmable logic cells temporary.
Preferably, CPU sends second 16 bit write command to programmable logic cells, after programmable logic cells combines the high address in first temporary 16 bit write command and the low order address in second 16 bit write operation instruction, the method be sent on the address signal pin of peripheral hardware chip comprises: CPU sends second 16 bit write operation instruction to programmable logic cells, programmable logic cells sends CSn to peripheral hardware chip, address signal ASn and and low level WRn, be sent on the address signal pin of peripheral hardware chip after 16 bit low order address in address signal in 16 temporary bit high addresses and second 16 bit write operation instruction being combined simultaneously.
Preferably, 32 bit data bus that the data of first 16 bit write operation instruction that the programmable logic cells data of second 16 bit write operation instruction that CPU is sent and programmable logic cells are kept in are sent to peripheral hardware chip comprise: be sent in 32 bit data bus of peripheral hardware chip after low 16 Bit datas temporary on high 16 Bit datas that programmable logic cells sends CPU and programmable logic cells data register combine.
The embodiment of the present application also provides the conversion method of another kind of local bus data bit width, comprising:
The instruction transformation of reading of 32 bits received is that 16 bits successively decreased by 16 bit aligned in two addresses read instruction by CPU;
CPU sends first 16 bit and reads instruction to programmable logic chip unit, programmable logic chip unit allows the end ALE cycle to be kept in 16 bit high addresses in first 16 bit read operation instruction at address latch, chip selection signal CSn, address signal ASn and read-write selection signal RWn is sent subsequently to peripheral hardware chip, be sent to the address signal pin of peripheral hardware chip after 16 bit low order address in 16 temporary bit high addresses and second 16 bit read operation instruction are combined, start the 32 bit read operation instructions to peripheral hardware chip;
Peripheral hardware chip is put into the data of 32 bits after on data bus, and programmable logic chip unit is transferred to CPU low 16 Bit datas wherein, and high 16 Bit data data registers are wherein kept in; Then to programmable logic chip unit, peripheral hardware chip represents that the read operation instruction of this 32 bit completes by sending termination signal Dtack_n;
Programmable logic chip unit then sends first 16 bit read operation instruction of one/TA signal terminating CPU after receiving the Dtack_n signal that peripheral hardware sends to CPU;
CPU sends second 16 bit read operation instruction to programmable logic chip unit, programmable logic chip unit is sent to CPU 16 Bit datas be temporarily stored in data register, and sends second 16 bit read operation instruction of one/TA signal terminating CPU to CPU.
Preferably, described programmable logic cells is complex programmable logic device (CPLD) or on-site programmable gate array FPGA.
The embodiment of the present application also provides a kind of conversion equipment of local bus data bit width, comprises the peripheral hardware chip of the CPU of 16 bit local bus, 32 bit local bus, is connected the programmable logic cells of described CPU and peripheral hardware chip respectively with one,
These two 16 bit write operation instructions for the write command of receive 32 bits being converted to the 16 bit write operation instructions successively decreased by 16 bit aligned in two addresses, and are sent to described programmable logic cells at two adjacent clock cycles by described CPU respectively;
Described programmable logic cells, after keeping in, sends an external address termination signal/TA to CPU and stops first 16 bit write operation instruction for the data in first 16 bit write operation instruction being sent by CPU and high address;
And receiving after CPU sends second 16 bit write operation instruction, be sent on the address signal pin of peripheral hardware chip after the low order address in the high address of first temporary 16 bit write operation instruction and second 16 bit write operation instruction is combined;
Data in first 16 bit write operation instruction that data in second 16 bit write operation instruction that CPU sends and programmable logic cells are kept in are sent in 32 bit data bus of peripheral hardware chip, then wait for that peripheral hardware chip sends termination signal Dtack_n;
Stop write operation instruction immediately after receiving the Dtack_n that peripheral hardware chip sends, send second 16 bit write operation instruction of one/TA signal terminating CPU simultaneously to CPU.
The embodiment of the present application additionally provides a kind of conversion equipment of local bus data bit width, comprises the peripheral hardware chip of the CPU of 16 bit local bus, 32 bit local bus, is connected the programmable logic cells of described CPU and peripheral hardware chip respectively with one,
These two 16 bit read operation instructions for being the 16 bit read operation instructions successively decreased by 16 bit aligned in two addresses by the instruction transformation of reading of receive 32 bits, and are sent to described programmable logic cells at two adjacent clock cycles by described CPU respectively;
Described programmable logic cells is used for:
Receiving CPU sends after first 16 bit read instruction, the end ALE cycle is allowed to be kept in 16 bit high addresses in first 16 bit read operation instruction at address latch, chip selection signal CSn, address signal ASn and read-write selection signal RWn is sent subsequently to peripheral hardware chip, be sent to the address signal pin of peripheral hardware chip after 16 bit low order address in 16 temporary bit high addresses and second 16 bit read operation instruction are combined, start the 32 bit read operation instructions to peripheral hardware chip;
Receive the data of 32 bits of peripheral hardware chip from data bus after, low 16 Bit datas are wherein transferred to CPU, high 16 Bit data data registers are wherein kept in; Then after receiving the termination signal Dtack_n signal that peripheral hardware chip sends, then first 16 bit read operation instruction of one/TA signal terminating CPU are sent to CPU;
Receiving after CPU sends second 16 bit read operation instruction, 16 Bit datas be temporarily stored in data register being sent to CPU, and sending second 16 bit read operation instruction of one/TA signal terminating CPU to CPU.
Preferably, described programmable logic cells is complex programmable logic device (CPLD) or on-site programmable gate array FPGA.
As can be seen from the above technical solutions, utilize the 32 bit operating instructions of CPU automatically can produce the feature of the LOCAL BUS operational order of two 16 bits, completed the conversion of 16 bit/32 Bit datas by the way of temporal data by programmable logic cells, to realize " writing " or " reading " peripheral hardware of high 16 bits and low 16 Bit datas simultaneously simultaneously, bit width conversion operational order is made not have perception concerning drive software.The narrow data bit width CPU Local Bus realized by this method, to the operational order of wide data bit width peripheral hardware, can reduce the workload of drive software further, improves CPU operational order efficiency, reduces system overhead.
Accompanying drawing explanation
Fig. 1 be in prior art in certain system CPU to the hardware block diagram of peripheral hardware management of software ic;
Fig. 2 be CPU of the present invention to CPLD send a 32 bit write operation instruction time sequential chart;
Fig. 3 is the sequential chart that send 32 bit write operation instructions of CPLD of the present invention to peripheral hardware chip;
The CPU that Fig. 4 provides for the embodiment of the present invention one sends 32 bit write command stream compression sequential charts by CPLD to peripheral hardware chip;
The CPU that Fig. 5 provides for the embodiment of the present invention one is to 32 bit write operation instruction flow charts of peripheral hardware chip;
Fig. 6 is that CPU of the present invention sends to CPLD the sequential chart that 32 bits read instruction;
Fig. 7 is that CPLD of the present invention sends to peripheral hardware chip the sequential chart that 32 bits read instruction;
The CPU that Fig. 8 provides for the embodiment of the present invention one sends 32 bits by CPLD to peripheral hardware chip and reads director data circulation sequential chart;
The CPU that Fig. 9 provides for the embodiment of the present invention two is to 32 bit read operation instruction flow charts of peripheral hardware chip.
Embodiment
For problems of the prior art, the application proposes a kind of conversion method of Local Bus data bit width, the basis of existing CPU standard 16 bit Local Bus bus read write command operates the peripheral hardware of 32 bits, utilize 32 bit instruction of CPU automatically can produce the feature of the Local Bus instruction of two 16 bits, completed the conversion of 16 bit/32 Bit datas by the way of temporal data by CPLD logic, to realize " writing " or " reading " peripheral hardware of high 16 bits and low 16 Bit datas simultaneously simultaneously, bit width conversion is operated concerning drive software, there is no perception.Improve readability and the efficiency of drive software.
For making the know-why of technical scheme, feature and technique effect clearly, below in conjunction with specific embodiment, technical scheme is described in detail.The conversion of the data bit width of local bus is divided into write operation instruction and read operation instruction two kinds of operational orders to realize, and is set forth respectively below by way of two embodiments.
Embodiment one: the local bus bit width conversion in write operation instruction
Fig. 2 be CPU to CPLD send a 32 bit write command time sequential chart, wherein A [15:0] is the address signal of 16 bits, Csn/WRn is chip selection signal/write enable signal, ALE is that address latch allows end (Address lock enable) signal, AD [31:16] is 16 bit addresses/data-reusing signal, and/TA is external address termination signal.When CPU receives the write command of 32 bits, for the local busLocal Bus of 16 bits, actual what send is successively decrease by 16 bit aligned in two addresses, and data bit is the write operation instruction of 16 bit widths.The local busLocal Bus of CPU must be configured such that the write operation instruction completing CPU with external address termination signal/TA.
Fig. 3 is the sequential chart that send 32 bit write operation instructions of CPLD to peripheral hardware chip.Wherein, CPU_CLK is clock signal, and CSn is chip selection signal, and ASn is address signal, RWn is read-write selection signal, and high expression reads, and low expression is write, A [23:2] is 22 bit writing address signals, and D [31:0] is 32 bit write data signals, and Dtack_n is that data transmit termination signal.Address sent in the ASn cycle, sent 32 Bit datas subsequently, until peripheral hardware chip provides termination signal Dtack_n.
As can be seen from Figures 2 and 3, as long as CPLD is embedded into the write operation instruction of peripheral hardware chip second write cycle time that CPU sends to CPLD, bumpless transfer can be realized.
The CPU that Fig. 4 shows embodiment one to be provided sends the stream compression sequential chart of 32 bit write operation instructions to peripheral hardware chip by CPLD.Based on this sequential, CPU to peripheral hardware chip 32 bit write operation instruction flows as shown in Figure 5, comprising:
After step 501:CPU receives the write command of 32 bits, for the local bus of 16 bits, be converted to the 16 bit write operation instructions successively decreased by 16 bit aligned in two addresses.
When CPU writes 32 Bit data, always first write low 16 Bit datas, then write high 16 Bit datas, general address wire A1 is low, and thus CPLD can be low by recognizing address wire A1, confirms that this is first the 16 bit write operation instruction writing 32 bits.In follow-up sequential, CPLD recognizes address wire A1 when being high, is confirmed to be second 16 bit write operation instruction that is write 32 bits.
16 bit high addresses A [31:16] in CPU first 16 bit write operation instruction allow in the address register of end ale signal write CPLD temporary by step 502:CPLD by address latch, low 16 Bit datas in first 16 bit write operation instruction are then by temporary in the data register of CSn and WRn signal write CPLD;
Step 503:CPLD sends to CPU the write operation instruction that one/TA stops first 16 bit;
Step 504:CPU sends second 16 bit write operation instruction and high 16 Bit datas is sent to CPLD, CPLD then to peripheral hardware chip send CSn, address signal ASn and and low level RWn, be sent on the address signal pin of peripheral hardware chip after the low order address in the high address of first temporary 16 bit write operation instruction and second 16 bit write operation instruction being combined according to the address signal pin scope of peripheral hardware chip, then wait for that peripheral hardware chip sends termination signal Dtack_n;
The address realm how combining the address wire support of high address in two 16 bit write operation instructions and status address and peripheral hardware chip herein has relation, if the address signal pin when peripheral hardware chip is FA [23:2], then the A [23:16] in 16 temporary bit high addresses A [31:16] and the A [15:2] in 16 bit low order address A [15:0] in address signal in second 16 bit write operation instruction are combined, be sent on the address signal pin FA [23:2] of peripheral hardware chip, CPLD combines high 16 Bit datas that CPU sends low 16 Bit datas that upper CPLD data register is preserved and is put on the peripheral hardware chip data bus D [31:0] of 32 bits,
Step 505:CPLD stops write operation instruction after receiving the Dtack_n that peripheral hardware chip sends immediately, send second 16 bit write operation instruction of one/TA signal terminating CPU simultaneously to CPU, thus complete the 32 bit write operation instructions of CPU to peripheral hardware chip.
Embodiment two: the local bus bit width conversion in read operation instruction
What Fig. 6 was CPU to CPLD sends the sequential chart that 32 bits read.As shown in Figure 6, CPU receive 32 bits read instruction time, for the Local Bus of 16 bits, actual what send is that two addresses increase by 16 bit aligned, and data bit is the read operation instruction of 16 bit widths.Local Bus use still external address termination signal/TA to complete the read operation instruction of CPU.
What Fig. 7 was CPLD to peripheral hardware chip sends the sequential chart that 32 bits read.Address sent in the ASn cycle, and 32 Bit datas send subsequently, until peripheral hardware chip provides termination signal Dtack_n.
As can be seen from Figures 6 and 7, as long as CPLD to take out the data of 32 bits first CPU read cycle from peripheral hardware chip, and low 16 bits are issued CPU, then in second read cycle of CPU, high 16 bits are issued CPU, the bumpless transfer of read operation instruction can be realized.
The CPU that Fig. 8 shows embodiment two to be provided sends the stream compression sequential chart of 32 bit read operation instructions to peripheral hardware chip by CPLD.Based on this sequential, CPU to peripheral hardware chip 32 bit read operation instruction flows as shown in Figure 9, comprising:
Step 901:CPU receive 32 bits read instruction after, for the Local Bus of 16 bits, actually send the read operation instruction that two addresses are 16 bit widths by the data bit that 16 bit aligned are successively decreased.When CPU reads 32 Bit data, always first read low 16 Bit datas, then read high 16 Bit datas, thus CPLD can be low by recognizing address wire A1, confirms that this is first 16 bit read operation instruction that 32 bits read instruction.
Step 902:CPLD receives for first 16 bit read operation instruction, then start to send CSn, ASn and RWn to peripheral hardware chip, 16 bit low order address in address signal A [15:0] in 16 temporary bit high address recombinants are sent on the address signal pin FA [23:2] of peripheral hardware chip simultaneously, start the 32 bit read operation instructions to peripheral hardware chip;
Step 903: when peripheral hardware chip is put into the data of 32 bits after on data bus D [31:0], CPLD is put into low 16 bit D [15:0] wherein on data bus D [15:0], and high 16 bit D [31:16] are wherein saved with data register; Then to CPLD, peripheral hardware chip represents that the read operation instruction of this 32 bit completes by sending Dtack_n.
Step 904:CPLD then sends first 16 bit read operation instruction of one/TA signal terminating CPU after receiving the Dtack_n signal that peripheral hardware sends to CPU;
Step 905:CPU is followed by sending second 16 bit read operation instruction, CPLD is put into 16 Bit datas be temporarily stored in register in AD [15:0] bus immediately, sends second 16 bit read operation instruction of one/TA signal terminating CPU to CPU simultaneously.
In above embodiment, the programmable logic device (PLD) of carrying out bit width conversion between CPU and peripheral hardware chip is CPLD.Also the programmable logic device (PLD) of other types can be adopted, such as FPGA in practical application.
The foregoing is only the preferred embodiment of the application; not in order to limit the protection domain of the application; within all spirit in technical scheme and principle, any amendment made, equivalent replacements, improvement etc., all should be included within scope that the application protects.
Claims (9)
1. a conversion method for local bus data bit width, is characterized in that, comprising:
The write operation instruction transformation of 32 bits received is the 16 bit write operation instructions successively decreased by 16 bit aligned in two addresses by CPU;
Data in CPU first 16 bit write operation instruction and high address are kept in by programmable logic cells;
Programmable logic cells sends an external address termination signal/TA to CPU and stops first 16 bit write operation instruction;
CPU sends second 16 bit write operation instruction to programmable logic cells, and programmable logic cells is sent on the address signal pin of peripheral hardware chip after the low order address in the high address of first temporary 16 bit write operation instruction and second 16 bit write operation instruction is combined;
Data in first 16 bit write operation instruction that data in second 16 bit write operation instruction that programmable logic cells sends CPU and programmable logic cells are kept in are sent in 32 bit data bus of peripheral hardware chip, then wait for that peripheral hardware chip sends termination signal Dtack_n;
Programmable logic cells stops write operation instruction after receiving the Dtack_n that peripheral hardware chip sends immediately, sends second 16 bit write operation instruction of one/TA signal terminating CPU to CPU simultaneously.
2. method according to claim 1, it is characterized in that, the method that data in the write operation instruction of CPU first 16 bit and high address are kept in is by described programmable logic cells: 16 bit high addresses in CPU first 16 bit write operation instruction allow in the address register of end ale signal write programmable logic cells temporary by programmable logic cells by address latch, low 16 Bit datas in first 16 bit write operation instruction are then by chip selection signal CSn with write useful signal WRn and write in the data register of programmable logic cells temporary.
3. method according to claim 2, it is characterized in that, CPU sends second 16 bit write command to programmable logic cells, after programmable logic cells combines the high address in first temporary 16 bit write command and the low order address in second 16 bit write operation instruction, the method be sent on the address signal pin of peripheral hardware chip comprises: CPU sends second 16 bit write operation instruction to programmable logic cells, programmable logic cells sends CSn to peripheral hardware chip, address signal ASn and and low level WRn, be sent on the address signal pin of peripheral hardware chip after 16 bit low order address in address signal in 16 temporary bit high addresses and second 16 bit write operation instruction being combined simultaneously.
4. method according to claim 3, it is characterized in that, 32 bit data bus that the data of first 16 bit write operation instruction that the data of second 16 bit write operation instruction that programmable logic cells sends CPU and programmable logic cells are kept in are sent to peripheral hardware chip comprise: be sent in 32 bit data bus of peripheral hardware chip after low 16 Bit datas temporary on high 16 Bit datas that programmable logic cells sends CPU and programmable logic cells data register combine.
5. a conversion method for local bus data bit width, is characterized in that, comprising:
The instruction transformation of reading of 32 bits received is that 16 bits successively decreased by 16 bit aligned in two addresses read instruction by CPU;
CPU sends first 16 bit and reads instruction to programmable logic chip unit, programmable logic chip unit allows the end ALE cycle to be kept in 16 bit high addresses in first 16 bit read operation instruction at address latch, chip selection signal CSn, address signal ASn and read-write selection signal RWn is sent subsequently to peripheral hardware chip, be sent to the address signal pin of peripheral hardware chip after 16 bit low order address in 16 temporary bit high addresses and second 16 bit read operation instruction are combined, start the 32 bit read operation instructions to peripheral hardware chip;
Peripheral hardware chip is put into the data of 32 bits after on data bus, and programmable logic chip unit is transferred to CPU low 16 Bit datas wherein, and high 16 Bit data data registers are wherein kept in; Then to programmable logic chip unit, peripheral hardware chip represents that the read operation instruction of this 32 bit completes by sending termination signal Dtack_n;
Programmable logic chip unit then sends first 16 bit read operation instruction of one/TA signal terminating CPU after receiving the Dtack_n signal that peripheral hardware sends to CPU;
CPU sends second 16 bit read operation instruction to programmable logic chip unit, programmable logic chip unit is sent to CPU 16 Bit datas be temporarily stored in data register, and sends second 16 bit read operation instruction of one/TA signal terminating CPU to CPU.
6. the method according to any one of claim 1 to 5, is characterized in that, described programmable logic cells is complex programmable logic device (CPLD) or on-site programmable gate array FPGA.
7. a conversion equipment for local bus data bit width, comprises the peripheral hardware chip of the CPU of 16 bit local bus, 32 bit local bus, is connected the programmable logic cells of described CPU and peripheral hardware chip respectively, it is characterized in that with one,
These two 16 bit write operation instructions for the write command of receive 32 bits being converted to the 16 bit write operation instructions successively decreased by 16 bit aligned in two addresses, and are sent to described programmable logic cells at two adjacent clock cycles by described CPU respectively;
Described programmable logic cells, after keeping in, sends an external address termination signal/TA to CPU and stops first 16 bit write operation instruction for the data in first 16 bit write operation instruction being sent by CPU and high address;
And receiving after CPU sends second 16 bit write operation instruction, be sent on the address signal pin of peripheral hardware chip after the low order address in the high address of first temporary 16 bit write operation instruction and second 16 bit write operation instruction is combined;
Data in first 16 bit write operation instruction that data in second 16 bit write operation instruction that CPU sends and programmable logic cells are kept in are sent in 32 bit data bus of peripheral hardware chip, then wait for that peripheral hardware chip sends termination signal Dtack_n;
Stop write operation instruction immediately after receiving the Dtack_n that peripheral hardware chip sends, send second 16 bit write operation instruction of one/TA signal terminating CPU simultaneously to CPU.
8. the conversion equipment of a local bus data bit width, comprise the peripheral hardware chip of the CPU of 16 bit local bus, 32 bit local bus, the programmable logic cells of described CPU and peripheral hardware chip is connected respectively with one, it is characterized in that, described CPU, for being the 16 bit read operation instructions successively decreased by 16 bit aligned in two addresses by the instruction transformation of reading of receive 32 bits, and these two 16 bit read operation instructions are sent to described programmable logic cells respectively at two adjacent clock cycles;
Described programmable logic cells is used for:
Receiving CPU sends after first 16 bit read instruction, the end ALE cycle is allowed to be kept in 16 bit high addresses in first 16 bit read operation instruction at address latch, chip selection signal CSn, address signal ASn and read-write selection signal RWn is sent subsequently to peripheral hardware chip, be sent to the address signal pin of peripheral hardware chip after 16 bit low order address in 16 temporary bit high addresses and second 16 bit read operation instruction are combined, start the 32 bit read operation instructions to peripheral hardware chip;
Receive the data of 32 bits of peripheral hardware chip from data bus after, low 16 Bit datas are wherein transferred to CPU, high 16 Bit data data registers are wherein kept in; Then after receiving the termination signal Dtack_n signal that peripheral hardware chip sends, then first 16 bit read operation instruction of one/TA signal terminating CPU are sent to CPU;
Receiving after CPU sends second 16 bit read operation instruction, 16 Bit datas be temporarily stored in data register being sent to CPU, and sending second 16 bit read operation instruction of one/TA signal terminating CPU to CPU.
9. device as claimed in claim 7 or 8, it is characterized in that, described programmable logic cells is complex programmable logic device (CPLD) or on-site programmable gate array FPGA.
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| CN103559161B (en) * | 2013-09-24 | 2016-02-10 | 北京时代民芯科技有限公司 | A kind of bus many width change-over circuit for FPGA configuration |
| CN108572787A (en) * | 2017-03-09 | 2018-09-25 | 深圳市中兴微电子技术有限公司 | A kind of method and device that data are stored, read |
| CN110221994B (en) * | 2018-03-01 | 2022-04-08 | 深圳市中兴微电子技术有限公司 | Method and device for data bit width conversion and computer readable storage medium |
| CN108984441B (en) * | 2018-05-31 | 2020-06-02 | 烽火通信科技股份有限公司 | Method and system for maintaining data transmission consistency |
| CN111309653B (en) * | 2018-12-12 | 2021-08-17 | 北京兆易创新科技股份有限公司 | Data bus and method for reading data and writing data |
| CN111949585A (en) * | 2020-07-15 | 2020-11-17 | 西安万像电子科技有限公司 | Data conversion processing method and device |
| CN114595181B (en) * | 2020-12-03 | 2024-01-12 | 沈阳中科数控技术股份有限公司 | Bus matching realization method for embedded system |
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