CN102955747B

CN102955747B - Golden key transmission method, memory controller and memory storage device

Info

Publication number: CN102955747B
Application number: CN201110243941.4A
Authority: CN
Inventors: 詹清文
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2011-08-24
Filing date: 2011-08-24
Publication date: 2015-05-20
Anticipated expiration: 2031-08-24
Also published as: CN102955747A

Abstract

The invention discloses a golden key transmission method, a memory controller and a memory storage device. The golden key transmission method is used for transmitting a golden key from a buffering memory to an encryption and decryption unit. The method includes: logically dividing multiple bits of the golden key into a plurality of golden key sectors, wherein each golden key sector comprises an initial position and a sector length; setting a transmission length corresponding to each golden key sector according to the initial position and the sector length of each golden key sector, and assigning transmission bit strings to each golden key sector from bits of the golden key; and deciding the transmission sequence of each golden key sector and transmitting the initial position, the sector length and the transmission bit string of each golden key sector to the encryption and decryption unit according to the transmission sequence. Therefore, the golden key can be safely transmitted from the buffering memory to the encryption and decryption unit by the golden key transmission method.

Description

Gold key transfer approach, Memory Controller and memorizer memory devices

Technical field

The present invention relates to a kind of golden key transfer approach, particularly relate to a kind of method golden key being sent to from memory buffer encryption/decryption element via bus, and use Memory Controller and the memorizer memory devices of the method.

Background technology

Digital camera, mobile phone and MP3 are very rapid in growth over the years, impel consumer to the demand of Storage Media also rapid increase.Due to type nonvolatile (rewritable non-volatile memory) have that data non-volatile, low power consumption, volume are little, mechanical structure and the characteristic such as read or write speed is fast, be suitable for use in most portable type electronic product, such as mobile phone, personal digital assistant and mobile computer etc.Therefore, in recent years, flash memory industry becomes a ring quite popular in electronic industry.Because type nonvolatile device volume is little, capacity is large and easy to carry, be thus extensively used in the storage of personal data.But when type nonvolatile device is lost because of carelessness, the mass data stored by it also may be thereupon stolen.For head it off, usually an encryption/decryption element can be set in type nonvolatile device, read with being consulted meaning to prevent data or usurp.

Generally speaking, conventional encryption and decryption rule (as AES and DES etc.) all first must input 1 to 3 golden key before use.Traditionally, when implementation hardware, usually can once by the register (register) of all golden key write encryption/decryption elements.But from the viewpoint of data bus (data bus) or subaisle (side channel), this way implies the risk that golden key is logged.Fig. 1 is the schematic diagram of the transmission gold key illustrated according to prior art.Please refer to Fig. 1, before use encryption/decryption element 1, must first golden key 252a be sent in the golden key register 1a of encryption/decryption element 1 from memory buffer 252.Usually, golden key 252a once can be write the golden key register 1a of encryption/decryption element 1 by prior art, and so, the content of golden key 252a will appear on data bus 401 uninterruptedly.Therefore, during the transmission of golden key 252a, the third party just can carry out detecting (probe) on data bus 401, or by modes such as measure energy variation, power losses, and obtain the content of golden key.Base this, have and need a kind of safer reliable golden key transfer approach of development.

Summary of the invention

The invention provides a kind of golden key transfer approach, Memory Controller and memorizer memory devices, golden key can be sent to encryption/decryption element from memory buffer by safely.

Exemplary embodiment of the present invention proposes a kind of golden key transfer approach, for golden key is sent to encryption/decryption element via data bus from memory buffer.This golden key transfer approach comprises multiple positions of golden key is logically divided into multiple golden key section, and wherein each golden key section has a reference position and a section length.This golden key transfer approach also comprises the section length according to this little golden key section, the transmission length of setting each golden key section corresponding; And according to belonging to the beginning position of this little golden key section and transmission length, from the position of golden key, assign the transmission bit string belonging to each golden key section.This golden key transfer approach also comprises a little golden key section for this reason and determines a transmission order; And according to this transmission order, be sent to encryption/decryption element from memory buffer via data bus by belonging to the reference position of each golden key section, section length and transmission bit string.

In one embodiment of this invention, the above-mentioned step of golden key section that is logically divided into the position of golden key comprises: the position of golden key is divided into multiple golden key section, and wherein the section length of each golden key section is identical and the transmission length of each golden key section is same as the section length of each golden key section.

In one embodiment of this invention, the above-mentioned step of golden key section that is logically divided into the position of golden key comprises: the position of golden key is divided into randomly multiple golden key section, and the section length of at least two golden key sections wherein among this little golden key section is different.

In one embodiment of this invention, the above-mentioned step for these golden key sections decision transmission orders comprises decision transmission order in a random basis.

In one embodiment of this invention, above-mentioned according to each golden key section and section length, the step of the transmission length of setting each golden key section corresponding comprises: the transmission length setting each golden key section corresponding according to the section length of length and each golden key section of golden key in a random basis.

In one embodiment of this invention, above-mentioned golden key transfer approach, also comprises: after golden key, add at least one virtual golden key.In addition, the above-mentioned section length according to each golden key section, the step of the transmission length of setting each golden key section corresponding comprises: according to the section length of the length of golden key, the length of virtual golden key and each golden key section.

In one embodiment of this invention, golden key transfer approach, also comprises: reconfigure in encryption/decryption element belong to this little golden key section reference position, section length and transmission bit string to obtain this golden key.

In one embodiment of this invention, above-mentioned encryption/decryption element comprises home location register, section length register, transmission bit string register and golden key register.In addition, above-mentioned according to transmission order, comprise belonging to the step that the reference position of each golden key section, section length and this transmission bit string be sent to encryption/decryption element from memory buffer via data bus: the reference position belonging to this little golden key section is sent to home location register via bus; The transmission length belonging to this little golden key section is sent to section length register via data bus; And the transmission bit string belonging to this little golden key section is sent to transmission bit string register via data bus.

In one embodiment of this invention, above-mentioned reconfigure in the encryption/decryption element reference position, section length and the transmission bit string that belong to this little golden key section comprise with the step obtaining this golden key: read with transmission bit string register the reference position, section length and the transmission bit string that belong to this little golden key section from the home location register encryption/decryption element, section length register respectively, obtain this golden key according to the read reference position belonging to this little golden key section, section length and transmission bit string, and obtained golden key is write in golden key register.

In one embodiment of this invention, above-mentioned according to belonging to the reference position of each golden key section, transmission length and one transmit step that bit string is reassembled into golden key comprise from the home location register encryption/decryption element, section length register and transmit bit string register read respectively belong to each golden key section reference position, transmit length and one and transmit bit string, and be reassembled into golden key.

Exemplary embodiment of the present invention proposes a kind of Memory Controller, and for controlling reproducible nonvolatile memorizer module, this Memory Controller comprises host interface, memory interface, memory buffer, encryption/decryption element and memory management circuitry.Host interface is electrically connected to host computer system; Memory interface is electrically connected to reproducible nonvolatile memorizer module; Memory buffer is in order to temporary golden key; Encryption/decryption element, carrys out encrypt and decrypt data in order to utilize this golden key; And memory management circuitry is electrically connected to host interface and memory interface, in order to this golden key is sent to encryption/decryption element from memory buffer via data bus.Multiple positions of golden key are logically divided into multiple golden key section by this memory management circuitry, and wherein each golden key section has reference position and section length.In addition, memory management circuitry is according to the section length of each golden key section, the transmission length of setting each golden key section corresponding, and according to belonging to the reference position of each golden key section and transmission length, from the position of golden key, assign the transmission bit string belonging to each golden key section.Moreover memory management circuitry for this reason a little golden key section determines transmission order, and according to this transmission order, be sent to encryption/decryption element from memory buffer via data bus by belonging to the reference position of each golden key section, section length and transmission bit string.

In one embodiment of this invention, the position of golden key is divided into above-mentioned golden key section by above-mentioned memory management circuitry, and wherein the section length of each golden key section is identical and the transmission length of each golden key section is same as the section length of each golden key section.

In one embodiment of this invention, the position of golden key is divided into above-mentioned golden key section by above-mentioned memory management circuitry randomly, and wherein the section length of at least two golden key sections is different.

In one embodiment of this invention, above-mentioned memory management circuitry determines this transmission order in a random basis.

In one embodiment of this invention, above-mentioned memory management circuitry sets the transmission length of each golden key section corresponding in a random basis according to the section length of the length of golden key and each golden key section.

In one embodiment of this invention, above-mentioned memory management circuitry adds at least one virtual golden key and sets the transmission length of each golden key section corresponding according to the length of golden key, the length of virtual golden key and the section length of each golden key section in a random basis after golden key.

In one embodiment of this invention, above-mentioned encryption/decryption element reconfigure belong to each golden key section a little reference positions, section length and transmission bit string to obtain golden key.

In one embodiment of this invention, above-mentioned encryption/decryption element has home location register, section length register, transmission bit string register and golden key register.In addition, the reference position belonging to each golden key section is sent to home location register via data bus by above-mentioned memory management circuitry, the section length belonging to each golden key section is sent to section length register via data bus and the transmission bit string belonging to each golden key section is sent to transmission bit string register via data bus.

In one embodiment of this invention, above-mentioned encryption/decryption element also comprises an encryption and decryption controller, wherein this encryption and decryption controller reads with transmission bit string register the reference position, section length and the transmission bit string that belong to each golden key section from home location register, section length register respectively, obtain golden key according to the read reference position belonging to each golden key section, section length and transmission bit string, and obtained golden key is write in golden key register.

Exemplary embodiment of the present invention proposes a kind of memorizer memory devices, comprises connector, reproducible nonvolatile memorizer module and above-mentioned Memory Controller.Connector is electrically connected to host computer system; Reproducible nonvolatile memorizer module is in order to storage data; And Memory Controller is electrically connected to connector and reproducible nonvolatile memorizer module.

Based on above-mentioned, golden key transfer approach provided by the present invention, Memory Controller and memorizer memory devices can prevent golden key to be stolen in the process being transferred into encryption/decryption element from memory buffer.

For making above-mentioned feature and advantage of the present invention become apparent, special embodiment below, and be described with reference to the accompanying drawings as follows.

Accompanying drawing explanation

Fig. 1 is the schematic diagram of the transmission gold key illustrated according to prior art.

Fig. 2 A is the host computer system and memorizer memory devices that illustrate according to exemplary embodiment of the present invention.

Fig. 2 B is the schematic diagram of computing machine, input/output device and the memorizer memory devices illustrated according to exemplary embodiment of the present invention.

Fig. 2 C is the schematic diagram of host computer system and the memorizer memory devices illustrated according to exemplary embodiment of the present invention.

Fig. 3 is the schematic block diagram illustrating the memorizer memory devices shown in Fig. 2 A.

Fig. 4 is the schematic block diagram of the Memory Controller illustrated according to exemplary embodiment of the present invention.

Fig. 5 A is the running schematic diagram of the golden key transfer approach illustrated according to the present invention first exemplary embodiment

Fig. 5 B is the list of relevant information golden key being logically divided into multiple golden key section illustrated according to Fig. 5 A.

Fig. 6 is the process flow diagram of the golden key transfer approach illustrated according to the present invention first exemplary embodiment.

Fig. 7 A is the running schematic diagram of the golden key transfer approach illustrated according to the present invention second exemplary embodiment.

Fig. 7 B is the list of relevant information golden key being logically divided into multiple golden key section illustrated according to Fig. 7 A.

Fig. 8 is the process flow diagram of the golden key transfer approach illustrated according to the present invention second exemplary embodiment.

Fig. 9 A is the running schematic diagram of the golden key transfer approach illustrated according to the present invention the 3rd exemplary embodiment.

Fig. 9 B is the list of relevant information golden key being logically divided into multiple golden key section illustrated according to Fig. 9 A.

Figure 10 is the process flow diagram of the golden key transfer approach illustrated according to the present invention the 3rd exemplary embodiment.

Figure 11 A is the running schematic diagram of the golden key transfer approach illustrated according to the present invention the 4th exemplary embodiment.

Figure 11 B is the schematic diagram of the transmission length of each golden key section of decision illustrated according to Figure 11 A.

Figure 11 C is the list of relevant information golden key being logically divided into multiple golden key section illustrated according to Figure 11 A.

Figure 12 is the process flow diagram of the golden key transfer approach illustrated according to the present invention the 4th exemplary embodiment.

Figure 13 A is the running schematic diagram of the golden key transfer approach illustrated according to the present invention the 4th exemplary embodiment.

Figure 13 B is the schematic diagram of the transmission length of each golden key section of decision illustrated according to Figure 13 A.

Figure 13 C is the list of relevant information golden key being logically divided into multiple golden key section illustrated according to Figure 13 A.

Figure 14 is the process flow diagram of the golden key transfer approach illustrated according to the present invention the 5th exemplary embodiment.

Reference numeral explanation

1000: host computer system

1100: computing machine

1102: microprocessor

1104: random access memory

1106: input/output device

1108: system bus

1110: data transmission interface

1202: mouse

1204: keyboard

1206: display

1208: printer

1212: portable disk

1214: storage card

1216: solid state hard disc

1310: digital camera

1312:SD card

1314:MMC card

1316: memory stick

1318:CF card

1320: embedded storage device

100: memorizer memory devices

102: connector

104: Memory Controller

106: reproducible nonvolatile memorizer module

202: memory management circuitry

204: host interface

206: memory interface

252: memory buffer

254: electric power management circuit

256: bug check and correcting circuit

1,258: encryption/decryption element

1a, 252a: golden key

252b: virtual golden key

258a: golden key register

258b: home location register

258c: section length register

258d: transmission bit string register

304 (0) ~ 304 (R): physical blocks

401: data bus

501 ~ 504: golden key section

701 ~ 704: golden key section

901 ~ 904: golden key section

1151 ~ 1154: golden key section

1351 ~ 1354: golden key section

P1 ~ P4: the reference position of golden key section

L1 ~ L4: the transmission length of golden key section

S601, S603, S605, S607, S609, S611, S801, S1007, S1203, S1403: the step transmitting golden key

Embodiment

[the first exemplary embodiment]

Generally speaking, memorizer memory devices (also known as, memory storage system) comprises reproducible nonvolatile memorizer module and controller (also known as, control circuit).Usual memorizer memory devices uses together with host computer system, data can be write to memorizer memory devices or read data from memorizer memory devices to make host computer system.

Please refer to Fig. 2 A, host computer system 1000 generally comprises computing machine 1100 and I/O (input/output, I/O) device 1106.Computing machine 1100 comprises microprocessor 1102, random access memory (random access memory, RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises as the mouse 1202 of Fig. 2 B, keyboard 1204, display 1206 and printer 1208.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Fig. 2 B, input/output device 1106 can also comprise other devices.

In embodiments of the present invention, memorizer memory devices 100 is electrically connected by data transmission interface 1110 other elements with host computer system 1000.By the running of microprocessor 1102, random access memory 1104 and input/output device 1106, data can be write to memorizer memory devices 100 or read data from memorizer memory devices 100 by host computer system 1000.Such as, memorizer memory devices 100 can be the type nonvolatile storage devices such as portable disk 1212, storage card 1214 or solid state hard disc (Solid State Drive, SSD) 1216 as shown in Figure 2 B.

Generally speaking, host computer system 1000 can be any system that can coordinate with memorizer memory devices 100 with storage data substantially.Although in this exemplary embodiment, host computer system 1000 illustrates with computer system, but in another exemplary embodiment of the present invention, host computer system 1000 can be the systems such as digital camera, video camera, communicator, reproducing apparatus for phonotape or video signal player.Such as, when host computer system is digital camera (video camera) 1310, type nonvolatile storage device is then its SD card 1312 used, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or embedded storage device 1320 (as shown in Figure 2 C).Embedded storage device 1320 comprises embedded multi-media card (Embedded MMC, eMMC).It is worth mentioning that, embedded multi-media card is directly electrically connected on the substrate of host computer system.

Please refer to Fig. 3, memorizer memory devices 100 comprises connector 102, Memory Controller 104 and reproducible nonvolatile memorizer module 106.

In this exemplary embodiment, connector 102 is compatible to advanced annex (Serial Advanced Technology Attachment, the SATA) standard of sequence.But, it must be appreciated, the present invention is not limited thereto, connector 102 can also be meet Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standards, parallel advanced annex (Parallel Advanced Technology Attachment, PATA) standard, high-speed peripheral component connecting interface (PeripheralComponent Interconnect Express, PCI Express) standard, universal serial bus (Universal Serial Bus, USB) standard, secure digital (Secure Digital, SD) interface standard, memory stick (Memory Stick, MS) interface standard, Multi Media Card (Multi Media Card, MMC) interface standard, compact flash (Compact Flash, CF) interface standard, integrated driving electrical interface (Integrated Device Electronics, IDE) standard or other standards be applicable to.

Memory Controller 104 in order to perform with multiple logic gate of hardware pattern or firmware pattern implementation or steering order, and according to the instruction of host computer system 1000 carry out in reproducible nonvolatile memorizer module 106 data write, read and the running such as to erase.

Reproducible nonvolatile memorizer module 106 is electrically connected to Memory Controller 104, and in order to store the data that host computer system 1000 writes.Reproducible nonvolatile memorizer module 106 comprises physical blocks 304 (0) ~ 304 (R).Each physical blocks has multiple physical page respectively, and the physical page wherein belonged in same physical blocks can be written independently and side by side be erased.In more detail, physical blocks is the least unit of erasing.That is, each physical blocks contain minimal amount in the lump by the storage unit of erasing.Physical page is the minimum unit of programming.That is, physical page is the minimum unit of write data.In this exemplary embodiment, reproducible nonvolatile memorizer module 106 is multi-level cell memory (Multi Level Cell, MLC) NAND quick-flash memory module.But, the present invention is not limited thereto, reproducible nonvolatile memorizer module 106 also single-order storage unit (Single Level Cell, SLC) NAND quick-flash memory module, other flash memory module or there are other memory modules of identical characteristics.

Please refer to Fig. 4, Memory Controller 104 comprises memory management circuitry 202, host interface 204 and memory interface 206.

Memory management circuitry 202 is in order to the overall operation of control store controller 104.Specifically, memory management circuitry 202 has multiple steering order, and when memorizer memory devices 100 operates, these steering orders can be performed to carry out data write, read and the running such as to erase.

Specifically, the steering order of memory management circuitry 202 is stored in the specific region (such as, being specifically designed to the system region of storage system data in reproducible nonvolatile memorizer module 106) of reproducible nonvolatile memorizer module 106 with the pattern of procedure code.In addition, memory management circuitry 202 has microprocessor unit (not illustrating), ROM (read-only memory) (not illustrating) and random access memory (not illustrating).Particularly, this ROM (read-only memory) has driving code section, and when Memory Controller 104 is enabled, microprocessor unit first can perform this and drive code section the steering order be stored in reproducible nonvolatile memorizer module 106 to be loaded in the random access memory of memory management circuitry 202.Afterwards, microprocessor unit can operate these steering orders with perform data write, read and the running such as to erase.In addition, in another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 a hardware pattern can also carry out implementation.

Host interface 204 is electrically connected to memory management circuitry 202 and in order to receive and to identify the instruction that transmits of host computer system 1000 and data.That is, the instruction that transmits of host computer system 1000 and data can be sent to memory management circuitry 202 by host interface 204.In this exemplary embodiment, host interface 204 is compatible to SATA standard.But, it must be appreciated and the present invention is not limited thereto, host interface 204 can also be compatible to PATA standard, IEEE 1394 standard, PCI Express standard, USB standard, SD standard, MS standard, MMC standard, CF standard, IDE standard or other data transmission standards be applicable to.

Memory interface 206 is electrically connected to memory management circuitry 202 and in order to access reproducible nonvolatile memorizer module 106.That is, the data for writing to reproducible nonvolatile memorizer module 106 can be converted to the receptible form of reproducible nonvolatile memorizer module 106 via memory interface 206.

In the present invention one exemplary embodiment, Memory Controller 104 also comprises memory buffer 252.Memory buffer 252 is electrically connected to memory management circuitry 202 and comes from the data and instruction of host computer system 1000 in order to temporary or come from the data of reproducible nonvolatile memorizer module 106.Particularly, before encryption/decryption element 258 comes into operation, golden key according to the golden key transfer approach of this exemplary embodiment, can be sent to encryption/decryption element 258 by memory management circuitry 202 from memory buffer 252.

In the present invention one exemplary embodiment, Memory Controller 104 also comprises electric power management circuit 254.Electric power management circuit 254 is electrically connected to memory management circuitry 202 and in order to the power supply of control store storage device 100.

In the present invention one exemplary embodiment, Memory Controller 104 also comprises bug check and correcting circuit 256.Bug check and correcting circuit 256 be electrically connected to memory management circuitry 202 and in order to execution error position inspection with correct with the correctness guaranteeing data.Specifically, when memory management circuitry 202 receives write instruction from host computer system 1000, bug check and correcting circuit 256 can be that the corresponding data that this writes instruction produce corresponding bug check and correcting code (Error Checking and Correcting Code, ECC Code), and the data of this write instruction corresponding can write in reproducible nonvolatile memorizer module 106 with corresponding bug check and correcting code by memory management circuitry 202.Afterwards, can read bug check corresponding to these data and correcting code when memory management circuitry 202 reads data from reproducible nonvolatile memorizer module 106, and bug check and correcting circuit 256 can according to this bug check and correcting code to the inspection of read data execution error position and corrections simultaneously.

In the present invention one exemplary embodiment, Memory Controller 104 also comprises encryption/decryption element 258, encryption/decryption element 258 is electrically connected to memory management circuitry 202, in order to encrypt the data writing to reproducible nonvolatile memorizer module 106 according to golden key, and the data that deciphering is read from reproducible nonvolatile memorizer module 106.

In the present embodiment, encryption and decryption function in encryption/decryption element 258 can Advanced Encryption Standard (Advanced Encryption Standard, AES) carry out implementation, data encryption standards (Data Encryption Standard, DES) implementation can also be carried out.

In this exemplary embodiment, before encryption/decryption element 258 carries out the encryption of data, the golden key be temporary in memory buffer 252 can carry out being divided into multiple golden key section and send the golden key section after segmentation and relevant information thereof to encryption/decryption element 258 via data bus by memory management circuitry 202.

Fig. 5 A is the running schematic diagram of the golden key transfer approach illustrated according to the present invention first exemplary embodiment, and Fig. 5 B is the list of relevant information golden key being logically divided into multiple golden key section illustrated according to Fig. 5 A.For simplifying and clearly demonstrate the operation situation of golden key transfer approach, suppose that golden key 252a only comprises 16 positions at this, but it must be appreciated, the present invention is not limited thereto.

As shown in Figure 5A, in this example, (namely golden key 252a can be divided into golden key section by memory management circuitry 202 in order, gold key section 501 ~ 504), wherein each golden key section has the attribute such as reference position and section length, to record the reference position of golden key section in this golden key and length.

As shown in Figure 5 B, in the list of relevant information of golden key section, first hurdle represents the numbering of golden key section, second hurdle represents the reference position (each golden key section is from which position in golden key) of golden key section, third column represents the section length (figure place of each golden key section) of golden key section respectively, 4th hurdle is the transmission length of each golden key section, and the 5th hurdle is the transmission bit string of each golden key section and the 6th hurdle is the sequencing that each golden key section will be sent to encryption/decryption element 258.At this, transmission length is the length representing the data that each golden key section transmits in data bus 401, and transmission bit string is the content representing the data that each golden key section transmits in data bus 401.

Please refer to Fig. 5 A, encryption/decryption element 258 comprises golden key register 258a, home location register 258b, section length register 258c, transmission bit string register 258d and encryption and decryption controller 258e.At this, gold key register 258a is in order to deposit last the obtained golden key 252a of encryption/decryption element 258, home location register 258b is in order to deposit the reference position of each golden key section, section length register 258c is in order to deposit the section length of each golden key section, and transmission bit string register 258d is in order to deposit the transmission bit string of each golden key section.

In golden key transport process, memory management circuitry 202 can the reference position of corresponding golden key section 501 ~ golden key section 504, section length and transmission bit string, write home location register 258b, section length register 258c and transmission bit string register 258d respectively.After completing golden key and transmitting, encryption/decryption element 258 can reduce original golden key 252a according to the content being stored in these three registers, and it is stored in golden key register 258a by reduced golden key 252a.

Please with reference to Fig. 5 A and Fig. 5 B.Specifically, before being transferred into encryption/decryption element 258, golden key 252a can first be temporarily stored in memory buffer 252.Then, 16 positions of golden key 252a are logically divided into golden key section 501 ~ golden key section 504 in the mode of regular length (4 positions) by memory management circuitry 202, and are respectively reference position and section length that each golden key section calculates correspondence.Wherein, the reference position P1 ~ P4 of golden key section 501 ~ golden key section 504 is 1,5,9 and 13 respectively, and the length of golden key section 501 ~ golden key section 504 is then all 4 (as shown in the third columns in Fig. 5 B).

Then, memory management circuitry 202, according to the section length of each golden key section, is respectively each golden key section setting one transmission length.At this, the transmission length of a corresponding golden key section is not less than the section length of this golden key section.In the first exemplary embodiment, memory management circuitry 202 is the transmission length using the length of golden key section itself as correspondence, in other words, the transmission length of golden key section 501 ~ golden key section 504 is all 4 (as shown in the 4th hurdles in Fig. 5 B).

Then, memory management circuitry 202, according to the reference position of each golden key section and transmission length, assigns the transmission bit string of each golden key section from the golden key 252a memory buffer 252.Specifically, (namely memory management circuitry 202 can read 4 place values from the reference position of golden key section 501, ' 1010 ') as the transmission bit string of golden key section 501, 4 place values are read (namely from the reference position of golden key section 502, ' 1000 ') as the transmission bit string of golden key section 502, 4 place values are read (namely from the reference position of golden key section 503, ' 0101 ') as golden key section 503 transmission bit string and from the reference position of golden key section 504, read 4 place values (namely, ' 0111 ') as the transmission bit string (as shown in the 5th hurdle of Fig. 5 B) of golden key section 504.

Then, memory management circuitry 202 is that each golden key section determines a transmission order, and according to this transmission order, the reference position of each golden key section, section length and transmission bit string are sent to respectively the home location register 258b on encryption/decryption element 258, section length register 258c with transmission bit string register 258d.In this exemplary embodiment, the sequencing of memory management circuitry 202 using each golden key section position in golden key 252a is as the transmission order of correspondence.In other words, the transmission order of each golden key section is golden key section 501, golden key section 502, golden key section 503, is then golden key section 504.

Finally, after the transmission completing golden key, the encryption and decryption controller 258e of encryption/decryption element 258 can reconfigure the reference position of each golden key section, section length and transmission bit string to obtain golden key.

Accordingly, in the process that golden key transmits, the content (that is, transmitting bit string) of each golden key section can be interted, so the content of golden key can not occur on the data bus uninterruptedly mutually with the reference position of each golden key section and section length.Base this, third party's direct detection data bus can be avoided or made a variation by measure energy and obtain the content of golden key easily.

It must be appreciated, in this exemplary embodiment, the length of golden key 252a is 16.But the present invention is not limited to this, in another exemplary embodiment of the present invention, the length of golden key 252a also can be other length such as 64,128 or 256 positions.In principle, golden key length depends on used encryption and decryption standard.

In addition, in this exemplary embodiment, golden key 252a is logically divided into 4 golden key sections by memory management circuitry 202.But it must be appreciated, golden key 252a also can be logically divided into more or less golden key section by memory management circuitry 202.

Please refer to Fig. 6, first, in step s 601, golden key is logically divided into multiple golden key section (such as by memory management circuitry 202,4 length are the golden key section of 4 positions), and identify the reference position (such as, the reference position of 4 golden key sections is respectively 1,5,9 and 13) of each golden key section and section length (such as, the length of 4 golden key sections is all 4).Then, in step S603, memory management circuitry 202 is according to the transmission length (such as, the transmission length of 4 golden key sections is all 4) of the corresponding each golden key section of section length setting of each golden key section.

Then, in step s 605, memory management circuitry 202, according to the reference position of each golden key section and transmission length, assigns the transmission bit string of each golden key section from the position of the golden key be stored in memory buffer 252.

Then, in step S607, memory management circuitry 202 determines transmission order with the sequencing of each golden key section position in golden key.Then, in step S609, the reference position of each golden key section, section length and transmission bit string, according to the transmission order determined in step S607, are sent to encryption/decryption element 258 by memory management circuitry 202.Particularly, the reference position of each golden key section, section length and transmission bit string can be written into home location register 258b respectively, section length register 258c and transmission bit string register 258d.

It must be appreciated, in the process transmitting each golden key section, the reference position of golden key section, the order between section length and transmission bit string three there is no specific restriction.

Finally, in step s 611, after the reference position of each golden key section, section length and transmission bit string are all transferred into encryption/decryption element 258, encryption and decryption controller 258e reconfigures the reference position of each golden key section, section length and transmission bit string with the golden key 252a obtained.

[the second exemplary embodiment]

The Memory Controller of the present invention second exemplary embodiment and memorizer memory devices are same as Memory Controller and the memorizer memory devices of the first exemplary embodiment in essence, and difference wherein is only that the second exemplary embodiment logically splits the golden key that send of tendency to develop by different way.More particularly, multiple positions of golden key can be logically divided into the multiple golden key section with different section length by the second exemplary embodiment randomly.Because each golden key section has on-fixed section length, the third party is thus allowed more to be difficult to direct detection data bus or to be made a variation by measure energy and obtain golden key content.The difference part will using Fig. 7 A and Fig. 7 B that the second exemplary embodiment and the first exemplary embodiment are described below.

Fig. 7 A is the running schematic diagram of the golden key transfer approach illustrated according to the present invention second exemplary embodiment and Fig. 7 B is the list of relevant information golden key being logically divided into multiple golden key section illustrated according to Fig. 7 A.At this, suppose that the length of golden key 252a is identical with the second exemplary embodiment with content.

Please with reference to Fig. 7 A and Fig. 7 B.Specifically, 16 positions of golden key 252a are logically divided into the golden key section 501 ~ golden key section 504 of different length by memory management circuitry 202 in a random basis, and identify reference position and the section length of each golden key section.Such as, suppose that memory management circuitry 202 is for being divided into golden key section 701 ~ golden key section 704 by 16 positions of golden key 252a, for this reason, the start position setting of golden key section 701 can be first 1 by memory management circuitry 202, and produce random random number between three 1 to 16 (such as, utilize random random number generator), the ascending reference position respectively as golden key section 702 ~ golden key section 704.

From Fig. 7 A and Fig. 7 B, in this exemplary embodiment, the reference position P1 ~ P4 of golden key section 701 ~ golden key section 704 is respectively 1,6,9 and 15.Accordingly, the section length that memory management circuitry 202 identifiable design goes out golden key section 701 ~ golden key section 704 is respectively 5,3,6 and 2 (as shown in the third columns in Fig. 5 B).

Then, memory management circuitry 202 is according to the section length of each golden key section, and the transmission length of the corresponding each golden key section of setting, wherein transmits the length that length is not less than golden key section itself.In this exemplary embodiment, memory management circuitry is using the section length of golden key section as the transmission length of correspondence, in other words, the transmission length of golden key section 701 ~ golden key section 704 is respectively 5,3,6 and 2 (as shown in the 4th hurdles in Fig. 5 B).

Then, memory management circuitry 202, according to the reference position of each golden key section and transmission length, assigns the transmission bit string of each golden key section among the golden key 252a memory buffer 252.Specifically, (namely memory management circuitry 202 can read 5 place values from the reference position of golden key section 701, ' 10101 ') as the transmission bit string of golden key section 701, 3 place values are read (namely from the reference position of golden key section 702, ' 000 ') as the transmission bit string of golden key section 702, 6 place values are read (namely from the reference position of golden key section 703, ' 010101 ') as golden key section 703 transmission bit string and from the reference position of golden key section 704, read 2 place values (namely, ' 11 ') as the transmission bit string (as shown in the 5th hurdle in Fig. 7 B) of golden key section 704.

Then, memory management circuitry 202 is that each golden key section determines transmission order and transmits the reference position of each golden key section, section length and transmission bit string according to this transmission order.Determine that transmission order is be same as the first exemplary embodiment with the mode transmitting the reference position of each golden key section, section length and transmission bit string, do not repeat them here.

Accordingly, in the process that golden key transmits, not only the content of each golden key section can be interted with the information of corresponding section length mutually with the reference position of each golden key section, and the length of each golden key section is random value, so compared to the first exemplary embodiment, the related content of each golden key section can occur on the data bus with more irregular form.Base this, the third party can be avoided to obtain the content of golden key easily by detection data bus or measure energy variation.

Please refer to Fig. 8, except step S801, all the other steps have been described in the first exemplary embodiment, do not repeat them here.Below only explain with regard to step S801.

In step S801, golden key is logically divided into the golden key section with different section length by memory management circuitry 202 in a random basis, and identifies reference position and the section length of each golden key section.Such as, can be first 1 by the start position setting of golden key section 701, and produce the random random number between three 1 to 16, the ascending reference position respectively as golden key section 702 ~ golden key section 704, then identify the section length of each golden key section according to this.

But it must be appreciated, the present invention is not limited to this, in another embodiment of the invention, also first can produce the section length of random random number as each golden key section, then identify the reference position of each golden key section more according to this.Specifically, the random random number that 4 summations are 16 is first produced, such as, 5,3,6 and 2, then be 1 by the start position setting of golden key section 701, and then identify the reference position of golden key section 702 ~ golden key section 704 successively according to above-mentioned 4 random random numbers, be respectively 6,9 and 15.

[the 3rd exemplary embodiment]

The Memory Controller of the present invention the 3rd exemplary embodiment and memorizer memory devices are same as Memory Controller and the memorizer memory devices of the second exemplary embodiment in essence, and difference wherein is only that the 3rd exemplary embodiment determines the transmission order of each golden key section by different way.More particularly, the 3rd exemplary embodiment determines the transmission order of each golden key section in a random basis.Therefore, except having unfixed length, each golden key section occurs on the data bus with unfixed order, thus allows the third party more be difficult to direct detection data bus or made a variation by measure energy and obtain golden key content.

Fig. 9 A is the running schematic diagram of the golden key transfer approach illustrated according to the present invention the 3rd exemplary embodiment, and Fig. 9 B is the list of relevant information golden key being logically divided into multiple golden key section illustrated according to Fig. 9 A.

Please with reference to Fig. 9 A and Fig. 9 B, as previously mentioned, golden key, to be same as the mode of the second exemplary embodiment, to be logically divided into 4 golden key sections and the transmission length of setting correspondence, not repeat them here by the 3rd exemplary embodiment.Unique difference is only, the 3rd exemplary embodiment determines the transmission order of golden key section 901 ~ golden key section 904 in a random way.Such as, memory management circuitry 202 can be respectively golden key section 901 ~ golden key section 904 and produce 4 random random numbers, then determines the transmission order of golden key section 901 ~ golden key section 904 according to size order.

From Fig. 9 B, in this exemplary embodiment, the transmission of each golden key section order is golden key section 902, golden key section 904, golden key section 901, be then golden key section 903.Then, the reference position of each golden key section, section length and transmission bit string, according to this transmission order, are sent to encryption/decryption element 258 by memory management circuitry 202.

Accordingly, not only the section length of each golden key section is random value, and its transmission order is also arranged in golden key sequencing with golden key section has nothing to do, so compared to the second exemplary embodiment, the content of each golden key section can occur on the data bus with more irregular form.Base this, the third party can be avoided to obtain the content of golden key easily by detection data bus or measure energy variation.

Please refer to Figure 10, except step S1007, all the other steps have been described in the second exemplary embodiment and the 3rd exemplary embodiment, do not repeat them here.Below only explain with regard to step S1007.

In step S1007, memory management circuitry 202 determines the transmission order of golden key section in a random basis.Such as, in this exemplary embodiment, memory management circuitry 202 first produce 4 belong to respectively in golden key section 901 ~ golden key section 904 random random number (such as, ' 3 ', ' 1 ', ' 4 ' and ' 2 '), more according to this order is as the transmission order of golden key section 901 ~ golden key section 904.That is memory management circuitry 202 first transmits golden key section 902, then transmit golden key section 904 again, golden key section 901, with golden key section 903.

It is worth mentioning that, although in the 3rd exemplary embodiment, multiple positions of golden key logically can be divided into the multiple golden key section with different section length randomly, the present invention is not limited thereto.Such as, in another exemplary embodiment, multiple positions of golden key logically also can be divided into the multiple golden key section with same sector length, and afterwards, the transmission order that the transmission bit string of golden key section determines in a random basis is again transmitted.

[the 4th exemplary embodiment]

The Memory Controller of the present invention the 4th exemplary embodiment and memorizer memory devices are same as Memory Controller and the memorizer memory devices of the 3rd exemplary embodiment in essence, and difference wherein is only that the 4th exemplary embodiment sets the transmission length of corresponding each golden key section by different way.More particularly, the 4th exemplary embodiment sets the transmission length of corresponding each golden key section in a random way, and the transmission length of each golden key section is not less than the length of each golden key section itself.Base this, except each golden key section has except unfixed section length, the transmission data string of each golden key section also can overlap mutually.Particularly, in the first exemplary embodiment in the 3rd exemplary embodiment, each position of golden key only can be transfused to once, but in the 4th exemplary embodiment, the golden key content of part may be transfused to more than twice.So, greatly can increase the degree of difficulty that subaisle attacks (side channel attack), thus allow the third party more be difficult to be obtained by detection data bus or measure energy variation the content of golden key.The place will using Figure 11 A ~ Figure 11 C that the difference of the 4th exemplary embodiment and the 3rd exemplary embodiment is described below.

Figure 11 A is the running schematic diagram of the golden key transfer approach illustrated according to the present invention the 3rd exemplary embodiment, and Figure 11 B is the schematic diagram of the transmission length for determining each golden key section illustrated according to Figure 11 A and Figure 11 C is the list of relevant information golden key being logically divided into multiple golden key section illustrated according to Figure 11 A.

Please with reference to Figure 11 A ~ Figure 11 C, as previously mentioned, golden key, to be same as the mode of the 3rd exemplary embodiment, is logically divided into 4 golden key sections by the 4th exemplary embodiment, and determines the transmission order of each golden key section, does not repeat them here.Unique difference is only that the 4th exemplary embodiment sets the transmission length of corresponding golden key section 1151 ~ golden key section 1154 in a random way.

In this exemplary embodiment, for the golden key section not being last golden key section, memory management circuitry 202 can set the transmission length of golden key section according to formula (1):

L(i)＝rand(P(i+1)-P(i)，N-P(i)) (1)

Wherein L (i) is the transmission length of i-th golden key section; Rand (a, b) is random function, random integers between passback integer a to integer b; P (i) is the reference position of i-th golden key section; P (i+1) is the reference position of the i-th+1 golden key section; And N is the figure place of golden key.

In this exemplary embodiment, for last golden key section, memory management circuitry 202 can calculate the transmission length of golden key section according to formula (2):

L(m)＝N-P(m)+1 (2)

Wherein m is the sum of golden key section; L (m) is the transmission length of m golden key section (last golden key section); P (m) is the reference position of m golden key section; And N is the figure place of golden key.

That is, above formula (1) and formula (2) set the transmission length of each golden key section corresponding in a random basis, the transmission length of any one golden key section is made to be more than or equal to the section length of this golden key section itself and difference between the reference position of the length being not more than golden key golden key section therewith itself adds 1 (that is, (P (i+1)-P (i)) <=L (i) <=(N-P (i)+1)).

Such as, in this exemplary embodiment, N is 16, m be 4, P (1) be 1, P (2) be 6, P (3) be 9, P (4) is 15.According to formula (1), L (1) is the random integers (that is, L (1)=rand (6-1,16-1)=rand (5,15)) between 5 ~ 15.In like manner, L (2) be random integers between 3 ~ 10 (namely, L (2)=rand (9-6,16-6)=rand (3,10)) and L (3) be random integers between 6 ~ 7 (namely, L (3)=rand (15-9,16-9)=rand (6,7)).Again according to formula (2), L (4) is 2 (that is, L (4)=16-15+1=2).Particularly, from Figure 11 B, in this exemplary embodiment, through the random function of formula (1) and calculating of formula (2), transmission length L1 (i.e. L (1)) is 7, transmission length L2 (i.e. L (2)) is 6, and transmission length L3 (i.e. L (3)) is 7, and transmission length L4 (i.e. L (4)) is 2.But, it should be noted that transmission length L1 is the random value that random function produces to transmission length L3, instead of fixed value.

After the transmission length setting each golden key section, memory management circuitry 202, according to the reference position of each golden key section and transmission length, assigns the transmission bit string of each golden key section among the golden key 252a memory buffer 252.Specifically, (namely memory management circuitry 202 can read 7 place values from the reference position of golden key section 1151, ' 1010100 ') as the transmission bit string of golden key section 1151, 6 place values are read (namely from the reference position of golden key section 1152, ' 000010 ') as the transmission bit string of golden key section 1152, 7 place values are read (namely from the reference position of golden key section 1153, ' 0101011 ') as golden key section 1153 transmission bit string and from the reference position of golden key section 1154, read 2 place values (namely, ' 11 ') as the transmission bit string (as shown in the 5th hurdle of Figure 11 C) of golden key section 1154.

Then, memory management circuitry 202, to be same as the mode of the 3rd exemplary embodiment, is that each golden key section determines transmission order, and transmits the reference position of each golden key section, section length and transmission bit string relevant information according to this.

According to the golden key load mode of the 4th exemplary embodiment, not only the section length of each golden key section is random value, and the sequencing that transmission order and the golden key section of each golden key section are arranged in golden key also has nothing to do.Meanwhile, the transmission length of each golden key section is also random value and is not less than the length of each golden key section, and therefore, the content of each golden key section has the overlapping phenomenon of randomness, and thus, energy information when golden key transmits can further be upset.So compared to the 3rd exemplary embodiment, the content of each golden key section can occur on the data bus with form that is more irregular and that mutually overlap.Base this, the third party can be avoided to obtain the content of golden key easily by detection data bus or measure energy variation.

It must be appreciated, this exemplary embodiment with the formula (1) and formula (2) decides the random transmission length of each golden key section.But, the present invention is not limited to this, as long as the transmission length that each golden key section produces is not less than the length of golden key section itself, and is no more than the length of golden key, in another embodiment of the invention, other random fashions also can be used to decide the random transmission length of each golden key section.

Please refer to Figure 12, except step S1203, all the other steps have been described in the first exemplary embodiment in the 3rd exemplary embodiment, do not repeat them here.Below only explain with regard to step S1203.

In step S1203, memory management circuitry 202 is the transmission length of each golden key section setting correspondence in a random basis.Such as, memory management circuitry 202 first can judge whether the golden key section for being set is last golden key section.If if not during last golden key section, memory management circuitry 202 meeting sets the transmission length corresponding to this golden key section according to above-mentioned formula (1).If when being last golden key section, memory management circuitry 202 meeting sets the transmission length corresponding to this golden key section according to above-mentioned formula (2).

It is worth mentioning that, although in the 4th exemplary embodiment, multiple positions of gold key logically can be divided into the multiple golden key section with different section length randomly, the transmission order of gold key section can decide in a random basis, and the transmission length of golden key section can decide in a random basis, but the present invention is not limited thereto.

Such as, in another exemplary embodiment, multiple positions of gold key logically also can be divided into the multiple golden key section with same sector length, and the transmission order of golden key section can decide with golden putting in order of key section, and the transmission length of golden key section can decide in a random basis.

Again such as, in another exemplary embodiment, multiple positions of gold key logically also can be divided into the multiple golden key section with same sector length, and the transmission order of golden key section can decide in a random basis, and the transmission length of golden key section can decide in a random basis.

Again such as, in another exemplary embodiment, multiple positions of gold key logically also can be divided into the multiple golden key section of tool not same sector length, and the transmission order of golden key section can decide with golden putting in order of key section, and the transmission length of golden key section can decide in a random basis.

[the 5th exemplary embodiment]

The Memory Controller of the present invention the 5th exemplary embodiment and memorizer memory devices are same as Memory Controller and the memorizer memory devices of the 4th exemplary embodiment in essence, and the 5th exemplary embodiment determines the transmission length of each golden key section in the mode of similar 4th exemplary embodiment, difference wherein is only that the 5th exemplary embodiment can continue at least one virtual golden key after real golden key.Therefore, each golden key section, except comprising the golden key content of overlapping mutually, also can comprise the content of extra virtual golden key.So, greatly can increase the degree of difficulty that subaisle attacks (side channel attack), thus allow the third party more be difficult to be obtained by detection data bus or measure energy variation the content of golden key.

Figure 13 A is the running schematic diagram of the golden key transfer approach illustrated according to the present invention the 5th exemplary embodiment, and Figure 13 B is the schematic diagram of the transmission length for determining each golden key section illustrated according to Figure 13 A and Figure 13 C is the list of relevant information golden key being logically divided into multiple golden key section illustrated according to Figure 13 A.

Please with reference to Figure 13 A ~ Figure 13 C.As previously mentioned, golden key, to be same as the mode of the 4th exemplary embodiment, is logically divided into 4 golden key sections by the 5th exemplary embodiment, and determines the transmission order of each golden key section, does not repeat them here.Unique difference is only, although memory management circuitry 202 also sets the transmission length corresponding to golden key section 1351 ~ golden key section 1354 in a random basis in the 5th exemplary embodiment, but, memory management circuitry 202 more continues at least one virtual golden key after real golden key, and the content of at least part of virtual golden key is transmitted together with true golden key.

For asking clear and simplified illustration, in this exemplary embodiment, suppose that the virtual golden key 252b be temporary in memory buffer 252 only comprises 8 positions (its content is as shown in FIG. 13A), and after being connected in real golden key 252a.

In this exemplary embodiment, for the golden key section not being last golden key section, memory management circuitry 202 can set the transmission length of golden key section according to formula (3):

L (i)=rand (P (i+1)-P (i), N+S-P (i)) (formula 3)

Wherein L (i) is the transmission length of i-th golden key section; Rand (a, b) is random function, random integers between passback integer a to integer b; P (i) is the reference position of i-th golden key section; P (i+1) is the reference position of the i-th+1 golden key section; N is the figure place of golden key; And S is the summation of the length of all virtual golden keys.

In this exemplary embodiment, for last golden key section, memory management circuitry 202 can set the transmission length of golden key section according to formula (4):

L (m)=N+S-P (m)+1 (formula 4)

Wherein m is the sum of golden key section; L (m) is the transmission length of m golden key section (last golden key section); P (m) is the reference position of m golden key section; N is the figure place of golden key; And S is the summation of the length of all virtual golden keys.

That is, above formula (3) and formula (4) set the transmission length of each golden key section corresponding in a random basis, the transmission length of any one golden key section is made to be more than or equal to the section length of this golden key section itself, and the difference between the reference position of the summation that the transmission length of any one golden key section is not more than the length of golden key and virtual golden key golden key section therewith itself adds 1 (that is, (P (i+1)-P (i)) <=L (i) <=(N+S-P (i)+1)).

Such as, in this exemplary embodiment, N is 16, S be 8, m be 4, P (1) be 1, P (2) be 6, P (3) be 9, P (4) is 15.According to formula (3), L (1) is the random integers (that is, L (1)=rand (6-1,16+8-1)=rand (5,24)) between 5 ~ 24.In like manner, L (2) be random integers between 3 ~ 18 (namely, L (2)=rand (9-6,16+8-6)=rand (3,18)) and L (3) be random integers between 6 ~ 15 (namely, L (3)=rand (15-9,16+8-9)=rand (6,15)).Be 10 (that is, L (4)=16+8-15+1=10) according to formula 4, L (4) again.Particularly, from Figure 13 B, in this exemplary embodiment, through the random function of formula (3) and calculating of formula (4), transmission length L1 (i.e. L (1)) is 9, transmission length L2 (i.e. L (2)) is 7, and transmission length L3 (i.e. L (3)) is 11, and transmission length L4 (i.e. L (4)) is 10.

After the transmission length of each golden key section of setting, memory management circuitry 202, according to the reference position of each golden key section and transmission length, assigns the transmission bit string of each golden key section among the golden key 252a memory buffer 252.Specifically, (namely memory management circuitry 202 can read 9 place values from the reference position of golden key section 1351, ' 101010000 ') as the transmission bit string of golden key section 1351, 7 place values are read (namely from the reference position of golden key section 1352, ' 0000101 ') as the transmission bit string of golden key section 1352, 11 place values are read (namely from the reference position of golden key section 1353, ' 01010111100 ') as golden key section 1353 transmission bit string and from the reference position of golden key section 1354, read 10 place values (namely, ' 1110010101 ') as the transmission bit string (as shown in the 5th hurdle of Figure 13 C) of golden key section 1354.

Then, memory management circuitry 202, to be same as the mode of the 4th exemplary embodiment, is that each golden key section determines transmission order, and transmits the reference position of each golden key section, section length and transmission bit string relevant information according to this.

Please refer to Figure 14, except step S1403, all the other steps have been described in the first exemplary embodiment in the 3rd exemplary embodiment, do not repeat them here.Below only explain with regard to step S1403.

In step S1403, memory management circuitry 202 can add at least one virtual golden key and be the transmission length of each golden key section setting correspondence in a random basis after golden key.

According to the golden key load mode of this exemplary embodiment, the transmission bit string of each golden key section can comprise the content of virtual golden key randomly, and energy information when can be transmitted by golden key further is thus to upsetting.So compared to the 4th exemplary embodiment, the content of each golden key section can occur on the data bus with more irregular form.Base this, the third party can be avoided to obtain the content of golden key easily by detection data bus or measure energy variation.

It must be appreciated, this exemplary embodiment with the formula (3) and formula (4) decides the random transmission length of each golden key section.But, the present invention is not limited to this, as long as the transmission length of each golden key section life is not less than the length of golden key section itself, and be no more than the length of golden key and virtual golden key, in another embodiment of the invention, other random fashions also can be used to decide the random transmission length of each golden key section.

It is worth mentioning that, although in the 5th exemplary embodiment, multiple positions of gold key logically can be divided into the multiple golden key section with different section length randomly, the transmission order of gold key section can decide in a random basis, and the transmission length of golden key section can decide in a random basis, but the present invention is not limited thereto.Such as, in another exemplary embodiment, multiple positions of gold key logically also can be divided into the multiple golden key section with same sector length, or the transmission order of golden key section can golden putting in order of key section decide, then or the transmission length of golden key section can also be set to regular length.

In sum, the golden key transfer approach of exemplary embodiment of the present invention, Memory Controller and memorizer memory devices can avoid golden key to occur on the data bus with continuous continual form in transport process, allow the third party be able to be obtained easily by detection data bus or measure energy variation the content of golden key.Base this, the security that golden key transmits can be promoted effectively, and the data in memorizer memory devices also can obtain more thorough protection.

Although the present invention discloses as above with embodiment; so itself and be not used to limit the present invention, those skilled in the art, under the premise without departing from the spirit and scope of the present invention; can do some changes and retouching, therefore protection scope of the present invention is as the criterion with claim of the present invention.

Claims

1. a golden key transfer approach, in order to the gold medal key be stored in a memory buffer is sent to an encryption/decryption element via a data bus, this golden key transfer approach comprises:

Multiple positions of this golden key are logically divided into multiple golden key section, and wherein each these golden key section has a reference position and a section length;

According to these section length of these golden key sections, a transmission length of setting each these golden key section corresponding;

According to belonging to this reference positions of these golden key sections and these transmit length, from this golden key these assign the transmission bit string belonging to each these golden key section;

For these golden key sections determine a transmission order; And

According to this transmission order, be sent to this encryption/decryption element from this memory buffer via this data bus by belonging to this reference position of each these golden key section, this section length and this transmission bit string.

2. these of this golden key are wherein logically divided into the step of these golden key sections to comprise by golden key transfer approach as claimed in claim 1:

These positions of this golden key are divided into these golden key sections, wherein these section length of these golden key sections are identical and these transmission length of these golden key sections are same as these section length of these golden key sections.

3. these of this golden key are wherein logically divided into the step of these golden key sections to comprise by golden key transfer approach as claimed in claim 1:

Multiple positions of this golden key are divided into randomly these golden key sections, the section length of at least two golden key sections wherein among these golden key sections is different.

4. golden key transfer approach as claimed in claim 1, wherein determines this transmission order in a random basis for these golden key sections determine that the step of this transmission order comprises.

5. golden key transfer approach as claimed in claim 1, wherein according to these section length of these golden key sections, the step of this transmission length of setting each these golden key section corresponding comprises:

This transmission length of each these golden key section corresponding is set in a random basis according to a length of this golden key and these section length of these golden key sections.

6. golden key transfer approach as claimed in claim 1, also comprises:

At least one virtual golden key is added after this golden key,

Wherein according to these section length of these golden key sections, the step of this transmission length of setting each these golden key section corresponding comprises:

This transmission length of each these golden key section corresponding is set in a random basis according to a length of this golden key, a length and these section length of these golden key sections of this at least one virtual golden key.

7. golden key transfer approach as claimed in claim 1, also comprises:

Reconfigure in this encryption/decryption element belong to these golden key sections these reference positions, these section length and these transmit bit string to obtain this golden key.

8. golden key transfer approach as claimed in claim 7, wherein this encryption/decryption element has a home location register, a section length register, transmission bit string register and a gold medal key register,

Wherein according to this transmission order, comprise belonging to the step that this reference position of each these golden key section, this section length and this transmission bit string be sent to this encryption/decryption element from this memory buffer via this data bus:

These reference positions belonging to these golden key sections are sent to this home location register via this data bus;

These section length belonging to these golden key sections are sent to this section length register via this data bus; And

These transmission bit strings belonging to these golden key sections are sent to this transmission bit string register via this data bus.

9. golden key transfer approach as claimed in claim 8, wherein reconfigure in this encryption/decryption element belong to these golden key sections these reference positions, these section length and these transmit bit string and comprise with the step obtaining this golden key:

From this home location register this encryption/decryption element, this section length register and this transmission bit string register read respectively belong to these golden key sections these reference positions, these transmit length and these transmit bit string, according to read these reference positions belonging to these golden key sections, these transmission length and these transmit bit string and obtain this golden key, and this obtained golden key to be write in this golden key register.

10. a Memory Controller, for controlling a reproducible nonvolatile memorizer module, this Memory Controller comprises:

One host interface, is electrically connected to a host computer system;

One memory interface, is electrically connected to this reproducible nonvolatile memorizer module;

One memory buffer, in order to a temporary gold medal key;

One encryption/decryption element, carrys out encrypt and decrypt data in order to utilize this golden key; And

One memory management circuitry, is electrically connected to this host interface and this memory interface, in order to this golden key is sent to this encryption/decryption element from this memory buffer via a data bus,

Wherein multiple positions of this golden key are logically divided into multiple golden key section by this memory management circuitry, and wherein each these golden key section has a reference position and a section length,

Wherein this memory management circuitry is according to these section length of these golden key sections, a transmission length of setting each these golden key section corresponding,

Wherein this memory management circuitry is according to this reference position and this transmission length that belong to each these golden key section, from this golden key these assign belong to each golden key section one transmission bit string,

Wherein this memory management circuitry is that these golden key sections determine a transmission order, and according to this transmission order, be sent to this encryption/decryption element from this memory buffer via this data bus by belonging to this reference position of each these golden key section, this section length and this transmission bit string.

11. Memory Controllers as claimed in claim 10, wherein these positions of this golden key are divided into these golden key sections by this memory management circuitry, and wherein these section length of these golden key sections are identical and these transmission length of these golden key sections are same as these section length of these golden key sections.

12. Memory Controllers as claimed in claim 10, wherein multiple positions of this golden key are divided into these golden key sections by this memory management circuitry randomly, and the section length of at least two golden key sections wherein among these golden key sections is different.

13. Memory Controllers as claimed in claim 10, wherein this memory management circuitry determines this transmission order in a random basis.

14. Memory Controllers as claimed in claim 10, wherein this memory management circuitry sets this transmission length of each these golden key section corresponding in a random basis according to these section length of the golden key section of a length of this golden key and these.

15. Memory Controllers as claimed in claim 10, wherein this memory management circuitry adds at least one virtual golden key and sets this transmission length of each these golden key section corresponding according to a length of this golden key, a length and these section length of these golden key sections of this at least one virtual golden key in a random basis after this golden key.

16. Memory Controllers as claimed in claim 10, wherein this encryption/decryption element reconfigure belong to these golden key sections these reference positions, these section length and these transmit bit string to obtain this golden key.

17. Memory Controllers as claimed in claim 16, wherein this encryption/decryption element has a home location register, a section length register, transmission bit string register and a gold medal key register,

Wherein these reference positions belonging to these golden key sections are sent to this home location register via this data bus by this memory management circuitry, these section length belonging to these golden key sections are sent to this section length register via this data bus and these transmission bit strings belonging to these golden key sections are sent to this transmission bit string register via this data bus.

18. Memory Controllers as claimed in claim 17, wherein this encryption/decryption element also comprises an encryption and decryption controller, wherein this encryption and decryption controller from this home location register, this section length register and this transmission bit string register read respectively belong to these golden key sections these reference positions, these section length and these transmit bit string, according to read these reference positions belonging to these golden key sections, these section length and these transmit bit string and obtain this golden key, and this obtained golden key to be write in this golden key register.

19. 1 kinds of memorizer memory devices, comprising:

A connector, is electrically connected to a host computer system;

One reproducible nonvolatile memorizer module, in order to storage data; And

One Memory Controller, be electrically connected to this connector and this reproducible nonvolatile memorizer module, wherein this Memory Controller comprises:

One host interface, is electrically connected to this connector;

One memory buffer, in order to a temporary gold medal key;

Wherein this memory management circuitry reads length according to this reference position belonging to these golden key sections each with these this transmission, from this golden key these assign to read from this memory buffer belong to each respectively these golden key sections one transmit bit string,

20. memorizer memory devices as claimed in claim 19, wherein multiple positions of this golden key are divided into these golden key sections by this memory management circuitry randomly, and the section length of at least two golden key sections wherein among these golden key sections is different.

21. memorizer memory devices as claimed in claim 19, wherein this memory management circuitry determines this transmission order in a random basis.

22. memorizer memory devices as claimed in claim 19, wherein this memory management circuitry sets this transmission length of each these golden key section corresponding in a random basis according to these section length of the golden key section of a length of this golden key and these.

23. memorizer memory devices as claimed in claim 19, wherein this memory management circuitry adds at least one virtual golden key and sets this transmission length of each these golden key section corresponding according to a length of this golden key, a length and these section length of these golden key sections of this at least one virtual golden key in a random basis after this golden key.

24. memorizer memory devices as claimed in claim 19,

Wherein this encryption/decryption element has a home location register, a section length register, transmission bit string register and a gold medal key register,

25. memorizer memory devices as claimed in claim 24, wherein this encryption/decryption element also comprises an encryption and decryption controller, wherein this encryption and decryption controller from this home location register, this section length register and this transmission bit string register read respectively belong to these golden key sections these reference positions, these section length and these transmit bit string, according to read these reference positions belonging to these golden key sections, these section length and these transmit bit string and obtain this golden key, and this obtained golden key to be write in this golden key register.