CN102928772A - Time sequence testing system and testing method thereof - Google Patents
Time sequence testing system and testing method thereof Download PDFInfo
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- CN102928772A CN102928772A CN2012104733943A CN201210473394A CN102928772A CN 102928772 A CN102928772 A CN 102928772A CN 2012104733943 A CN2012104733943 A CN 2012104733943A CN 201210473394 A CN201210473394 A CN 201210473394A CN 102928772 A CN102928772 A CN 102928772A
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Abstract
The invention discloses a time sequence testing system. The system comprises a testing machine, and the testing machine comprises a test vector storage unit, an information recording unit, a sampling unit and a processor unit; a tested chip is selected; the test vector storage unit is controlled by the processor unit to input an excitation signal into the tested chip; after the excitation signal is received, the tested chip outputs a response signal which is corresponding to the excitation signal and has certain time delay; multiple sampling is carried out on the response signal by the sampling unit according to a fixed sampling frequency; sampling data is stored into a designated address by the information recording unit in real time; and then the processor unit reads the sampling data in the designated address from the information recording unit, calculates delay time T and outputs a result. With the adoption of a time sequence testing method of the time sequence testing system, time sequence testing efficiency can be effectively improved and time can be saved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of timing sequence test system and method for testing thereof.
Background technology
At present, the correctness of wanting to guarantee VLSI (very large scale integrated circuit) designs need to satisfy two aspects requirements: the first, and the correctness of chip circuit basic function; The second, the correctness of all device sequential in the chip circuit.Because the transmission of signal and the designing requirement of chip in the chip, have certain time delay between the pumping signal of the response signal of chip and correspondence, described time delay of the long or too short normal operation that all can affect chip, so need to detect accurately time delay, thereby judge that can chip work.
The method of utilizing tester table to carry out timing sequence test in the prior art mainly is: by after pumping signal of chip under test input, in the moment of rising edge or negative edge the response signal of chip is sampled and to judge the height of its level.And then the time of input signal and adjustment sampling, obtain new sampled data, so through repeatedly repeating input and sampling, until obtain the sampled data different from the last time, it is the level generation saltus step of response signal, the moment of sampling this moment is exactly rising or the negative edge moment of response signal, and the time between the sampling instant after the rising edge of pumping signal or negative edge trigger constantly and wait at this moment is exports relatively and the time delay between the pumping signal.
Since need to carry out repeatedly signal input, response signal is sampled and deterministic process, and constantly adjust the moment of sampling, whole test process need to expend a large amount of time and just can detect the saltus step of response signal levels.Even and if detect the saltus step of output level, still be difficult to obtain the position of rising edge accurately or negative edge, the resolution of test is also very low.
More time sequence test method please refer to the open text of US Patent No. 20110130990A1.
Summary of the invention
The problem that the present invention solves provides a kind of timing sequence test system and a kind of time sequence test method, improves the testing efficiency of realizing timing sequence test at tester table, improves the precision of timing sequence test.
For addressing the above problem, the present invention proposes a kind of time sequence test method, described time sequence test method comprises: tester table is provided, and described tester table comprises test vector storage unit, information recording unit, sampling unit and processor unit; Selected chip under test; Input a pumping signal by processor unit control test vector storage unit to chip under test; Chip under test is exported the therewith response signal with certain hour delay corresponding to pumping signal after receiving pumping signal, and the time of described delay is T; Triggering sampling unit when pumping signal changes repeatedly samples with a fixing sample frequency f to described response signal, until sampled data stops sampling when changing, and export sampled data to information recording unit in sampling, the number of described sampled data is n; Information recording unit advances assigned address with the sampled data real-time storage; Processor unit reads sampled data in the assigned address of information recording unit, calculate T time delay, and Output rusults, described T=time delay (1/f) * n.
Preferably, described chip under test has digital signal processing capability.
Preferably, described chip under test is memory chip or processor chips.
Preferably, described pumping signal is digital signal, has one or more rising edges.
Preferably, when described pumping signal had rising edge, the response signal corresponding with described pumping signal had negative edge or rising edge; When described pumping signal had negative edge, the response signal corresponding with described pumping signal had rising edge or negative edge;
Preferably, described information recording unit has storage chip, is suitable for the real-time storage sampled data.
Preferably, described information recording unit is the high-speed RAM storer.
Preferably, described sample frequency f is 10MHz ~ 100MHz.
Triggering sampling unit when preferably, described pumping signal produces rising edge or negative edge samples to response signal.
Preferably, after the described sampling unit data that sampling obtains to response signal changed, described sampling unit stopped the sampling to response signal.
Preferably, when stopping to sample, described sampling unit triggers processor, reading out data in the assigned address of information recording unit.
A kind of timing sequence test system that also proposes of the present invention comprises: test vector storage unit, described test vector storage unit are used for the storage test vector, send pumping signal by processor unit control to chip under test; Chip under test, described chip under test receives pumping signal, and output the response signal with certain hour delay corresponding with described pumping signal; Sampling unit, the sampling of the sample frequency that the response signal that described sampling unit is used for that chip under test is sent is fixed, and to information recording unit output sampled data; Information recording unit, described information recording unit is used for storing sampled data in assigned address; Processor unit is triggered by sampling unit, reads sampled data in the assigned address of information recording unit, calculates the time delay between response signal and the pumping signal.
Preferably, described chip under test has digital signal processing capability.
Preferably, described chip under test is memory chip, processor chips.
Preferably, described pumping signal is digital signal, has one or more rising edges.
Preferably, when described pumping signal had rising edge, the response signal corresponding with described pumping signal had negative edge or rising edge; When described pumping signal had negative edge, the response signal corresponding with described pumping signal had rising edge or negative edge.
Preferably, described information recording unit has storage chip, is suitable for the real-time storage sampled data.
Preferably, described information recording unit is the high-speed RAM storer.
Preferably, the sample frequency f of described sampling unit is 10MHz ~ 100MHz.
Preferably, described sampling unit is triggered when pumping signal produces rising edge or negative edge, and response signal is sampled.
Preferably, after the described sampling unit data that sampling obtains to response signal change, stop the sampling to response signal.
Preferably, described processor is triggered when sampling unit stops to sample, reading out data in the assigned address of information recording unit.
Compared with prior art, the present invention has the following advantages:
The timing sequence test system that technical scheme of the present invention adopts has information recording unit, and this information recording unit has the sampled data that storage chip can the real-time storage tester table.Chip under test receives pumping signal and is determined by test vector, chip under test is exported corresponding with it response signal after receiving pumping signal, trigger the sampling of the sample frequency that sampling unit is fixed response signal when pumping signal changes, the data that simultaneously sampling obtained deposit in the assigned address of information recording unit in real time.Because described information recording unit can the real-time storage sampled data, just can obtain this response signal with respect to the delay of pumping signal so observe the sampled data of described storage, the moment that sampled data changes is exactly the moment of the level generation saltus step of response signal.And the sampled data before this moment is logical one or logical zero, the number of described logical one or logical zero multiply by time interval between each sampling and can obtain from the time span of the level generation jumping moment that begins to sample response signal, namely this response signal is with respect to the time delay of pumping signal, and computing method are simple.Only need the input of a pumping signal just can detect the edge of the response signal generation level saltus step that obtains chip under test, obtain time delay, can effectively save the time of test, with higher sample frequency response signal is sampled, can obtain more accurately the position at response signal levels saltus step edge, can the Effective Raise measuring accuracy.
Description of drawings
Fig. 1 is the block diagram of the timing sequence test system of embodiments of the invention;
Fig. 2 is the schematic flow sheet of the time sequence test method of embodiments of the invention;
Fig. 3 is the sequential chart of embodiments of the invention.
Embodiment
As described in the background art, prior art is utilizing tester table chip under test to be carried out in the process of timing sequence test, need to carry out multiple signal input and sampling analysis, just can detect rising or the trailing edge edge of signal, and the time cost is longer.
Embodiments of the invention have proposed a kind of timing sequence test system and method for testing thereof, utilize tester table to carry out timing sequence test, test duration that can Effective Raise and the precision of test.
Below in conjunction with accompanying drawing, by specific embodiment, technical scheme of the present invention is carried out clear, complete description, obviously, described embodiment only is the part of embodiment of the present invention, rather than they are whole.According to these embodiment, those of ordinary skill in the art belongs to protection scope of the present invention need not obtainable all other embodiments under the prerequisite of creative work.
Please refer to Fig. 1, be the schematic diagram of the timing sequence test system of the present embodiment.
Described timing sequence test system made is on tester table 100, and described tester table 100 comprises test vector storage unit 101, sampling unit 102, information recording unit 103, processor unit 104 and chip under test 300.
Described test vector storage unit 101 is used for the storage test vector, and described test vector is the set of the chip input and output value that should have according to designing requirement.Common 1/0 is used for representing input state, and the independent vector of every row represents " original " data of a single test period.By processor unit 104 controls, utilize test vector storage unit 101 with data and sequential, waveform format and voltage data combine, and form pumping signal and export to chip under test.
Chip under test 300 has digital signal processing function, can be the chip of memory chip, processor chips or type.
In the described test macro, connect by test bus between the unit, realize transmission and the reception of data between the unit.
Please refer to Fig. 2, be the method flow schematic diagram of the timing sequence test of the present embodiment.
The time sequence test method of the present embodiment may further comprise the steps:
S100: tester table is provided, and described tester table comprises test vector storage unit, information recording unit, sampling unit and processor unit;
S101: selected chip under test;
S102: input a pumping signal to chip under test by processor unit control test vector storage unit;
S103: chip under test is exported the therewith response signal with time delay corresponding to pumping signal after receiving pumping signal, and the time of described delay is T;
S104: trigger sampling unit when pumping signal changes described response signal is repeatedly sampled with a fixing sample frequency f, until sampled data stops sampling when changing, and export sampled data to information recording unit in sampling, the number of described sampled data is n;
S105: information recording unit advances assigned address with the sampled data real-time storage;
S106: processor unit reads sampled data in the assigned address of information recording unit, calculates T time delay, and Output rusults, described T=time delay (1/f) * n.
Concrete, please refer to Fig. 1, tester table at first is provided.
The tester table 100 that the present embodiment adopts, described tester table 100 comprises test vector storage unit 101, sampling unit 102, information recording unit 103, processor unit 104 and chip under test 300.
Described test vector storage unit 101 is used for the storage test vector, and described test vector is the set of the chip input and output value that should have according to designing requirement.Generally represent low level with logical zero, logical one represents high level.Test vector is stored in the test vector storage unit by the sequence of positions that occurs in test procedure.In the present embodiment, employing be the memory test board, have information recording unit.In other embodiments of the invention, if tester table does not have information recording unit, the technician can an external storage chip as information recording unit, thereby realize technical scheme of the present invention.
Then, selected chip under test 300.
Chip under test 300 has digital signal processing function, can be the chip of memory chip, processor chips or type.Described chip under test 300 has input end and output terminal.The output terminal of the test vector storage unit 101 in the described tester table links to each other with the input end of chip under test 300 by test interface 200, and the output terminal of chip under test 300 links to each other with the input end of sampling unit 102 by test interface 200.Described test interface 200 is connected to the translation interface on the port of tester table for the pin with chip under test, according to characteristic profile and the electric characteristics of chip to be measured many types are arranged.
In the process of carrying out timing sequence test, at first, to pumping signal 210 of chip under test 300 inputs, described pumping signal as shown in Figure 3 by processor unit 104 control test vector storage unit 101.
In the present embodiment, described pumping signal 210 is digital signal, has a rising edge.In other embodiments of the invention, described pumping signal also can be the digital signal with one or more rising edges and negative edge.Described pumping signal is to be produced by test vector storage unit 101.Concrete, sending of the test vector data of processor 103 control test vector storage unit, the test vector data communication device is crossed tester table and is converted into described pumping signal 210 with rising edge waveform, by the input end input of test interface 200 from chip under test.
Chip under test receive export after the pumping signal 210 one therewith the response signal 220(with time delay corresponding to pumping signal please refer to Fig. 3), the time of described delay is T.The waveform of described response signal 220 is decided according to the designing requirement of chip.Pumping signal 210 is rising edge in the present embodiment, and corresponding response signal is negative edge with it.In other embodiments of the invention, test different chips, may produce different response signals, the high-low level of described response signal changes and can change consistent or opposite with the high-low level of pumping signal.Because the transmission of signal and the designing requirement of chip in the chip, have certain T time delay between the response signal of chip and the input signal, long or the too short normal operation that all can affect chip of described T time delay, so need to detect accurately described time delay of T, thereby judge that can described chip work.
Described response signal 220 inputs to the sampling unit 102 of tester table 100 by the output terminal of chip under test by test interface.102 pairs of response signals 220 of described sampling unit are sampled.Described sampling process is exactly to read the level value of response signal with certain frequency.In the present embodiment, if sampled data is high level, then output logic 0; If low level then is output as logical one.In other embodiments of the invention, also can be by the different sample circuit of design, so that sampled value is then output logic 1 of high level, low level is output logic 0 then.
Triggering 102 pairs of described response signals 220 of sampling unit when pumping signal 210 changes repeatedly samples with a fixing sample frequency f, until sampled data stops sampling when changing, and export sampled data to information recording unit in sampling, the number of described sampled data is n.
In the present embodiment, the moment of described pumping signal high-low level generation saltus step is the negative edge moment of pumping signal.The sample frequency scope of described sampling unit is 10MHz ~ 100MHz, depends on the highest frequency of the tester table that adopts.In the embodiments of the invention, the sample frequency of employing is 100MHz, and among other embodiment of the present invention, sample frequency can also be 30MHz, 50MHz or 80MHz.Described sample frequency is determined by the performance of the tester table that adopts.Sample frequency is higher, and the interval between the double sampling is shorter, and the accurate testing degree is higher.In the present embodiment, when response signal generation high level during to low level saltus step, the saltus step from the logical zero to the logical one occurs in sampling output, is the negative edge of response signal constantly this moment.Because the delay of signal transmission, in sampled data changes the process that sampling unit stops to sample, still can carry out the sampling of several times, so, after changing, sampled data still can obtain some sampled datas.
The sampled data that obtains in the process of sampling in real time with (0000 ... 00001111 ... 1111) form deposits in the assigned address in the storage chip of information recording unit 103.
When described sampling unit stops to sample, trigger processor unit 104 and read the sampled data (0000 of described storage from the assigned address of information recording unit 103 ... 00001111 ... 1111), calculate this response signal with respect to the time delay of pumping signal by the sampled data that reads.Concrete, be T described time delay, and sample frequency is f, and the number of sampling continuous wave output logical zero is n, and then be T=(1/f) * n described time delay.In the present embodiment, sample frequency is 100MHz, and the number of described logical zero is 2000, so T=10ns in the present embodiment * 2000=20 μ s.In other embodiments of the invention, if in the sampling process, the high level output logical one of response signal, the low level output logical zero, sample frequency is 50MHz, the number of described logical one is 2000, then time delay T=20ns * 2000=40 μ s.
In the present embodiment, the sampling unit of tester table is sampled to response signal with a fixing frequency, this sampling process by the rising of pumping signal or trailing edge along trigger, in the time of sampling, described sampled data deposits in the assigned address of information recording unit in real time.Because described information recording unit can the real time record sampled data, so the sampled data of observing described storage just can obtain the wave form varies of this response signal, the moment that sampled data changes is exactly the level generation saltus step appearance rising of response signal or the moment of negative edge.Sampled data before this moment is logical one or logical zero, the number of described logical one or logical zero multiply by time interval between each sampling and can obtain from the time span of the level generation jumping moment that begins to sample response signal, and namely the edge of this response signal is with respect to the time delay at the edge of pumping signal.Technical scheme of the present invention only needs the input of a pumping signal just can detect the edge of the response signal generation level saltus step that obtains chip under test, and detection method is direct and convenient.
The timing sequence test system that adopts in the present embodiment can solve in the method that existing employing tester table tests needs repeatedly input signal, and circulation is repeatedly sampled, and need to expend a large amount of time, the problem that testing efficiency is low.The present invention only needs the input of a pumping signal, can effectively save the time of test, with higher sample frequency response signal is sampled, and can obtain more accurately the position at response signal levels saltus step edge, can the Effective Raise measuring accuracy.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Any those of ordinary skill in the art, do not breaking away from the technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.
Claims (22)
1. a time sequence test method is characterized in that, comprising:
Tester table is provided, and described tester table comprises test vector storage unit, information recording unit, sampling unit and processor unit;
Selected chip under test;
Input a pumping signal by processor unit control test vector storage unit to chip under test;
Chip under test is exported the therewith response signal with time delay corresponding to pumping signal after receiving pumping signal, and the time of described delay is T;
Triggering sampling unit when pumping signal changes repeatedly samples with a fixing sample frequency f to described response signal, until sampled data stops sampling when changing, and export sampled data to information recording unit in sampling, the number of described sampled data is n;
Information recording unit advances assigned address with the sampled data real-time storage;
Processor unit reads sampled data in the assigned address of information recording unit, calculate T time delay, and Output rusults, described T=time delay (1/f) * n.
2. time sequence test method according to claim 1 is characterized in that, described chip under test has digital signal processing capability.
3. time sequence test method according to claim 1 is characterized in that, described chip under test is memory chip or processor chips.
4. time sequence test method according to claim 1 is characterized in that, described pumping signal is digital signal, has one or more rising edges.
5. the method for timing sequence test according to claim 4 is characterized in that, when described pumping signal had rising edge, the response signal corresponding with described pumping signal had negative edge or rising edge; When described pumping signal had negative edge, the response signal corresponding with described pumping signal had rising edge or negative edge.
6. time sequence test method according to claim 1 is characterized in that, described information recording unit has storage chip, is suitable for the real-time storage sampled data.
7. time sequence test method according to claim 6 is characterized in that, described information recording unit is the high-speed RAM storer.
8. time sequence test method according to claim 1 is characterized in that, described sample frequency f is 10MHz ~ 100MHz.
9. time sequence test method according to claim 1 is characterized in that, triggers sampling unit when described pumping signal produces rising edge or negative edge response signal is sampled.
10. time sequence test method according to claim 1 is characterized in that, after the described sampling unit data that sampling obtains to response signal changed, described sampling unit stopped the sampling to response signal.
11. time sequence test method according to claim 10 is characterized in that, triggers processor when described sampling unit stops to sample, reading out data in the assigned address of information recording unit.
12. a timing sequence test system is characterized in that, comprising:
Test vector storage unit, described test vector storage unit are used for the storage test vector, send pumping signal by processor unit control to chip under test;
Chip under test, described chip under test receives pumping signal, and output the response signal with certain hour delay corresponding with described pumping signal;
Sampling unit, described sampling unit is used for the response signal that chip under test sends is fixed the sampling of frequency, and to information recording unit output sampled data;
Information recording unit, described information recording unit is used for storing sampled data in assigned address;
Processor unit is triggered by sampling unit, reads sampled data in the assigned address of information recording unit, calculates the time delay between response signal and the pumping signal.
13. timing sequence test according to claim 12 system is characterized in that described chip under test has digital signal processing capability.
14. timing sequence test according to claim 13 system is characterized in that described chip under test is memory chip, processor chips.
15. timing sequence test according to claim 12 system is characterized in that described pumping signal is digital signal, has one or more rising edges.
16. timing sequence test according to claim 15 system is characterized in that when described pumping signal had rising edge, the response signal corresponding with described pumping signal had negative edge or rising edge; When described pumping signal had negative edge, the response signal corresponding with described pumping signal had rising edge or negative edge.
17. timing sequence test according to claim 12 system is characterized in that described information recording unit has storage chip, is suitable for the real-time storage sampled data.
18. timing sequence test according to claim 17 system is characterized in that described information recording unit is the high-speed RAM storer.
19. timing sequence test according to claim 12 system is characterized in that the sample frequency f of described sampling unit is 10MHz ~ 100MHz.
20. timing sequence test according to claim 12 system is characterized in that, described sampling unit is triggered when pumping signal produces rising edge or negative edge, and response signal is sampled.
21. timing sequence test according to claim 12 system is characterized in that, after the described sampling unit data that sampling obtains to response signal change, stops the sampling to response signal.
22. timing sequence test according to claim 12 system is characterized in that described processor is triggered when sampling unit stops to sample, reading out data in the assigned address of information recording unit.
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