CN102904715B - Based on the parallel Pseudo-random bit generator of coupled chaotic mapping system - Google Patents

Based on the parallel Pseudo-random bit generator of coupled chaotic mapping system Download PDF

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CN102904715B
CN102904715B CN201210364841.1A CN201210364841A CN102904715B CN 102904715 B CN102904715 B CN 102904715B CN 201210364841 A CN201210364841 A CN 201210364841A CN 102904715 B CN102904715 B CN 102904715B
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mapping system
coupled
chaotic mapping
initial value
coupled chaotic
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CN102904715A (en
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王世红
梁仁夫
周琥
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Beijing University of Posts and Telecommunications
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Abstract

The object of the invention is that design can be used for hardware implementing, is applicable to parallel work-flow, high efficiency Pseudo-random bit generator.Based on the Pseudo-random bit generator of coupled chaotic mapping system, by initialization module, the initial value of random bit generator (also referred to as seed) is expanded by nonlinear transformation and produces the initial value of coupled chaotic mapping system; The initial value input coupled chaotic mapping system of the coupled chaotic mapping system that expansion produces, through the effect of coupled chaotic mapping system, parallel output multichannel chaos sequence; The process of the chaos sequence exported by output module, parallel output meets the PRBS pseudo-random bit sequence that NIST SP800-22 revises testing standard.

Description

Based on the parallel Pseudo-random bit generator of coupled chaotic mapping system
Technical field
The present invention relates to field of information security technology, is the parallel Pseudo-random bit generator based on coupled chaotic mapping system.
Technical background
Pseudo random number has a wide range of applications in Monte Carlo Calculation, text encryption, image encryption and video-encryption and the key in cipher protocol, initializing variable, and therefore the research of randomizer has consequence in Statistical Physics and modern password.The sequence requirements that pseudorandom number generator produces has cycle large as far as possible and good randomness.
Because chaotic orbit is to the sensitiveness of initial value and parameter, and the pseudo-randomness of chaotic signal, in recent years, much researcher's application of chaos dynamics builds pseudorandom number generator.From existing achievement in research, a more competitive class is the chaos pseudo random number generator based on time and space usage chaotic maps grid.Compared with low-dimensional system, Spatiotemporal Chaotic Systems has multiple positive Liapunov exponent, adds complexity and the cycle of system.Chaotic computing is based on real number field, and therefore the design of the existing randomizer based on chaos is applicable to software operating environment mostly, and for moving to, hardware platform to also exist operation cost high, the shortcoming that operational efficiency is low.
The present invention is special completely newly, based on the parallel Pseudo-random bit generator of chaos coupled maps, its main feature adopts one dimension coupled chaotic mapping system, by selecting effective parameter, ensure that the space-time chaos complexity of system, also not only make the sequence of output have good statistical property by limited, shifting function easily, and be applicable to hardware platform; Can be used for parallel output random bit sequence simultaneously.
Summary of the invention
The object of the invention is that design can be used for hardware implementing, is applicable to parallel work-flow, high efficiency Pseudo-random bit generator.Based on the parallel Pseudo-random bit generator of coupled chaotic mapping system, its process feature is following treatment step:
A1) by initialization module, the initial value of Pseudo-random bit generator (also referred to as seed) is produced the initial value of coupled chaotic mapping system by nonlinear transformation expansion;
A2) the initial value input coupled chaotic mapping system of the coupled chaotic mapping system of expansion generation, through the effect of coupled chaotic mapping system, parallel output multichannel chaos sequence, chaos sequence rounds output bit sequence.
In A1, the initial value of 64 bits is extended to 32N bit by nonlinear transformation, produces N number of initial value x of coupled chaotic mapping system 0(i), i=1,2 ..., N, N are the number of coupled maps, N>=4, each x 0i () is all belong to [0,2 32) integer on interval; If have all equal initial value, i.e. x 0(i)=x 0(1), i=2,3 ..., N, the initial value of output is changed to x 0(i)=x 0(1)+10000 × i, i=2,3 ..., N, wherein symbol+be mould 2 32addition.
above-mentioned non-line piece conversion can in the following way: first by the Initial Value definition of 64 bits be w (1) || w (2) || ... || w (7) || w (8), each w (i) is [0,2 8 ) integer, i=1,2 ..., 8; Definition w (i+8)=S (w (i)+w (i+4)+i), i=1,2 ..., 4N-8, wherein symbol+be mould 2 8 addition, S is 8 bits to the non-linear S box conversion of 8 bits, the S box of AES can be selected to convert; Combine 48 ratios in order special w forms the integer of 32 bits, as x 0 (1)=w (1) || w (2) || w (3) || w (4), x 0 (2)=w (5) || w (6) || w (7) || w (8), ..., x 0 (N)=w (4N-3) || w (4N-2) || w (4N-1) || w (4N).
In A2, the initial value of the coupled chaotic mapping system expanding generation in A1 is inputted coupled chaotic mapping system, and described coupled chaotic mapping system meets
x n+1(i)=(1-ε 12)f(x n(i))+ε 1f(x n(i+1))+ε 2f(x n(i-1)),i=1,2,...,N,
Wherein n=0,1,2 ... be discrete time step number; I is coupled maps position coordinates, and N is the length of coupled map lattices; Adopt periodic boundary condition x n(0)=x n(N), x n(N+1)=x n(1); F (x)=ax mod 2 32displacement maps, a ∈ (1,2]; ε 1and ε 2for stiffness of coupling, meet ε 1> 0, ε 2> 0, and ε 1≠ ε 2, 1-ε 12> 0;
And described coupled chaotic mapping system requires parameter a, ε 1and ε 2selection make coupled system be Spatiotemporal Chaotic Systems, simultaneously in order to make complicated multiplying be converted into simple shifting function, getting parameter is following form
a = 1 + Σ i = 1 a i 2 - i , a i ∈ { 0,1 } ,
ϵ 1 = Σ i = 1 b i 2 - i , a i ∈ { 0,1 } ,
ϵ 2 = Σ i = 1 c i 2 - i , c i ∈ { 0,1 } ,
And described coupled chaotic mapping system requires that discrete time n just starts parallel output chaos time sequence when being greater than 100, chaos sequence rounds output bit sequence.
The present invention has following technique effect:
1. the randomizer based on Time Chaotic Dynamical Systems is generally only applicable to software operating environment, and the present invention is by Selection parameter a, ε 1and ε 2, make the random bit generator based on Time Chaotic Dynamical Systems can conveniently for hardware implementing with less cost.
2. this Pseudo-random bit generator can parallel output bit sequence.
Accompanying drawing explanation
Fig. 1 is structural representation of the present invention.
Fig. 2 is embodiment of the present invention f (x)=2x mod 2 32displacement maps operation chart.
Fig. 3 is the embodiment of the present invention displacement maps operation chart.
Fig. 4 is the schematic diagram of the coupling chaotic mapping of the embodiment of the present invention.
Fig. 5 is the output module schematic diagram of the embodiment of the present invention.
Embodiment
Further describe technical scheme of the present invention below in conjunction with accompanying drawing and example: A1) by initialization module, the initial value of Pseudo-random bit generator (also referred to as seed) expansion is produced the initial value of coupled chaotic mapping system; A2) the initial value input coupled chaotic mapping system of the coupled chaotic mapping system of expansion generation, through the effect of coupled chaotic mapping system, parallel output multichannel chaos sequence, chaos sequence rounds defeated go out bit sequence.
In A1, initialization module is that the initial value of 64 bits is extended to 32N bit by nonlinear transformation, produces N number of initial value x of coupled chaotic mapping system 0i (), N is the number of coupled maps, N>=4, each x 0i () is all belong to [0,2 32) integer on interval.If all initial value is all equal, i.e. x 0(i)=x 0(1), i=2,3 ..., N, then the initial value exported is x 0(i)=x 0(1)+10000 × i, i=2,3 ..., N.
Above-mentioned nonlinear transformation alsohashing function approach can be adopted, such as SHA-1.The initial value of 64 bits is carried out SHA-1 hash transformation as information, obtains the hashed value of 160 bits, the expansion of 160 bits corresponds to the coupled maps system of N=5, often gets the initializaing variable x that map of 32 bit values as coupled chaotic mapping system 0(i), i=1,2,3,4,5.If the coupled maps system of N > 5, then 160 bit values continued using exporting carry out SHA-1 hash transformation as new information, and the hashed value of often getting 32 bits outputs continues to be left as coupled chaotic mapping system the initializaing variable x of mapping 0(i), i=6,7,8,9,10.By that analogy, if the coupled maps system of N > 10, then 160 bit values continued using exporting carry out SHA-1 hash transformation as new information, often get the initializaing variable x of hashed value as coupled chaotic mapping system of 32 bits outputs 0i (), i=11,12..., until all initializaing variable x obtaining the coupled chaotic mapping system needed 0(i), i=1,2 ..., N.
Above-mentioned nonlinear transformation also can in the following way: be first w (1) by the Initial Value definition of 64 bits || w (2) || ... || w (7) || w (8), each w (i) is [0,2 8) integer, i=1,2 ..., 8; Definition w (i+8)=S (w (i)+w (i+4)+i), i=1,2 ..., 4N-8, wherein symbol+be mould 2 8addition, S is the non-linear S box conversion of 8 bits to 8 bits, and the S box of AES can be selected to convert; The w combining 48 bits in order forms the integer of 32 bits, as x 0(1)=w (1) || w (2) || w (3) || w (4), x 0(2)=w (5) || w (6) || w (7) || w (8) ..., x 0(N)=w (4N-3) || w (4N-2) || w (4N-1) || w (4N).
In A2, the initial value input coupled chaotic mapping system of the coupled chaotic mapping system that expansion produces, through the effect of coupled chaotic mapping system, parallel output multichannel chaos sequence.Described coupled chaotic mapping system meets:
x n+1(i)=(1-ε 12)f(x n(i))+ε 1f(x n(i+1))+ε 2f(x n(i-1)),i=1,2,...,N
Wherein displacement maps f (x)=ax mod 2 32, a ∈ (1,2]; ε 1and ε 2for stiffness of coupling, meet ε 1> 0, ε 2> 0, and ε 1≠ ε 2, 1-ε 12> 0.Described coupled chaotic mapping system requires parameter a, ε 1and ε 2selection make coupled system be Spatiotemporal Chaotic Systems, and require that discrete time n just starts parallel output chaos time sequence when being greater than 100.
the chaos time sequence value that A2 exports is converted into 32 bits wherein export the partial bit position that sensitiveness is lower the bit sequence exported adopts NIST SP800-22 revised edition as testing standard, ensures that each sequence has good good statistical property, separate between different sequences.
Fig. 2 is displacement maps f (the x)=ax mod 2 of the embodiment of the present invention 32operation chart.If get a=2, then displacement maps f (x)=2x mod 2 32be converted into f (x)=(x < < < 1) mod 2 32, wherein x < < < 1 represents 1 bit manipulation that moves to left.
Fig. 3 is the embodiment of the present invention displacement maps operation chart. can be decomposed into 1 3 4 = 1 + 2 - 1 + 2 - 2 , Then displacement maps f ( x ) = 1 3 4 x mod 2 32 Be converted into f (x)=x+ (x > > > 1)+(x > > > 2) mod 2 32, wherein x > > > 1 and x > > > 2 represents move to right 1 and 2 bit manipulations that move to right respectively.
Fig. 4 is the schematic diagram of the coupling chaotic mapping of the embodiment of the present invention.If get then parameter can be decomposed into &epsiv; 2 = 3 32 = 2 - 4 + 2 - 5 , ε 2=2 -5 1 - &epsiv; 1 - &epsiv; 2 = 7 8 = 2 - 1 + 2 - 2 + 2 - 3 , Coupled maps system is expressed as further:
x n + 1 ( i ) = ( 1 - &epsiv; 1 - &epsiv; 2 ) f ( x n ( i ) ) + &epsiv; 1 f ( x n ( i + 1 ) ) + &epsiv; 2 f ( x n ( i - 1 ) ) = ( 1 - &epsiv; 1 - &epsiv; 2 ) X n ( i ) + &epsiv; 1 X n ( i + 1 ) + &epsiv; 2 X n ( i - 1 ) = ( X n ( i ) > > > 1 ) + ( X n ( i ) > > > 2 ) + ( X n ( i ) > > > 3 ) + ( X n ( i + 1 ) > > > 4 ) + ( X n ( i + 1 ) > > > 5 ) + ( X n ( i - 1 ) > > > 5 ) .
In Fig. 2, embodiment shown by 3 and 4, ensure that the multiplying of displacement maps and coupling chaotic mapping is converted into shifting function, be conducive to the design of hardware operation.Under the above parameters, system is Spatiotemporal Chaotic Systems simultaneously.Just can parallel output chaos time sequence when requiring to be greater than 100 running time, ensure that the initial value of input is fully mixed and spreads.
Fig. 5 is the output module schematic diagram of the embodiment of the present invention.In order to ensure that sequence has good statistical property, select 32 bit x n+1i the low partial bit of the sensitivity in (), as output, is namely selected x n + 1 ( i ) = b n + 1 1 ( i ) b n + 1 2 ( i ) . . . b n + 1 31 ( i ) b n + 1 32 ( i ) ( b n + 1 j ( i ) &Element; { 0,1 } ) in 16 low bits adopt the statistical method of NIST SP800-22 revised edition to detect, testing result shows N number of sequence of parallel output (i=1,2 ..., N) statistical property that all had, simultaneously the cross-correlation statistical property that had of adjacent sequence, i.e. sequence b n + 1 17 ( i ) &CirclePlus; b n + 1 17 ( i + 1 ) , b n + 1 18 ( i ) &CirclePlus; b n + 1 18 ( i + 1 ) , . . . , b n + 1 31 ( i ) &CirclePlus; b n + 1 31 ( i + 1 ) , b n + 1 32 ( i ) &CirclePlus; b n + 1 32 ( i + 1 ) , Also the detection of NIST SP800-22 revised edition is satisfied with, wherein i=1,2 ..., N-1.

Claims (3)

1., based on the parallel Pseudo-random bit generator of coupled chaotic mapping system, its process feature is following treatment step:
A1) by initialization module, the initial value of Pseudo-random bit generator (also referred to as seed) is expanded by nonlinear transformation and produces the initial value of coupled chaotic mapping system;
A2) the initial value input coupled chaotic mapping system of the coupled chaotic mapping system of expansion generation, through the effect of coupled chaotic mapping system, parallel output multichannel chaos sequence, chaos sequence rounds output bit sequence;
Wherein steps A 1) initial value of 64 bits is extended to 32N bit by nonlinear transformation, produce N number of initial value x of coupled chaotic mapping system 0(i), i=1,2 ..., N, N are the number of coupled maps, N>=4, each x 0i () is all belong to [0,2 32) integer on interval; If have all equal initial value, i.e. x 0(i)=x 0(1), i=2,3 ..., N, the initial value of output is changed to x 0(i)=x 0(1)+10000 × i, i=2,3 ..., N;
Steps A 1) described in nonlinear transformation can in the following way:
First be w (1) by the Initial Value definition of 64 bits || w (2) || ... || w (7) || w (8), each w (i) is [0,2 8) integer, i=1,2 ..., 8; Definition w (i+8)=S (w (i)+w (i+4)+i), i=1,2 ..., 4N-8, wherein symbol+be mould 2 8addition, S is the non-linear S box conversion of 8 bits to 8 bits, and the S box of AES can be selected to convert; Combine the integer that 4 w form 32 bits in order, as x 0(1)=w (1) || w (2) || w (3) || w (4), x 0(2)=w (5) || w (6) || w (7) || w (8) ..., x 0(N)=w (4N-3) || w (4N-2) || w (4N-1) || w (4N);
Steps A 2) the initial value input coupled chaotic mapping system of the coupled chaotic mapping system of expansion generation, described coupled chaotic mapping system meets
x n+1(i)=(1-ε 12)f(x n(i))+ε 1f(x n(i+1))+ε 2f(x n(i-1)),i=1,2,...,N,
Wherein n=0,1,2 ... be discrete time step number; I is coupled maps position coordinates, and N is the length of coupled map lattices; Adopt periodic boundary condition x n(0)=x n(N), x n(N+1)=x n(1); F (x)=ax mod 2 32displacement maps, a ∈ (1,2]; ε 1and ε 2for stiffness of coupling, meet ε 1> 0, ε 2> 0, and ε 1≠ ε 2, 1-ε 12> 0.
2. the parallel Pseudo-random bit generator based on coupled chaotic mapping system according to claim 1, steps A 2) middle coupled chaotic mapping system requirement parameter a, ε 1and ε 2selection make coupled system be Spatiotemporal Chaotic Systems, and meet following form: a = 1 + &Sigma; i = 1 a i 2 - i , a i &Element; { 0,1 } ; &epsiv; 1 = &Sigma; i = 1 b i 2 - 1 , b i &Element; { 0,1 } ; &epsiv; 2 = &Sigma; i = 1 c i 2 - 1 , c i = &Element; { 0,1 } .
3. the parallel Pseudo-random bit generator based on coupled chaotic mapping system according to claim 1, steps A 2) described in coupled chaotic mapping system require that discrete time n just starts parallel output chaos time sequence when being greater than 100.
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CN103580849A (en) * 2013-10-25 2014-02-12 西安理工大学 Spatiotemporal chaos secret communication method
CN106291616B (en) * 2016-07-29 2018-11-23 武汉大学 Space-time chaos vector pseudo-noise code generator offset carrier modulator approach and system
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060291649A1 (en) * 2005-06-22 2006-12-28 Crandall Richard E Chaos generator for accumulation of stream entropy
US20080183785A1 (en) * 2007-01-29 2008-07-31 Oded Katz Differential Approach to Current-Mode Chaos Based Random Number Generator
CN101252416A (en) * 2008-03-24 2008-08-27 清华大学 Space-time chaos double coupling drive system and code error detecting and handling method
CN101702117A (en) * 2009-11-09 2010-05-05 东南大学 Method for generating random pseudorandom sequence based on discrete progressive determinacy
CN101902332A (en) * 2010-07-16 2010-12-01 北京邮电大学 Hashing method with secrete key based on coupled chaotic mapping system

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060291649A1 (en) * 2005-06-22 2006-12-28 Crandall Richard E Chaos generator for accumulation of stream entropy
US20080183785A1 (en) * 2007-01-29 2008-07-31 Oded Katz Differential Approach to Current-Mode Chaos Based Random Number Generator
CN101252416A (en) * 2008-03-24 2008-08-27 清华大学 Space-time chaos double coupling drive system and code error detecting and handling method
CN101702117A (en) * 2009-11-09 2010-05-05 东南大学 Method for generating random pseudorandom sequence based on discrete progressive determinacy
CN101902332A (en) * 2010-07-16 2010-12-01 北京邮电大学 Hashing method with secrete key based on coupled chaotic mapping system

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
基于混沌映射的伪随机序列发生器;邱劲、王平、肖迪、廖晓峰;《计算机科学》;20111015;第38卷(第10期);第81-83页 *
混沌伪随机序列发生器设计及应用;张靓;《中国优秀硕士学位论文全文数据库 信息科技辑》;20091215(第12期);I136-119页 *

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