CN102903642B - Chip scale packaging method capable of encapsulating bottom and periphery of chip - Google Patents
Chip scale packaging method capable of encapsulating bottom and periphery of chip Download PDFInfo
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- CN102903642B CN102903642B CN201110221870.8A CN201110221870A CN102903642B CN 102903642 B CN102903642 B CN 102903642B CN 201110221870 A CN201110221870 A CN 201110221870A CN 102903642 B CN102903642 B CN 102903642B
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 88
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 84
- 239000010703 silicon Substances 0.000 claims abstract description 84
- 239000002390 adhesive tape Substances 0.000 claims abstract description 23
- 239000005022 packaging material Substances 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- 238000005520 cutting process Methods 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 238000002161 passivation Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000012856 packing Methods 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 150000003376 silicon Chemical class 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 238000005516 engineering process Methods 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 4
- 238000009826 distribution Methods 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000010992 reflux Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000005538 encapsulation Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000007306 turnover Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/11002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Abstract
The invention relates to a chip scale packaging method capable of encapsulating the bottom and periphery of a chip, which comprises the following steps: after thinning backs of silicon chips, binding the silicon chips onto a scribing film; scribing the upward fronts of the silicon chips, so that the chips are connected through the scribing film on the bottom surfaces; after reversely installing each silicon chip with the scribing film and binding all the silicon chips onto the top surface of a double-sided adhesive tape, removing the scribing film; binding and fixing the bottom surface of the double-sided adhesive tape onto a support lining board; filling a plastic packaging material in gaps among the chips from the backs of the silicon chips, so that the plastic packaging material is covered on the backs of all the chips to form a plastic packaging body; after peeling the silicon chips, mounting balls in the positions corresponding to every chip top electrode, and carrying out refluxing treatment; and finally, scribing to separate the integrated plastic packaging body formed by connecting the adjacent chips, so that certain protection of the plastic packaging body is left on the bottom and periphery of each independent chip.
Description
Technical field
The present invention relates to a kind of method for packing (WLP) of chip-scale, particularly a kind of chip-scale packaging method chip bottom and periphery encapsulated.
Background technology
As shown in Figure 1, be the structural representation of existing a kind of semiconductor chip 200, only the periphery of described chip 200 be provided with plastic-sealed body 300.Specifically respective production metal line 210, the passivation layer 220 of some chip 200 end faces on a silicon chip 100, and planted tin ball 230 respectively on its top electrodes after, carry out described chip 200 and encapsulate; Described method for packing, as shown in Figure 2: steps A 1, makes the bottom surface of described silicon chip 100 be attached on scribing film 400, and makes the metal line 210 at described some chips 200 top, passivation layer 220 and tin ball 230 upward; Steps A 2, to silicon chip 100 scribing, namely correspondence forms dicing lane 110 between each chip 200 of scribing film 400 connection; Steps A 3, injects the plastic packaging materials such as plastic packaging resin, to form described plastic-sealed body 300 in described some dicing lane 110; Steps A 4, in the position scribing of described dicing lane 110, separates the plastic-sealed body 300 be originally integrated between adjacent chips 200, forms each independently chip 200; After removing described scribing film 400, the chip 200 namely defined as shown in Figure 1 encapsulates.Visible, in the bottom surface of each chip 200, do not encapsulate with plastic-sealed body 300, lack protection.
As shown in Figure 3, be the plastic package structure schematic diagram of existing another kind of semiconductor chip 200, the bottom of this chip 200 and periphery have plastic-sealed body 300 to encapsulate.The method for packing of this chip 200, as shown in Figure 4: step B1, B2, first silicon chip 100 cutting is formed to the individual chips 200 be separated, again by each chip 200 face down, be separately fixed on scribing film 400, make to leave certain interval between the position of each chip 200 and other chips 200, it is greatly spaced that this interval is positioned on silicon chip 100 than chip 200; Step B3, carries out injection moulding, makes plastic packaging material be filled in the interval location of adjacent chips 200 and cover described silicon chip 100 back side upwards completely, forms described plastic-sealed body 300; Step B4, B5, after removing scribing film 400, be that overall some chips 200 overturn by silicon chip 100 is connected by described plastic-sealed body 300, silicon chip 100 faced up; Step B6, B7, the metal line carrying out fan-out-type successively in silicon chip 100 front distributes (Fan-Out RDL) process and Passivation Treatment again; Step B8, B9, at silicon chip 100 front correspondence position implanting tin ball 230, form the top electrodes of chip 200; After testing chip 200, from silicon chip 100 front scribing, isolate some independently chips 200 as shown in Figure 3.The bottom of this chip 200 and periphery have plastic-sealed body 300 to protect, but its manufacture craft is very complicated.
Summary of the invention
The object of this invention is to provide a kind of chip-scale packaging method, obtain the chip-packaging structure all being encapsulated protection in chip bottom and periphery by plastic-sealed body.
In order to achieve the above object, technical scheme of the present invention is to provide a kind of chip-scale packaging method chip bottom and periphery encapsulated, and its bottom at each chip and periphery define the plastic-sealed body of protection; This method for packing comprises following steps:
Step 1, silicon chip prepare; The picture on surface of several chips in a slice front side of silicon wafer respective production, and this making silicon chip faces up;
Step 2, carry out thinning back side process at silicon chip back side;
Step 3, the back side of silicon chip is fixedly bonded on scribing film;
Step 4, from front side of silicon wafer scribing cutting, corresponding each chip to be separated; Those chips are connected by the scribing film of bottom surface, and keep the relative position that is positioned at each other on silicon chip and interval;
Step 5, by the silicon chip upside-down mounting of band scribing film, make the whole front side of silicon wafer after cutting be fixedly bonded on the end face of a two-sided tape downwards, afterwards described scribing film is removed; The bottom surface of described two-sided tape is adhesively fixed on a support lining plate or in other fixture;
Step 6, plastic packaging is carried out to silicon chip, make plastic packaging material fill up the interval location between adjacent chips from silicon chip back side, and cover all chip backs and form plastic-sealed body;
Step 7, by silicon wafer turnover, and from mutually bonding described support lining plate and two-sided tape, this silicon chip to be stripped down;
Step 8, at front side of silicon wafer upward, the position of corresponding each chip top electrode carries out planting ball;
Step 9, by reflow treatment, define some tin balls of those top electrodes corresponding;
Step 10, form each independently chip by scribing: by the plastic-sealed body that is coupled as one between adjacent chips separately, make the bottom of each chip and periphery leave certain described plastic-sealed body protection.
When described chip is MOSFET chip, in step 1, the silicon chip substrate front of this chip, includes silicon dioxide initial layers, the metal wiring layer of aluminum, and passivation layer; This of described chip faces up.
In step 2, after described silicon chip back side is thinning, then by back side burn into back side metallization technology, define certain thickness metal level at silicon chip back side.
When described chip is power device chip, in step 1, be also included in the metal line distribution process again that front side of silicon wafer carries out; The silicon chip substrate front of this chip, includes silicon dioxide initial layers, the metal line redistributing layer of aluminum, and passivation layer; This of described chip faces up.
In one embodiment, described two-sided tape possesses certain ductility, whole silicon chip upside-down mounting in step 5 after cutting and on the end face being fixedly bonded to two-sided tape after, also to carry out stretching a step of this adhesive tape, increase with the interval making chip mutual, facilitate follow-up plastic packaging material to inject the interval of this chip; Two-sided tape after stretching, its bottom surface is adhesively fixed on support lining plate or in other fixture, with the interval that chip after keeping stretching is mutual.
In step 3, described scribing film is ultraviolet light adhesive tape;
In step 5, described two-sided tape is hot stripping tape or ultraviolet light adhesive tape.
In step 5, the described support lining plate bonding with two-sided tape bottom surface is glass substrate or other silicon chips.
Compared with prior art, chip-scale packaging method of the present invention, with the manufacture craft of simple possible, obtains the chip-packaging structure all being encapsulated protection in chip bottom and periphery by plastic-sealed body.
Accompanying drawing explanation
Fig. 1 is existing a kind of schematic diagram arranging the semiconductor chip structure of plastic-sealed body at periphery;
Fig. 2 is the Making programme schematic diagram of chip shown in Fig. 1;
Fig. 3 is that existing another kind all arranges the schematic diagram of the semiconductor chip structure of plastic-sealed body at bottom and periphery;
Fig. 4 is the Making programme schematic diagram of chip shown in Fig. 3;
It is the chip-scale packaging method schematic flow sheet in embodiment 1 of chip bottom of the present invention and periphery encapsulating shown in Fig. 5 to Figure 14;
It is the chip-scale packaging method schematic flow sheet in example 2 of chip bottom of the present invention and periphery encapsulating shown in Figure 15 to Figure 24.
Embodiment
Below in conjunction with accompanying drawing, some execution modes of the present invention are described.
Embodiment 1
Chip-scale packaging method described in the present embodiment; be particularly useful for the chip package of MOSFET (metal oxide semiconductor field effect tube) or other similar semiconductor device, make the bottom of each chip 20 and periphery can both be undertaken protecting (Figure 14) by plastic-sealed body 30 encapsulating.
See shown in Fig. 5 to Figure 14, described method for packing comprises following steps:
Step 1, as shown in Figure 5, complete the front technique of silicon chip 10; At the front respective production picture on surface of several chips 20 of a silicon chip 10, and this making silicon chip 10 faces up; That is, make on silicon chip 10 substrate of each chip 20, to include silicon dioxide initial layers 11, the metal wiring layer 21 of aluminum, and the surface of passivation layer 22 upward.
Step 2, as shown in Figure 6, carry out thinning back side process at silicon chip 10 back side, then by back side burn into back side metallization technology, form certain thickness metal level 24 at silicon chip 10 back side.
Step 3, as shown in Figure 7, the ultraviolet light adhesive tape that has been sticked from below, as scribing film 40, makes this silicon chip 10 be fixed on this scribing film 40 by the described metal level 24 at the back side.
Step 4, as shown in Figure 8, from top to silicon chip 10 front scribing cutting, to be correspondingly separated each chip 20; Those chips 20 are connected by the scribing film 40 of bottom surface, and keep the relative position that is positioned at each other on silicon chip 10 and interval.
Step 5, as shown in Figure 9, by whole silicon chip 10 upside-down mounting after the cutting of band scribing film 40, and is fixedly bonded on the end face of an adhesive tape 50, is removed by described scribing film 40 afterwards; Described adhesive tape 50 is looped around the described metal wiring layer 21 in chip 20 front, the surface of passivation layer 22 and periphery and arranges, and contacts with the front of described initial layers 11.
In one embodiment, described adhesive tape 50 is two-sided tapes that bottom surface is adhesively fixed on a support lining plate 60, and this support lining plate 60 can be glass substrate or other silicon chips.This two-sided tape 50 can be hot stripping tape or ultraviolet light adhesive tape.Cutting forms the individual chips be separated and is fixedly bonded on the end face of described two-sided tape 50, and keeps the relative position that is positioned at each other on silicon chip 10 and interval.
In another embodiment, described adhesive tape 50 possesses good ductility, whole silicon chip 10 upside-down mounting in step 5 after cutting and on the end face being fixedly bonded to adhesive tape 50 after, also carry out a step of stretch tape 50, to increase the interval that chip 20 is mutual, the plastic packaging material in subsequent step is made easily to inject the interval of chip 20.Adhesive tape after stretching can be adhesively fixed on support lining plate 60 or in other fixture with the interval that chip 20 after keeping stretching is mutual.
Step 6, as shown in Figure 10, plastic packaging is carried out to silicon chip 10: from the plastic packaging material of top note, cover the end face adequate thickness of described two-sided tape 50, make this plastic packaging material fill up the interval location between adjacent chips 20 from silicon chip 10 back side, and cover the metal level 24 at all chip 20 back side.Thus, obtain encapsulating the back side (namely bottom finished product) of each chip 20 and the described plastic-sealed body 30 of periphery.
Step 7, as shown in figure 11, silicon chip 10 to be overturn, and from mutually bonding described support lining plate 60 with two-sided tape 50, this silicon chip 10 is stripped down.Now, by bottom chip 20 and the described plastic-sealed body 30 of adjacent chips 20 interval location, those chips 20 are coupled to one.
Step 8, as shown in figure 12, in silicon chip 10 front upward, on described metal wiring layer 21, the position of corresponding each chip 20 top electrodes carries out planting ball.
Step 9, as shown in figure 13, by reflow treatment, defines some tin balls 23 of those top electrodes corresponding.
Step 10, as shown in figure 14, form each independently chip 20 by scribing: by the plastic-sealed body 30 that is originally integrated between adjacent chips 20 separately, make the periphery of each chip 20 leave certain described plastic-sealed body 30 and protect.
So far, complete the encapsulation to chip 20, the bottom of each chip 20 and periphery have plastic-sealed body 30 to protect.
Embodiment 2
The present embodiment, is particularly useful for the chip package of power device (Power IC), makes the bottom of each chip 20 and periphery can both be undertaken protecting (Figure 24) by plastic-sealed body 30 encapsulating.
See shown in Figure 15 to Figure 24, described method for packing comprises following steps, wherein distinguishes to some extent in step 1 and step 2 and above-described embodiment, and other steps are similar:
Step 1, as shown in figure 15, complete the front technique of silicon chip 10, comprise its metal line distribution process (RDL) again; The respective production picture on surface of several chips 20 on a slice silicon chip 10, and this making silicon chip 10 faces up; That is, make on silicon chip 10 substrate of each chip 20, to include silicon dioxide initial layers 11, the metal line redistributing layer 25 of aluminum, and the surface of passivation layer 22 upward.
Step 2, as shown in figure 16, carry out thinning back side process at silicon chip 10 back side.
Step 3, as shown in figure 17, the ultraviolet light adhesive tape that has been sticked from below, as scribing film 40, makes the back side of this silicon chip 10 be fixedly bonded on this scribing film 40.
Step 4, as shown in figure 18, from top to silicon chip 10 front scribing, to be correspondingly separated each chip 20; Those chips 20 are connected by the scribing film 40 of bottom surface.
Step 5, as shown in figure 19, will silicon chip 10 upside-down mounting of band scribing film 40, and is fixedly bonded on the end face of an adhesive tape 50, is removed by described scribing film 40 afterwards; Described adhesive tape 50 is looped around the described metal line redistributing layer 25 in chip 20 front, the surface of passivation layer 22 and periphery and arranges, and contacts with the front of described initial layers 11.
In one embodiment, described adhesive tape 50 is two-sided tapes that bottom surface is adhesively fixed on a support lining plate 60, and this support lining plate 60 can be glass substrate or other silicon chips.This two-sided tape 50 can be hot stripping tape or ultraviolet light adhesive tape.Cutting forms the individual chips be separated and is fixedly bonded on the end face of described two-sided tape 50, and keeps the relative position that is positioned at each other on silicon chip 10 and interval.
In another embodiment, described adhesive tape 50 possesses good ductility, whole silicon chip 10 upside-down mounting in step 5 after cutting and on the end face being fixedly bonded to adhesive tape 50 after, also carry out a step of stretch tape 50, to increase the interval that chip 20 is mutual, the plastic packaging material in subsequent step is made easily to inject the interval of chip 20.Adhesive tape after stretching can be adhesively fixed on support lining plate 60 or in other fixture with the interval that chip 20 after keeping stretching is mutual.
Step 6, as shown in figure 20, plastic packaging is carried out to silicon chip 10: from the plastic packaging material of top note, cover the end face adequate thickness of described two-sided tape 50, make this plastic packaging material fill up the interval location between adjacent chips 20 from silicon chip 10 back side, and cover all chip 20 back side.Thus, obtain encapsulating the back side (namely bottom finished product) of each chip 20 and the described plastic-sealed body 30 of periphery.
Step 7, as shown in figure 21, silicon chip 10 to be overturn, and from mutually bonding described support lining plate 60 with two-sided tape 50, this silicon chip 10 is stripped down.Now, by bottom chip 20 and the described plastic-sealed body 30 of adjacent chips 20 interval location, those chips 20 are coupled to one.
Step 8, as shown in figure 22, in silicon chip 10 front upward, on described metal line redistributing layer 25, the position of corresponding each chip 20 top electrodes carries out planting ball.
Step 9, as shown in figure 23, by reflow treatment, defines some tin balls 23 of those top electrodes corresponding.
Step 10, as shown in figure 24, form each independently chip 20 by scribing: by the plastic-sealed body 30 that is originally integrated between adjacent chips 20 separately, make the periphery of each chip 20 leave certain described plastic-sealed body 30 and protect.
So far, complete the encapsulation to chip 20, the bottom of each chip 20 and periphery have plastic-sealed body 30 to protect.
Although content of the present invention has done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.After those skilled in the art have read foregoing, for multiple amendment of the present invention and substitute will be all apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (7)
1. by the chip-scale packaging method that chip bottom and periphery are encapsulated, it is characterized in that, define the plastic-sealed body (30) of protection in the bottom of each chip (20) and periphery; This method for packing comprises following steps:
Step 1, silicon chip (10) prepare; The picture on surface of several chips (20) in a slice silicon chip (10) front respective production, and this making silicon chip (10) faces up;
Step 2, carry out thinning back side process at silicon chip (10) back side;
Step 3, the back side of silicon chip (10) is fixedly bonded on scribing film (40);
Step 4, from silicon chip (10) front scribing cutting, corresponding each chip (20) to be separated; Those chips (20) are connected by the scribing film (40) of bottom surface, and keep the relative position that is positioned at each other on silicon chip (10) and interval;
Step 5, will with the silicon chip of scribing film (40) (10) upside-down mounting, on the end face whole silicon chip (10) after cutting being faced down be fixedly bonded to a two-sided tape (50), afterwards described scribing film (40) is removed; The bottom surface of described two-sided tape (50) is adhesively fixed on a support lining plate (60) or in other fixture;
Step 6, plastic packaging is carried out to silicon chip (10), make plastic packaging material fill up the interval location between adjacent chips (20) from silicon chip (10) back side, and cover all chips (20) back side formation plastic-sealed body (30);
Step 7, silicon chip (10) to be overturn, and from mutually bonding described support lining plate (60) and two-sided tape (50), this silicon chip (10) is stripped down;
Step 8, in silicon chip (10) front upward, the position of corresponding each chip (20) top electrodes carries out planting ball;
Step 9, by reflow treatment, define some tin balls (23) of those top electrodes corresponding;
Step 10, form each independently chip (20) by scribing: by the plastic-sealed body (30) that is coupled as one between adjacent chips (20) separately, make the bottom of each chip (20) and periphery leave certain described plastic-sealed body (30) protection.
2. described in claim 1 by chip bottom and periphery encapsulating chip-scale packaging method, it is characterized in that,
Described chip (20) is MOSFET chip, in step 1, silicon chip (10) substrate face of this chip (20), includes silicon dioxide initial layers (11), the metal wiring layer (21) of aluminum, and passivation layer (22); This of described chip (20) faces up.
3. described in claim 2 by chip bottom and periphery encapsulating chip-scale packaging method, it is characterized in that,
In step 2, after described silicon chip (10) thinning back side, then by back side burn into back side metallization technology, define certain thickness metal level (24) at silicon chip (10) back side.
4. described in claim 1 by chip bottom and periphery encapsulating chip-scale packaging method, it is characterized in that,
Described chip (20) is power device chip, in step 1, is also included in the metal line distribution process again of carrying out in silicon chip (10) front; Silicon chip (10) substrate face of this chip (20), includes silicon dioxide initial layers (11), the metal line redistributing layer (25) of aluminum, and passivation layer (22); This of described chip (20) faces up.
5. described in claim 3 or 4 by chip bottom and periphery encapsulating chip-scale packaging method, it is characterized in that,
Described two-sided tape (50) possesses certain ductility, whole silicon chip (10) upside-down mounting in step 5 after cutting and on the end face being fixedly bonded to two-sided tape (50) after, also to carry out stretching the step of this two-sided tape (50), increase with the interval making chip (20) mutual, facilitate follow-up plastic packaging material to inject the interval of this chip (20);
The bottom surface of the two-sided tape (50) after stretching, is adhesively fixed in upper or other fixture of support lining plate (60) to keep the interval that chip (20) is mutual afterwards that stretches.
6. described in claim 5 by chip bottom and periphery encapsulating chip-scale packaging method, it is characterized in that,
In step 3, described scribing film (40) is ultraviolet light adhesive tape;
In step 5, described two-sided tape (50) is hot stripping tape or ultraviolet light adhesive tape.
7. described in claim 5 by chip bottom and periphery encapsulating chip-scale packaging method, it is characterized in that,
In step 5, the described support lining plate (60) bonding with two-sided tape (50) bottom surface is glass substrate or other silicon chips.
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| US10181423B2 (en) | 2012-10-02 | 2019-01-15 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of using a standardized carrier in semiconductor packaging |
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| US9496195B2 (en) | 2012-10-02 | 2016-11-15 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of depositing encapsulant along sides and surface edge of semiconductor die in embedded WLCSP |
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| CN106783642A (en) * | 2016-12-29 | 2017-05-31 | 华进半导体封装先导技术研发中心有限公司 | A kind of chip and its method for packing |
| CN107342256A (en) * | 2017-06-26 | 2017-11-10 | 矽力杰半导体技术(杭州)有限公司 | Semiconductor technology and semiconductor structure |
| CN110098160A (en) * | 2019-02-26 | 2019-08-06 | 上海朕芯微电子科技有限公司 | A kind of wafer-level packaging chip and preparation method thereof |
| CN110676183A (en) * | 2019-10-10 | 2020-01-10 | 广东佛智芯微电子技术研究有限公司 | Fan-out type packaging method for reducing plastic deformation of chip |
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