CN102866389A - Double-channel radar echo simulator and method and system for generating double-channel radar echo signal - Google Patents
Double-channel radar echo simulator and method and system for generating double-channel radar echo signal Download PDFInfo
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Abstract
The invention discloses a double-channel radar echo simulator as well as a method and a system for generating a double-channel radar echo signal. In the double-channel radar echo simulator, a frequency integrator is used for supplying a clock signal; a field programmable gate array (FPGA) control circuit transmits a control signal to a first digital display scope (DDS) and a second DDS; the first DDS and the second DDS respectively receive the control signal transmitted by the FPGA control circuit and respectively output a first middle-frequency signal and a second middle-frequency signal to a first upper frequency converter and a second upper frequency converter; the first upper frequency converter performs upper frequency conversion on the first middle-frequency signal to obtain a first radio frequency signal; the second upper frequency converter performs upper frequency conversion on the second middle-frequency signal to obtain a second radio frequency signal; and a power distributing network receives the first radio frequency signal and the second radio frequency signal and decomposes the first radio frequency and the second radio frequency signal. By setting two signal processing paths, different delayed interference specific absorption rate (SAR) echo signals are generated according to the variation of a distance between a radar and a measured target.
Description
Technical field
The present invention relates to the radar echo simulation field, especially relate to a kind of Two-channels radar echo simulator, in addition, also related to the method and system that produces the Two-channels radar echoed signal.
Background technology
Radar utilizes electromagnetic wave to detect target in the reflection of body surface.Judge the distance of target according to the time delay of target echo signal, determine the orientation of target according to beam position.Early stage radar resolution is very low, and resolution element greater than the size of target, can only be considered as point target with target usually.Original radar concept has been expanded in the appearance of imaging radar.Radar is had moving target and regional aim are had the ability of identification and imaging, and aspect microwave remote sensing, show increasing potentiality.Than traditional optical imagery, radar has round-the-clock, the advantage such as round-the-clock.
The concept of synthetic aperture radar (SAR) is to be taken the lead in proposing in nineteen fifty-one by the Carl Wiley of U.S. Goodyear company.Synthetic-aperture radar is a kind of high-resolution microwave imaging system, occupies an important position in the microwave remote sensing field.Synthetic-aperture radar by distance upwards emission have large time the long-pending signal of wide bandwidth, then adopt pulse compression to obtain the high resolving power that distance makes progress; Upwards utilize the track of the relative motion formation of target and radar to consist of synthetic aperture in the orientation, obtain high azimuth resolution with this.Through nearly 60 years development, the function of SAR strengthens greatly, makes it not only be used for military surveillance, also is applied to the civil areas such as remote sensing, geology topographic mapping, oceanographic observation, environmental monitoring simultaneously.Development along with technology, the function of SAR is greatly expanded, appearing as of binary channels interference SAR realizes that dimensional topography mapping, moving object detection etc. provide good technological means, and increasing effect is being brought into play in binary channels interference SAR dual-use field at home and abroad.
The development of radar echo simulator is the inevitable demand of Radar Technology development, and along with improving constantly of radar performance, simultaneously radar application scene and environment is complicated, diversified, and the test problem of radar performance is shown especially out gradually.In development process, need to detect and verify by test of many times the quality of radar serviceability.Traditional method is to do field trial with aircraft, and the test data of radar is provided, but field testing consumes more human and material resources, financial resource, pay a price very large, and field testing can't provide test data under the various complex situations.Therefore, obtaining the radar return data by analog simulation is very important approach.Radar echo simulator is take actual measurement or ideal data as prototype, and the echoed signal that radar receives under the analog simulation true environment can save experimentation cost, accelerate Development Schedule, has great importance for design, debugging and the Performance Evaluation etc. of radar.
Yet existing radar echo simulator can only produce one tunnel echoed signal.Therefore, the present invention is directed to the defective that prior art exists, a kind of Two-channels radar echo simulator is provided.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of Two-channels radar echo simulator, it can produce the identical or different echoed signal of two-way phase place, also can produce the echoed signal of two-way fixed skew, can also according to the variation of radar and measured target distance, produce the different interference SAR echoed signals that postpone; In addition, also provide a kind of method and a kind of Two-channels radar echoed signal that produces the Two-channels radar echoed signal to produce system.
For solving the problems of the technologies described above, the invention provides a kind of Two-channels radar echo simulator, it comprises power supply, frequency synthesizer, FPGA control circuit, a DDS, the 2nd DDS, the first upconverter, the second upconverter and power division network, and this power supply is used for frequency synthesizer, a DDS, the 2nd DDS, FPGA control circuit, the first upconverter and the second upconverter are powered; This frequency synthesizer is used for being respectively FPGA control circuit, a DDS, the 2nd DDS, the first upconverter and the second upconverter provides clock signal; The FPGA control circuit transmits control signal to a DDS and the 2nd DDS, respectively a DDS and the 2nd DDS is triggered control; The one DDS receives the control signal that the FPGA control circuit sends, and exports the first intermediate-freuqncy signal, and exports the first upconverter to; The 2nd DDS receives the control signal that the FPGA control circuit sends, and exports the second intermediate-freuqncy signal, and exports the second upconverter to; The first upconverter is carried out up-conversion to the first intermediate-freuqncy signal, obtains the first radiofrequency signal; The second upconverter is carried out up-conversion to the second intermediate-freuqncy signal, obtains the second radiofrequency signal; Power division network receives the first radiofrequency signal and the second radiofrequency signal, and be two tunnel the 1 branch signals with the first radio-frequency signal decomposition, wherein one tunnel the 1 branch signal is decomposed into two tunnel the 1 branch signals again, and be two tunnel the 2 1/2 branch signals with the second radio-frequency signal decomposition, wherein the phase place of two tunnel described the one 1/4 branch signals is consistent, has phase differential between the one 1/2 branch signal and the 2 1/2 branch signal.
Preferably, this FPGA control circuit comprises fpga chip; Fpga chip comprises serial communication modular, register, dual port RAM, AD stochastic sampling module and DDS control module; Wherein, serial communication modular is got 2 operational processes for the data that receive are carried out 3; Register is used for storing the data that described serial communication modular receives; Dual port RAM is used for realizing the delay of trigger pip; AD stochastic sampling module is used for noise is sampled, to determine the address date of radar emission signal among a DDS and the 2nd DDS; The DDS control module cooperates with dual port RAM, is used for coming described trigger pip is postponed output according to altitude information, and selects radar emission signal among a DDS and the 2nd DDS according to the data in the register.
A kind of method that produces the Two-channels radar echoed signal that the present invention also provides comprises: first via radar return baseband signal is carried out up-conversion, form the first intermediate-freuqncy signal; The the second road radar return baseband signal is carried out up-conversion, form the second intermediate-freuqncy signal, wherein, have phase differential between the second road radar return baseband signal and the first via radar return baseband signal; The first intermediate-freuqncy signal is carried out up-conversion, obtain the first radiofrequency signal; The second intermediate-freuqncy signal is carried out up-conversion, obtain the second radiofrequency signal; Be two tunnel the 1 branch signals with the first radio-frequency signal decomposition, wherein one tunnel the 1 branch signal is decomposed into two tunnel the 1 branch signals again; Be two tunnel the 2 1/2 branch signals with the second radio-frequency signal decomposition; Choose one tunnel the 1 branch signal, two tunnel the 1 branch signals, one tunnel the 2 1/2 branch signal as radar echo signal.
Preferably, first via radar return baseband signal and the second road radar return baseband signal are selected from a DDS and the 2nd DDS by following steps: noise is sampled, to determine to select the address date of first via radar return baseband signal and the second road radar return baseband signal; Come trigger pip is postponed output according to altitude information, regulating the generation time of radar emission signal, and select described first via radar return baseband signal and the second road radar return baseband signal according to address date.
A kind of system that produces the Two-channels radar echoed signal provided by the invention comprises: host computer and above-mentioned Two-channels radar echo simulator; This host computer comprises the PC control device, and the PC control device comprises: reseting module, preparation module, monodrome sending module, file send module and parameter generating and sending module; Wherein, reseting module sends reseting data to the FPGA chip; Preparation module is used for calculating binary data corresponding to altitude information that receives, and delay time data between the actual height single-value data that sends and per two the height single-value datas; The monodrome sending module is used for sending the height single-value data that is calculated by preparation module; File send module comprises: Transmit message selects module, file to send the beginning module, file sends and finishes module; Wherein, Transmit message selects module to be used for selecting the height file data; File sends the beginning module and sends the height file data; File sends and finishes the transmission that module is used for finishing current altitude information file; Parameter generating and sending module comprise: trigger pip selects module, transmitted waveform to select module and transmission lag module; Wherein, trigger pip selects module to be used for selecting internal trigger signal or outer triggering signal; Transmitted waveform selects module to be used for from the transmitted waveform of a DDS and the 2nd DDS selection pre-stored; The transmission lag module is used for the transmission time interval between two altitude informations of selection.
Preferably, the PC control device also comprises: waveform generation module and waveform download module; Wherein, the waveform generation module is used for generating the first and second radar return baseband signals; The waveform download module is used for the radar return baseband signal is downloaded to a DDS and the 2nd DDS.
Compared with prior art, the present invention has the following advantages:
Because the embodiment of the invention is provided with two direct digital synthesisers, two upconverter and a power division network, pass through again the control of FPGA control circuit, form two paths of processing respectively the two-way radar return baseband signal with phase differential, can produce the identical or different echoed signal of two-way phase place, also can produce the echoed signal of two-way fixed skew, and export to the two-channel receiver of binary channels interferometer radar (particularly interference SAR radar system), two channel phase consistencies that are used for test receiver, and the performance of checking receiver, and, the embodiment of the invention can be observed the radar return of different distance target in simulation loading platform motion process.
Simultaneously, the embodiment of the invention can according to the variation of distance between binary channels interferometer radar and the measured target, produce the different interference SAR echoed signals that postpone.
According to the altitude information that host computer sends, embodiment provided by the invention can be used for the track algorithm of test binary channels interferometer radar.
Other features and advantages of the present invention will be set forth in the following description, and partly become apparent from instructions, perhaps understand by implementing the present invention.Purpose of the present invention and other advantages can realize and obtain by specifically noted structure in claims, instructions and accompanying drawing thereof.
Description of drawings
Fig. 1 is the system framework schematic diagram of Two-channels radar echo simulator of the present invention;
Fig. 2 is FPGA control device system framework schematic diagram of the present invention;
Fig. 3 is the communication scheme between PC control device of the present invention and the FPGA chip;
Fig. 4 is the operating process in radar echo simulator when work of the embodiment of the invention.
Embodiment
Below in conjunction with concrete drawings and Examples the present invention is done detailed elaboration.
The system of the generation Two-channels radar echoed signal that the embodiment of the invention provides comprises: host computer and Two-channels radar echo simulator.
Fig. 1 has shown the system framework schematic diagram of Two-channels radar echo simulator.This Two-channels radar echo simulator comprises: power supply (not shown), frequency synthesizer, FPGA control circuit, a DDS(the first Direct Digital Synthesizer), the 2nd DDS(the second Direct Digital Synthesizer), the first upconverter, the second upconverter and power division network.
Power supply converts the 220V alternating voltage to DC voltage, be used for providing+12V/1A ,+15V/3A ,+5V/3A ,-the 5V/1A direct current, and frequency synthesizer, a DDS, the 2nd DDS, FPGA control circuit, the first upconverter and the second upconverter powered.
Frequency synthesizer is not when having outside 100MHz reference clock input, utilize the crystal oscillator of self to produce 75MHz clock signal, 100MHz clock signal, 1.03GHz clock signal, 12.55GHz clock signal, and in the situation that the input of external reference clock is arranged, the inside crystal oscillator of frequency synthesizer is not worked, and the various clock signals that are concerned with external timing signal can be provided, and produce the clock signal of 75MHz, 100MHz, 1.03GHz, four kinds of frequencies of 12.55GHz.
The FPGA control circuit comprises FPGA chip, AD(modulus) acquisition chip, level transferring chip, serial ports, the FPGA chip comprises serial communication modular, register, dual port RAM, AD stochastic sampling module, DDS control module and internal trigger signal generator module.The FPGA control circuit links to each other with computing machine by serial ports.The 100MHz clock signal that the FPGA control circuit provides with frequency synthesizer is as the clock signal of fpga chip, utilize fpga chip, according to serial communication protocol, receive the supplemental characteristic (selecting data, transmitted waveform to select data, transmission lag time data such as height single-value data, height file data, trigger pip) that the PC control device sends by serial ports; The FPGA control circuit transmits control signal to a DDS and the 2nd DDS, and a DDS and the 2nd DDS are triggered control.Wherein, control signal comprises a trigger pip and two address signals, and trigger pip both can be that the internal trigger signal also can be outer triggering signal.The internal trigger signal is to be produced by the internal trigger signal generator module of fpga chip inside; Outer triggering signal is produced by the external trigger source.The DDS control module of fpga chip inside is carried out certain delay according to altitude information (that is: height single-value data and height file data) to trigger pip, then the DDS control module trigger pip that will be delayed certain hour is exported to respectively a DDS and the 2nd DDS, and is used for triggering control the one DDS and the 2nd DDS; Two address signals are used for selecting the waveform of a DDS or the 2nd DDS pre-stored.
Pre-stored among the one DDS and the 2nd DDS have a radar emission signal (as the radar return baseband signal) with phase differential, specifically four radar emission waveforms (also i.e. first to fourth radar return baseband signal).In essence, radar echo signal is exactly with the signal after the delay that transmits of radar.If the designer is at the design radar, when needing the transradar system, just need to generate the radar emission signal that is fit to this radar system, this radar emission signal can be produced and be downloaded among a DDS and the 2nd DDS by the waveform download module by the waveform generation module in the host computer this moment.The one DDS and the 2nd DDS respectively with 75MHz as the base band local oscillation signal, this base band local oscillation signal is as the clock signal of a DDS and the 2nd DDS.The frequency of the 1.03GHz clock signal that the one DDS provides with frequency synthesizer is as local frequency, the first radar return baseband signal that waveform download module by pre-stored or host computer among the DDS downloads is carried out up-conversion, be transformed into the first intermediate-freuqncy signal (i.e. an IF signal), wherein the first radar return baseband signal comprises an I road radar return baseband signal and a Q road radar return baseband signal.The frequency of the 1.03GHz clock signal that the 2nd DDS provides with frequency synthesizer is as local frequency, the second radar return baseband signal that waveform download module by pre-stored or host computer among the 2nd DDS downloads is carried out up-conversion, be transformed into the second intermediate-freuqncy signal, wherein the second radar return baseband signal comprises the 2nd I road radar return baseband signal and the 2nd Q road radar return baseband signal.The one DDS exports an I road radar return baseband signal, Q road radar return baseband signal and first intermediate-freuqncy signal, and exports the first upconverter under the triggering control of FPGA control circuit; The 2nd DDS exports the 2nd I road radar return baseband signal, the 2nd Q road radar return baseband signal and the second intermediate-freuqncy signal, and exports the second upconverter under the triggering control of FPGA control circuit; Wherein, the I road represents in-phase branch, and the Q road represents quadrature branch, has certain phase differential between an I road radar return baseband signal and the 2nd I road radar return baseband signal, a Q road radar return baseband signal and the 2nd Q road radar return baseband signal; Whether the I road radar return baseband signal of the one DDS and the 2nd DDS output and Q road radar return baseband signal are used for the check intermediate-freuqncy signal correct.
The frequency of the 12.55GHz clock signal that the first upconverter provides with frequency synthesizer is as local frequency, and the first intermediate-freuqncy signal of DDS output is carried out up-conversion, then exports the first radiofrequency signal (i.e. a RF signal).
The frequency of the 12.55GHz clock signal that the second upconverter provides with frequency synthesizer is as local frequency, and the second intermediate-freuqncy signal of the 2nd DDS output is carried out up-conversion, then exports the second radiofrequency signal (i.e. the 2nd RF signal).
Power division network comprises three power splitters, and the power splitter full name is power divider, and it is used for one road input signal being become two paths of signals and exporting.The first upconverter sends the first radiofrequency signal to the first power splitter of power division network, the first power splitter becomes two-way 1/2 branch signal with this first radio-frequency signal decomposition, and then one tunnel 1/2 branch signal of the first power splitter output inputed to the second power splitter, this second power splitter resolves into two-way 1/4 branch signal with this 1/2 branch signal; The second upconverter sends the second radiofrequency signal to the 3rd power splitter of power division network, and the 3rd power splitter becomes two-way 1/2 branch signal with this second radio-frequency signal decomposition.One tunnel 1/2 branch signal of two-way 1/4 branch signal of one tunnel 1/2 branch signal of the first power splitter output, the output of the second power splitter and the output of the 3rd power splitter is as radar echo signal, and exported by power division network.Wherein, the phase place of two-way 1/4 branch signal of the second power splitter output is in full accord; The phase differential of 1/2 branch signal of one tunnel 1/2 branch signal of the first power splitter output and the output of the 3rd power splitter is fixed, and 1/2 fixing branch signal of this two-way phase differential can obtain by the radar return baseband signal of pre-stored among a DDS and the 2nd DDS is adjusted.The radar echo signal of this power division network output can be sent to the two-channel receiver of binary channels interferometer radar (referring to especially the interference SAR radar system), with whether consistent for the phase place of two passages testing two-channel receiver, and the performance of checking two-channel receiver.In addition, the first power splitter and the 3rd power splitter be output signal simultaneously, to be used for carrying out the interference of radar echo signal.
Host computer refers to that the people can directly send the computing machine of controlling order.Host computer comprises: PC control device, waveform generation module and waveform download module.Wherein, just need to produce the radar return baseband signal that is fit to this radar system when the improper radar system of waveform pre-stored among a DDS and the 2nd DDS, this radar return baseband signal is produced by the waveform generation module.The parameters such as characteristic, destination number and clutter of the target that the waveform generation module arrives according to radar illumination are adjusted frequency, the parameter such as signal period, generate the radar return baseband signal.The waveform download apparatus is by SPI(synchronous serial Peripheral Interface) communication protocol, the radar return baseband signal is downloaded among a DDS and the 2nd DDS.
The PC control device passes through serial communication protocol, send the supplemental characteristics such as reseting data, height single-value data, height file data, transmitted waveform selection data and trigger pip selection data to the FPGA control circuit, and be defeated by the FPGA chip through serial communication modular and process; Be used for selecting internal trigger signal or outer triggering signal for supplemental characteristic " trigger pip selection ".Wherein the internal trigger signal shows that this trigger pip is produced by the FPGA control circuit, and outer triggering signal shows that this trigger pip is produced by the external trigger source.
Because the height on satellite distance ground is between 300km ~ 490km, the resolution that needs is 1.5m.In the process of transmitting of reality, only needing to send effective altitude range is that 0km ~ 190km gets final product, 16 system numbers with respect to 1.5 meters are 0x0000000 ~ 0x0001EECA, because serial ports once can only send the data of a 8bit, therefore, the data that height value resolved into 4 8bit send (sending order by high byte to low byte).In order to distinguish height single-value data, height file data and supplemental characteristic, need add a sign in valid data front of every transmission.Wherein, the height single-value data comprises an altitude information; The height file data comprises a plurality of height single-value datas, and the expression satellite is the distance apart from ground in the difference moment; Supplemental characteristic comprises trigger pip selection data, transmitted waveform selection data and transmission lag time data.Table 1 has shown the corresponding sign of transmission different parameters data.
Table 1
| Reseting data | （255,255,255,255） |
| Supplemental characteristic | （254,254,254,254） |
| The height single-value data | （253,253,253,253） |
| The height file data | （252,252,252,252） |
Fig. 3 shows is communication scheme between PC control device and the fpga chip.
The PC control device comprises: reseting module, preparation module, monodrome sending module, file send module, parameter generating and sending module, reception display module.
Reseting module sends reseting data " 255; 255; 255,255,0; 0; 0,0 " to fpga chip, after the FPGA chip is received reseting data, make the FPGA register return to default parameters (that is: the altitude information register is value corresponding to 300KM, and DDS address date register is address corresponding to first paragraph waveform).
Preparation module receives a height value at the altitude information of 300000～490000 scopes, calculate simultaneously the binary data of nybble corresponding to this height value (8bit), and the actual height single-value data that sends and radar echo signal delay time data corresponding to height single-value data.Radar echo signal is calculated by height value time delay, and its value is very little, is generally several milliseconds.Height value represents the satellite of 300km～490km scope apart from the distance on ground at the altitude information of 300000～490000 scopes.The height resolution of the echo simulator of a kind of embodiment provided by the invention is 1.5 meters, and then numerical value 1 represents 1.5 meters, and numerical value 2 represents 3 meters, by that analogy.After preparation module is artificially triggered, if the data of input have exceeded the scope (namely 300000 ~ 490000) of regulation, then receive display module demonstration " satellite altitude Data Out of Range! "; If the data of input within the limits prescribed, then receive display module and show that " the satellite altitude input is correct! ".The computing formula of above-mentioned time delay is:
Wherein h be in the binary channels interferometer radar operational process apart from the height of substar, c=299792458m/s is the speed of Electromagnetic Wave Propagation, θ is the downwards angle of visibility of radar antenna, t be radar return and transmit between delay.
The monodrome sending module is used for sending the height single-value data that is calculated by preparation module, and the monodrome sending module sends first sign " 253,253; 253; 253 ", then once sends the data of 4 bytes corresponding to height single-value data, and sends according to the order from the high byte to the low byte.
File send module comprises: Transmit message selects module, file to send the beginning module, file sends and finishes module; Wherein, Transmit message is selected the height file data of module selection PC control device generation and is shown in real time by receiving display module; File sends the beginning module and sends the height file data, and the rule of transmission is to send first sign " 252,252,252,252 ", then sends successively the data of corresponding 4 bytes of each altitude information, sending order by high byte to low byte; File sends and finishes the transmission that module is used for finishing current altitude information file.
Parameter generating and sending module comprise: trigger pip selects module, transmitted waveform to select module and transmission lag module.Wherein, trigger pip selects module to be used for selecting internal trigger signal or outer triggering signal.Transmitted waveform selects module to be used for from the waveform of a DDS and the 2nd DDS selection pre-stored.The transmission lag module is used for from the transmission time interval (also being time delay) between three adjacent two altitude informations of time selection of 500ms, 1000ms, 1500ms of being set by host computer.Table 2 has shown according to different transmitted waveforms, transmitted waveform quantity and different trigger pips and the data value that sends to FPGA.In table 2, first single waveform is selected in " 1 waveform-first waveform " expression, and second single waveform selected in " 1 waveform-second waveform " expression, by that analogy; " random (four waveforms) " expression is selected from four waveforms randomly; Two waveforms are selected in " 2 waveforms " expression, and other by that analogy.The data value that the data value that " 0,0,240,0 " expression sends when selecting first single waveform and selecting the internal trigger signal, " 0,0,15,0 " expression send when selecting first single waveform and selecting outer triggering signal, other by that analogy.
Table 2
Receive display module and be used for receiving and showing the data that fpga chip feeds back, these data that feed back are exactly the data that PC control device in the host computer sends to the fpga chip in the FPGA control circuit, for example altitude information.
The FPGA chip comprises serial communication modular, register, dual port RAM, AD stochastic sampling module, DDS control module and internal trigger signal generator module.
Serial communication modular receives the data (for example: reseting data, supplemental characteristic, height single-value data and height file data) of sending from the PC control device according to serial communication protocol.Serial communication modular is deposited these data respectively in the different registers according to different signs, after " 3 get 2 operations " processing, again according to serial communication protocol data feedback to the PC control device, then show by the reception display module in the PC control device.So-called " 3 get 2 operations " processed and referred to: select data, trigger pip to select the supplemental characteristics such as data reseting data, height single-value data, height file data and transmitted waveform that the PC control device produces, send three times, through serial communication modular input FPGA chip, from the cubic parametric data that send, get the equal supplemental characteristic of data value twice, if there is no twice equal situation of supplemental characteristic then given up this supplemental characteristic.
The every certain interval of time of AD stochastic sampling module (this time is artificial the setting) is once sampled to noise, determine the address date of radar emission signal among a DDS and the 2nd DDS according to the noise of sampling, then AD stochastic sampling module sends trigger pip and address date to the DDS control module.
The DDS control module is come inside/outer triggering signal is postponed output accordingly according to altitude information, the design of signal delay adopts the dual port RAM in the fpga chip to design, for example can allow the mouth of inside/outside trigger pip from dual port RAM input, then from another mouthful output, reach the purpose of delay, thereby can be artificially according to postponing numerical value, the generation time of the radar return that automatically adjusts; Simultaneously, select radar emission signal corresponding with this two bits among a DDS and the 2nd DDS according to the minimum two bits of the address date in the register, wherein, when module selection " random (four waveforms) " (seeing Table 2) was selected in the transmitted waveform in the PC control device, the address date in the register was sent by AD stochastic sampling module; When the transmitted waveform in the PC control device selected module to select other waveform, the address date in the register sent " transmitted waveform selection " parameter according to host computer and obtains.Radar echo signal corresponding to altitude information with different time delays, the satellite altitude that different radar echo signals is corresponding different.
The internal trigger signal generator module is for generation of the internal trigger signal, and trigger pip is 1024 pulses, and the duration of pulse is 50us, interval 10us, and trigger pip can be used for the self-test of system performance.
Fig. 4 has shown the operating process the when radar echo simulator of the embodiment of the invention is worked, and this operating process is:
Step S1: connect the 220V AC power;
Step S2: open switch, plugged is powered;
Step S3: connect outer triggering signal;
Step S4: connect external timing signal;
Step S5: the PC control device sends supplemental characteristic (as: height single-value data, height file data, transmitted waveform quantity, trigger pip are selected, dead time) to the FPGA control circuit, check between host computer and the FPGA control circuit communicate by letter whether correct;
Step S6: from a DDS and the 2nd DDS, select the radar emission waveform in the waveform of pre-stored;
Step S7: if there is not pre-stored radar emission waveform among a DDS and the 2nd DDS, then to a DDS and the 2nd DDS stored transmit waveform, otherwise skip this step;
Step S8:FPGA control circuit transmits control signal for a DDS and the 2nd DDS;
Step S9: whether the time-delay to the synchronous trigger pip of exporting of a DDS, the 2nd DDS is correct respectively to utilize oscillograph observation FPGA control circuit;
Step S10: utilize oscillograph to observe the output of the radar return baseband signal of storing among a DDS and the 2nd DDS whether normal;
Step S11: utilize frequency spectrograph observation radiofrequency signal whether to export normally.
It should be noted last that, above embodiment is only unrestricted in order to technical scheme of the present invention to be described.Although with reference to embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that, technical scheme of the present invention is made amendment or is equal to replacement, do not break away from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (6)
1. Two-channels radar echo simulator, it comprises power supply;
It is characterized in that:
This Two-channels radar echo simulator also comprises: frequency synthesizer, the FPGA control circuit with fpga chip, a DDS, the 2nd DDS, the first upconverter, the second upconverter and power division network; Wherein,
Described frequency synthesizer, it is used for being respectively described fpga chip, a described DDS, described the 2nd DDS, described the first upconverter and described the second upconverter provides clock signal;
Described FPGA control circuit, it transmits control signal to a described DDS and described the 2nd DDS, respectively a described DDS and described the 2nd DDS is triggered control;
A described DDS, it receives the control signal that described FPGA control circuit sends, and exports the first intermediate-freuqncy signal, and exports described the first upconverter to;
Described the 2nd DDS, it receives the control signal that described FPGA control circuit sends, and exports the second intermediate-freuqncy signal, and exports described the second upconverter to;
Described the first upconverter, it carries out up-conversion to described the first intermediate-freuqncy signal, obtains the first radiofrequency signal;
Described the second upconverter, it carries out up-conversion to described the second intermediate-freuqncy signal, obtains the second radiofrequency signal;
Described power division network, it receives described the first radiofrequency signal and described the second radiofrequency signal, and be two tunnel the 1 branch signals with described the first radio-frequency signal decomposition, wherein one tunnel described the one 1/2 branch signal is decomposed into two tunnel the 1 branch signals again, and be two tunnel the 2 1/2 branch signals with described the second radio-frequency signal decomposition, wherein the phase place of two tunnel described the one 1/4 branch signals is consistent, has phase differential between described the one 1/2 branch signal and described the 2 1/2 branch signal.
2. Two-channels radar echo simulator according to claim 1 is characterized in that, described FPGA control circuit comprises the FPGA chip; Described fpga chip comprises serial communication modular, register, dual port RAM, AD stochastic sampling module and DDS control module; Wherein,
Described serial communication modular, it is used for that the data that receive are carried out 3 and gets 2 operational processes;
Described register, it is used for storing the data that described serial communication modular receives;
Described dual port RAM, it is used for realizing the delay of trigger pip;
Described AD stochastic sampling module, it is used for noise is sampled, to determine the address date of radar emission signal among a described DDS and described the 2nd DDS;
Described DDS control module, it cooperates with described dual port RAM, be used for coming described trigger pip is postponed output according to altitude information, regulating the generation time of radar emission signal, and select radar emission signal among a described DDS and described the 2nd DDS according to the address date in the described register.
3. method that produces the Two-channels radar echoed signal is characterized in that:
The first radar return baseband signal is carried out up-conversion, form the first intermediate-freuqncy signal;
The second radar return baseband signal is carried out up-conversion, form the second intermediate-freuqncy signal, wherein, have phase differential between described the second road radar return baseband signal and the described first via radar return baseband signal;
Described the first intermediate-freuqncy signal is carried out up-conversion, obtain the first radiofrequency signal;
Described the second intermediate-freuqncy signal is carried out up-conversion, obtain the second radiofrequency signal;
Be two tunnel the 1 branch signals with described the first radio-frequency signal decomposition, wherein one tunnel described the one 1/2 branch signal is decomposed into two tunnel the 1 branch signals again;
Be two tunnel the 2 1/2 branch signals with described the second radio-frequency signal decomposition;
Choose one tunnel described the one 1/2 branch signal, two tunnel described the one 1/4 branch signals, one tunnel described the 2 1/2 branch signal as radar echo signal.
4. method according to claim 3, it is characterized in that: described first via radar return baseband signal and described the second road radar return baseband signal are selected from a DDS and the 2nd DDS by following steps:
Noise is sampled, to determine to select the address date of described first via radar return baseband signal and described the second road radar return baseband signal;
Come described trigger pip is postponed output according to altitude information, regulating the generation time of radar emission signal, and select described first via radar return baseband signal and described the second road radar return baseband signal according to described address date.
5. system that produces the Two-channels radar echoed signal, it is characterized in that: this system comprises: host computer and Two-channels radar echo simulator as claimed in claim 1 or 2;
Described host computer comprises the PC control device, and described PC control device comprises: reseting module, preparation module, monodrome sending module, file send module and parameter generating and sending module; Wherein,
Described reseting module, it sends reseting data to the FPGA chip;
Described preparation module, it is used for calculating binary data corresponding to altitude information that receives, and delay time data between the actual height single-value data that sends and per two the height single-value datas;
The monodrome sending module, it is used for sending the height single-value data that is calculated by preparation module;
File send module comprises: Transmit message selects module, file to send the beginning module, file sends and finishes module; Wherein,
Transmit message is selected module, and it is used for selecting the height file data;
File sends the beginning module and sends the height file data;
File sends and finishes the transmission that module is used for finishing current altitude information file;
Parameter generating and sending module comprise: trigger pip selects module, transmitted waveform to select module and transmission lag module; Wherein,
Trigger pip is selected module, and it is used for selecting internal trigger signal or outer triggering signal;
Module is selected in transmitted waveform, and it is used for from the transmitted waveform of a DDS and the 2nd DDS selection pre-stored;
The transmission lag module, it is used for the transmission time interval between two altitude informations of selection.
6. system according to claim 5, it is characterized in that: described PC control device also comprises: waveform generation module and waveform download module; Wherein, the waveform generation module is used for generating described the first and second radar return baseband signals; The waveform download module is used for described radar return baseband signal is downloaded to a described DDS and described the 2nd DDS.
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